The ADSP-BF531 /ADSP-BF532/ADSP-BF533 processors are members of the Blackfin® family of products, including Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine the advantages of a dual MAC state-of-the-art signal processing engine, clean, orthogonal RISClike microprocessor instruction set, and a single-instruction, multiple-data (SIMD) multimedia-capable integrated instruction-set architecture.

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are fully code and pin compatible, differing only in respect of their performance and on-chip memory.

feature

High-performance Blackfin processors up to 600 MHz Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifters RISC-like register and instruction model for easy programming and compilation Friendly support for advanced debugging , tracking and performance monitoring.

Programmable On-Chip Voltage Regulator

160-ball CSP_BGA, 169-ball PBGA and 176-pin LQFP package

Peripherals

Parallel peripheral interface PPI, support ITU-R 656 video data format 2 dual channels, full duplex synchronous serial port, support 8 stereo I2S channels

2 memory-to-memory DMAs

8 peripheral DMAs

SPI Compatible Port

Three 32-bit timer/counter real-time clock and watchdog timer with PWM support

32-bit core timer

Up to 16 general purpose I/O pins (GPIO)

UART supports IrDA

event handler

Debug/JTAG interface

On-chip PLL capable of frequency multiplication

Functional block diagram

Portable Low Power Architecture

Blackfin processors provide world-class power management and performance. Blackfin Processor Design Low Power and Low Voltage Design Methodologies and Features

Dynamic Power Management - Ability to vary the voltage and frequency of operation, thereby significantly reducing overall performance energy consumption. Changing the voltage and frequency can result in significantly lower power consumption compared to changing the operating frequency alone. This translates to longer battery life for portable devices.

System Integration The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are highly integrated system-on-chip solutions for next-generation digital communications and consumer multimedia applications. By combining industry-standard interfaces and high-performance signal processing cores, users can develop cost-effective solutions without costly external components. System peripherals include a UART port, SPI port, two serial ports (SPORTs), four general-purpose timers (three with PWM capability), a real-time clock, a watchdog timer, and a parallel peripheral interface.

Processor Peripherals

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors contain a rich set of peripherals that connect to the core through several high-bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see features in the diagram above Box. General purpose peripherals include functions such as a UART, timers with PWM (pulse width modulation) and pulse measurement capabilities, general purpose I/O pins, a real-time clock and a watchdog timer. This set of functions caters for a wide variety of The functionality of the typical system support needs and is augmented by the system's ability to expand components. In addition to these general purpose peripherals, the processor contains high-speed serial devices and parallel ports for connecting various audio, video, and modem codecs. A Flexible interrupt controllers manage interrupts from on-chip peripherals or external sources; and power management control functions customize the performance and power consumption characteristics of processors and systems in many application scenarios.

With the exception of general purpose I/O, all peripherals are real-time clocks and timers are supported by a flexible DMA structure. There is also a dedicated independent memory DMA channel for data transfers between the processor's various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz are sufficient bandwidth to keep the processor core running on all on-chip and external peripherals.

The processor includes dynamic power management features that support the processor's on-chip voltage regulator. The voltage regulator provides a range of core voltage levels VDDEXT. The voltage regulator can be bypassed at the discretion of the user.

BLACKFIN processor core

As shown in Figure 1 below, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs and a 40-bit shifter. The computing unit processes 8-bit, 16-bit or 32-bit data from registration files.

The computational register file contains eight 32-bit registers. When to perform computation operations on 16-bit operand data The register file operates as 16 separate 16-bit registers. Operands for all computational operations come from the multiport register file and instruction constant fields. Each MAC can perform a 16-bit by 16-bit multiply loop in each MAC, accumulating the results into a 40-bit accumulator. Signed and unsigned formats, rounding and saturation are supported.

The ALU performs a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to speed up various signal processing tasks. These include bit operations such as field extraction and population counting, modulo- 232 multiplication, division primitives, saturation and rounding, and sign/exponent detection. This set of video instructions includes byte alignment and packing operations, 16-bit and 8-bit addition with clipping, 8-bit average operations, and 8-bit subtract/absolute/accumulate (SAA) operations. Compare/select and vector search instructions are also provided.

For some instructions, two 16-bit ALU operations can be performed simultaneously on the register pair (16-bit upper half and 16-bit lower half of the compute register. Quad 16-bit operations can use the second ALU. 40 shift Bitters can perform shifts and rotations and are used to support normalization, field extraction, and field storage specification.

The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC-relative and indirect conditional jumps (using static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead loops. The architecture is fully interlocked, meaning that the programmer does not need to manage the pipeline's data-dependent instructions at execution time. The address arithmetic unit provides two addresses for simultaneous double fetches from memory. It contains a multi-port register file consisting of four sets of 32-bit index, modify, length and base registers (for circular buffering) and 8 additional 32-bit pointer registers (for C-style index stack operations).

Blackfin processors support an improved Harvard architecture combined with a hierarchical memory structure. Level 1 (L1) memory is typically memory that runs on full processors with little or no latency. At the L1 level, instruction memory only retains instructions. Two data memories set up data and a dedicated scratchpad data memory to store stack and local variable information. In addition, multiple L1 memory blocks are available, providing a configurable combination of SRAM and cache. The Memory Management Unit (MMU) provides individual memory protection registers that can run on the core and can protect the system's tasks from unintended accesses. The architecture provides three modes of operation: user mode, administrator mode and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while administrator mode has unrestricted access to system and core resources.

The Blackfin processor instruction set has been optimized with 16-bit opcodes representing the most commonly used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded as 32-bit opcodes, representing fully functional multifunction instructions. Blackfin processors support a limited multi-issue capability, where 32-bit instructions can be issued in parallel with two 16-bit instructions, allowing programmers to use many core resources in a single instruction cycle.

Blackfin processor assembly language uses an algebraic syntax to simplify coding and readability. This architecture has always been optimized for use with C/C++ compilers for fast and efficient software implementation.

memory architecture

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors view memory as a single unified 4Gbyte address space, using 32-bit addresses. All resources including internal memory, external memory and I/O control registers occupy different parts of this common address space. The memory portion of this address space is arranged in a hierarchical structure to provide some very fast, low latency good cost/performance balanced on-chip memory as cache or SRAM, larger, lower cost and performance off-chip memory systems. See Figure 2, Figure 3, and Figure 4 below. The L1 memory system is the main memory available to the highest performance Blackfin processors.

Blackfin processor core

ADSP-BF531 Internal/External Memory Map

ADSP-BF532 Internal/External Memory Map

ADSP-BF533 Internal/External Memory Map

The event controller on the handler handles all asynchronous and synchronous events for the handler. The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor provides event processing which supports nesting and priority. Nesting allows multiple event service routines to be active at the same time. Priority ensures that events of higher priority are serviced at the priority of events of lower priority. Controllers support five different types of events:

Emulation - An emulation event causes the processor to enter into emulation mode, allowing command and control of the processor through the JTAG interface.

reset - This event resets the processor.

Non-Maskable Interrupt (NMI) - NMI events can be generated by a software watchdog timer or NMI as an input signal to the processor. NMI events frequently occur as power outage indicators to initiate an orderly shutdown of the system.

Exception - The flow of events that occurs synchronously with the program (ie, exceptions are made before instructions allow completion). Conditional violations such as data alignment and undefined instructions cause exceptions.

Interrupt - A stream of events that occurs asynchronously to the program. They are peripherals caused by input pins, timers, etc., and explicit software instructions.

Each event type has an associated register to hold the return address and associated event return instruction. When an event is fired, the state of the handler is saved in

Supervisor stack.

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processor event controller consists of two stages, the Core Event Controller (CEC) and the System Interrupt Controller (SIC). The core event controller works in conjunction with the system interrupt controller to prioritize and control all system events. Conceptually, the interrupted peripheral goes into the SIC, which is then routed directly to the CEC's generic interrupt.