feature

• Low VIN and Wide VIN range: 1.0V to 5.5V

• Bias voltage (VVCC) range: 2.7V to 5.5V

• Low voltage range: 0.8V to 3.3V

• Low dropout voltage: 165mV, typical voltage is 1.5A, VVCC=5V

• 2% accuracy over line, load and temperature ranges

• Sequencing of power monitoring and other supplies

• Programmable soft-start provides linear voltage start

• Bias supply allows low VIN operation with good

Transient response

• Stable with any output capacitor ≥ 2.2µF

• DFN3030-10 and SOP-8L-EP: "Green" provides molding compound (Br, Sb free)

• Lead-free finish / RoHS compliant (Note 1)

General Instructions

The AP7173 is a 1.5A low dropout (LDO) linear regulator with user programmable soft-start, enable input and power-out good.

Soft start reduces the magnetizing inrush current of the load capacitor and minimizes stress on the input power supply during start-up. The enable input and power good output allow the user to configure a power management solution that meets the sequencing requirements of FPGAs, DSPs and other applications requiring different startup and power down requirements.

The AP7173 is stable with any type of output capacitance of 2.2µF or more. Accurate reference and feedback control provides 2% accuracy over load, line and operating temperature range. The AP7173 is packaged in both the DFN3030-10 and the SOP-8L-EP.

application

Modem, and setup; FPGA application; core and I/O Voltaire; post-conditioning application; sequence-required application.

Sort information

Note: 1. RoHS version 13.2.2003 . Exemptions for glass and high temperature solders apply, see Notes 5 and 7 of the EU Directive Annex.

2. Pad layout as shown by Diode Co.

pin assignment

Pin Description

block diagram

Typical Application Circuit

Absolute Maximum Ratings

NOTE: Stresses in excess of the Absolute Maximum Ratings may cause permanent damage to the device. These are pressure ratings only and functional operation of the device under these conditions is not implied. Long-term exposure to absolute maximum rating conditions may affect device reliability.

Recommended Operating Conditions

Typical performance characteristics

At TA=+25°C, unless otherwise noted, VIN=VOUT(typ)+0.3V, VVCC=5V, IOUT=50mA, VEN=VIN, CIN=1µF, CVCC=4.7µF, COUT=10µF.

Application Instructions

Bias VVCC

The AP7173 is a low VIN, low attenuation regulator that uses NMOS through field effect transistors. The VCC pin must be connected to the DC internal control circuit and the gate of the bias supply VVCC to drive the pass FET to function properly and obtain low dropout. VVCC must be equal to or higher than the VIN in the range of 2.7V-5.5V. Figure 27 shows a typical AP7173 application circuit.

Adjustable output voltage

With an external voltage divider, the AP7173 can provide output voltages from 0.8V to 3.3V. R1 and R2 can be calculated for any output voltage using the following equation, where VREF=0.8 is the internal reference voltage of the AP7173. Refer to Table 1 for common output resistor combinations for voltages. Maximum voltage accuracy, R2 should be ≤5kΩ.

Input VIN and Bias VVCC Capacitors

Keep the IN and VCC pins away from large ones by connecting capacitors to the input and VCC pins. The capacitance required on these pins is strongly dependent on the supply.

To provide good decoupling from the input supply VIN, it is recommended to use ceramic capacitors with a capacitance of at least 1µF connected as close to them as possible. High quality, low ESR capacitors should be used for better performance.

The internal control circuit for the AP7173 works fine. This is when VVCC and VIN are separate. If VIN and VVCC are connected to the same power supply, the recommended minimum capacitance for VVCC is 4.7µF. Good quality, low ESR capacitors should be used for optimum performance.

output capacitor

The output capacitance affects the stability and transient response of the system LDC. The AP7173 is designed for use with all types of output capacitor numbers ≥2.2µF, single or multiple in parallel. Using high quality, low ESR capacitors and placing them at the output and ground pins can improve performance.

dropout voltage

The extremely low dropout rate makes the AP7173 ideal for high current, low VIN/low VOUT applications. To achieve the low dropout performance specified for such applications, the VCC pin should be connected to at least 3.25 volts above VOUT. Figure 28 shows an application circuit where VVCC is 5V and VOUT is 1.2V.

For applications where a low dropout rate is not required or a separate VVCC supply is not available, the input and VCC pins can be connected together. In this case, a voltage difference of at least 1.7V between VVCC and VOUT must maintain VVCC to provide sufficient gate drive for the pass FET. Therefore, the guarantor needs to be 1.7 volts or more below the VIN as shown in Figure 29.

Programmable soft start

The AP7173 has a voltage controlled soft start, i.e. programmable external capacitor (CSS). The AP7173 works by tracking the external soft-start capacitor until the ramp voltage reaches the internal reference voltage. The relationship between soft-start time and soft-start charging current (ISS), soft-start capacitor (CSS), and internal reference voltage (VREF) is:

See Table 2 for recommended soft-start capacitor values.

enable/disable

The EN pin can be used for standard digital signals or relatively slow ramping analog signals. Pulling the vein below 0.4V turns off the regulator, while driving VEN above 1.1V turns the regulator on. Figure 30 shows an example where an RC circuit is used to delay the start of the AP7173.

If not used, EN pin can be connected to VCC or IN pin when VIN is greater than 1.1V, as long as good decoupling has been done to EN pin.

good power

The Power Good (PG) pin is an open-drain output that can pass 10kΩ to 1MΩ to VIN, VOUT, or any other 5.5V or lower rail. When VOUT≥VPG, TH+VPG, HYS, PG output is high impedance; if VOUT drops below VPG, TH, VVCC≤1.9V or the device is disabled, the PG pin is pulled low by the internal MOSFET.

Overcurrent and Short Circuit Protection

The AP7173 features factory trim, temperature and supply voltage compensation internal current limit and overcurrent protection circuitry to protect the device from overload conditions. It limits the device current to a value of 3A and makes it more popular to reduce VOUT when the load is trying to pull.

For more effective protection against short-circuit faults, the AP7173 also includes a short-circuit folding mechanism that reduces the current limit to below 0.2V from a typical value of 1.0A when VFB.

Thermal Protection

Thermal shutdown limits the AP7173 junction temperature to prevent device damage from overheating. When the AP7173 is turned off, thermal protection shuts down the VOUT junction temperature rising to approximately +150°C, allowing it to cool down. When the junction temperature drops to approximately +130°C, the output is re-enabled. The thermal protection circuit can thus cycle on and off at a rate that depends on power dissipation, thermal resistance, and ambient temperature.

Power consumption

Thermal shutdown is designed to protect the AP7173 from abnormal overheating. During normal operation, excessive power should avoid heat dissipation and provide good heat dissipation. The power dissipation in the device is the device voltage and load current,

It can be seen that output voltage regulation is achieved using the minimum input voltage required. To ensure that the device connection temperature exceeds the specified limit of 125°C, the application should provide a thermal conduction path to the surrounding environment with a thermal resistance lower than the value calculated here:

For DFN packages with exposed pads, the primary thermal conduction path is through the exposed pad printed circuit board. The pads should be connected to the appropriate copper PCB area to ensure the device does not overheat.

tag information

DFN3030-10

SOP-8L-EP

DFN3030-10

SOP-8L-EP