UniSLIC14 is a family of ultra-low power SLICs. The feature set and common pinout of this UniSLIC14 series position it as: Common Solutions Service (POTS) for Plain Old Telephone, PBX, Central Office, Loop Carrier, Optical Input Loop, ISDN-TA and NT1+, Pairgain and Wireless Local cycle. The UniSLIC14 series enables ultra-low power operation through: its automatic single and dual cell selection (based on line length) and cell tracking anti-pinch to ensure maximum loop coverage at the lowest cell voltage. This architecture is ideal for power critical applications such as ISDN NT1+, Pairgain and wireless local loop products. The UniSLIC14 series has many user programmable features. This range of SLICs provides a low noise, low component voice-grade design for counting solutions common to central office and ring line operators. The product family integrates advanced pulse metering, testing and signaling capabilities, as well as zero-cross loop control. The UniSLIC14 series utilizes the Intersil "Latch" free design bonded wafer process. This process isolates active circuits by dielectrics to eliminate competing JI processes. This allows the UniSLIC14 family to meet "hot swap" requirements and operate in harsh outdoor environments.

feature

Ultra-low active power (OHT) <60mW

Single/dual battery operation

Automatic silent battery selection

power management/shutdown

Battery Tracking Anti-Pinch

Single 5V Supply with 3V Compatible Logic

Zero-Crossing Loop Control - Zero Voltage On/Zero Current Off

tip/ring break

Pulse metering capability

4-wire loopback

Programmable current feed

Programmable Resistor Feed

Programmable loop detection threshold

Programmable on-hook and off-hook overhead

Programmable overhead for pulse metering

Programmable polarity reversal time

Optional transmission gain 0dB/-6dB

Single Net Setup 2-Wire Impedance

Loop and Ground Key Detectors

hook transport

common pinout

Lead-free plus annealed (RoHS compliant) available

Type HC55121 - Polarity Inversion HC55130 - 63dB Longitudinal Balance HC55140 - Polarity Inversion - Ground Start - Line Voltage Measurement - 2 Line Loopback - 63dB Longitudinal Balance V RMS Pulse Metering - 2 Wire Loopback HC55150 - Polarity Reversal - Line Voltage Measurement - 2.2V RMS Pulse Metering - 2 Wire Loopback

Available by putting SLIC in test mode.

The part mark is the same as the part number on all parts.

Note: Intersil lead-free + annealed products feature a special lead-free material set; molding compound/die attach material and 100% matte tin board termination finish, RoHS compliant, and compatible with SnPb and lead-free soldering operations. Intersil's lead-free products are MSL classified at lead-free peak reflow temperatures that meet or exceed the lead-free requirements of IPC/JEDEC J STD-020.

Absolute Maximum Ratings TA=25°C Thermal Information Temperature, Humidity

Storage temperature range. -65°C to 150°C

range of working temperature. -40°C to 110°C

Operating Junction Temperature Range. -40°C to 150°C

Power supply (-40°C≤TA≤85°C)

supply voltage V CC to ground. -0.4V to 7V

Supply voltage V BL to GND. -V BH to 0.4V

Supply voltage V BH to ground, continuous. -75V to 0.4V

Supply voltage V BH to ground, 10ms. -80V to 0.4V

Relay driver

Ring relay supply voltage. 0V to 14V

Ring relay current. 50 mA

Digital input, output (C1, C2, C3, C4, C5, SHD, GKD-LVM)

Input voltage. -0.4V to V CC

Output voltage (SHD, GKD U LVM not active). -0.4V to V CC

Output current (SHD, GKD_LVM). 5mA

ESD rating. 500 volts

gate count. 543 transistors, 51 diodes

Tipx and Ringx terminals (-40°C≤TA≤85°C)

Tipx or Ringx current. -100mA to 100mA

Thermal Resistance (Typical, Note 1) θJA

28 lead PLCC package. 52°C/W

28 lead SOIC package. 45°C/W

32-lead PLCC package. 66.2 degrees Celsius/Watt

Continuous power dissipation at 85°C

28 lead PLCC package. 1.5 watts

28 lead SOIC package. 2.0 watts

32-lead PLCC package. 1.4 watts

Lead temperature (10s for soldering). 300 degrees Celsius

(PLCC, SOIC - lead ends only) Derating tips and ring terminals above 70°C

Tipx or Ringx, current, pulse <10ms, T repetition >10s. Dijia

Tipx or Ringx, current, pulse < 1 ms, T repetition > 10 s. 5A class

Tipx or Ringx, current, pulse <10 microseconds, T REP>10s. 15A

Tipx or Ringx, current, pulse <1 microsecond, T repetition >10s. 20A

Tipx or Ringx, pulse <250ns, T repetition >10s 20A

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Installation under the above or any other conditions stated in the operating section of this specification is not implied.

Note:

1. θJA is measured in free air with components mounted on an evaluation PC board. Typical Operating Conditions These represent conditions for device development and are recommended as guidelines.

Electrical Specifications TA=-40°C to 85°C, V CC=+5V±5%, V BH=-48V, V BL=-24V, PTG=open circuit, R P1=R P2=0Ω, ZT=120kΩ, R LIM=38.3kΩ, RD=50kΩ, RDC URAC=20kΩ, R OH=40kΩ, CH=0.1μF, C DC=4.7μF, C RT/REV=0.47μF, GND=0V, RL=600Ω. unless otherwise specified. The symbols used to indicate the test apply to the part. (NA) Symbols used to indicate tests are not applicable to parts

notes

1. Overload level (two-wire port, off-hook) - overload when the signal source is located on the four-wire receive port (E RX). RL=600Ω, I DCMET≥18mA. Increase the amplitude of E RX until 1% THD is measured at V TR. Refer to Figure 1.

3. Overload level (two-wire port, hook) - overload at the signal source located at the four-wire receive port (E RX). RL=∞, I DCMET=0 mA. Increase the amplitude of the measured E RX to 1% THD at V TR. Refer to Figure 1.

4. Longitudinal Impedance - The longitudinal impedance is calculated using the following equation with the tip and ring voltages referenced to ground. L ZT, L ZR, VT, VR, AR and T are defined in Figure 2. (Hint) L ZT=VT/AT (ring) L ZR=VR/AR In the formula: EL=1V RMS (0Hz to 100Hz)

5. Longitudinal current limit (active on hook) - On hook determines the amplitude of the longitudinal current limit EL (Figure 3A) by increasing (60Hz) until the 2-wire longitudinal current is greater than the 28mA RMS wire. In this case, the SHD pin is kept low (no false detections), the 2-to-4-wire is verified, and the longitudinal balance is greater than 45dB (lb 2-4=20logvtx/EL).

6. Longitudinal Current Limit (Off-Hook Activated) - Off-hook determines the amplitude of the Longitudinal Current Limit EL (Figure 3B) by increasing (60Hz) until the 2-wire longitudinal current is greater than 28mA RMS/wire. In this case, the SHD pin is held high (no false detection), the 2-to-4-wire is verified, and the longitudinal balance is greater than 45dB (lb 2-4 = 20logvtx/EL).

7. Longitudinal to Metal Equilibrium - The Longitudinal to Metal Equilibrium was calculated using the formula: BLME = 20 log (EL/V TR), where: EL and V TR are defined in Figure 4.

8. Metal to Longitudinal FCC Part 68, Paragraph 68.310 - This specification addresses metal to longitudinal balance.

9. Longitudinal to four-wire balance - Longitudinal to four-wire balance is calculated using the following formula: BLFE = 20 log (EL/V TX ), EL and V TX as shown in Figure 4.

10. Metal-to-Longitudinal Balance - Metal-to-Longitudinal Balance Calculate balance using the following formula: BMLE = 20 logarithms (E TR/VL), E RX = 0 where: E TR, VL and E RX are shown in Figure 5.

11. Four-Pair Longitudinal Balance - Four-Pair Longitudinal Balance is calculated using the following formula: BFLE = 20 log(E RX/VL), E TR = source removed. Among them: E RX, VL and E TR as shown in Figure 5.

12. Two-wire return loss - Calculate two-wire return loss using the following formula: r=-20 log (2V M/VS), where: ZD=desired impedance; eg. , the characteristic impedance of the line, nominally 600Ω. (Refer to Figure 6).

13. Overload Level (4-Wire Port Decoupling) - The overload level specifies the power supply at the 2-wire port (for example) at the 4-wire transmit port (V TX), ZL=20kΩ, RL=600Ω (refer to Figure 7). The amplitude of the EG was increased to 1% THD and measured at V TX. Note that the PTG pin is open and the gain from the 2-wire port to the 4-wire port is equal to 1.

14. Overload Level (4-Wire Port on Hook) - The overload level specifies the power supply at the 2-wire port (for example) at the 4-wire transmit port (V TX ), ZL=20kΩ, RL=∞ (refer to Figure 7). Increase the amplitude of the EG until 1% THD is measured at VTX. Note that the PTG pin is open and the 2-wire port to the 4-wire port is equal to 1.

15. Output Offset Voltage - Specify the output offset voltage under the following conditions: EG=0, RL=600Ω, ZL=∞ and measured at VTX. For example, RL, VTX and ZL are shown in Figure 7.

16.2-Pair 4-Wire Frequency Response - 2-Pair Measurement 4-Wire Frequency Response For example, at 1.0kHz, G=0dBm, E RX=0V (VRX input float), RL=600Ω. The frequency response was calculated using the following formula: F 2-4 = 20 log (V TX / V TR ) with frequencies ranging from 300Hz to 3.4kHz and compared to a 1kHz reading. V TX, V TR, RL and EG are shown in Figure 8.

17. Four-to-two-wire frequency response - Four-to-two-wire - Measured wire frequency response relative to E RX = 0 dBm at 1.0 kHz, eg power removed from circuit, RL = 600Ω. This frequency response was calculated using the following formula: F 4-2 = 20 log (V TR/E RX ) for frequencies ranging from 300Hz to 3.4kHz and compared to the 1kHz reading. V TR, RL and E RX are shown in Figure 8.

18. 4-wire to 4-wire frequency response - 4-wire measurement 4-wire frequency response E RX = 0 dBm (at 1.0 kHz), e.g. with power removed from the circuit, RL = 600 ohms. The frequency response was calculated using the following equation: F 4-4 = 20 log (V TX/E RX ) with frequencies ranging from 300 Hz to 3.4 Hz and compared to a 1kHz reading. V TX, RL and E RX are shown in Figure 8.

19. 2-to-4-wire insertion loss measurement of 2-to-4-wire insertion loss For example, under a 1.0 kHz input signal, E RX=0 (VRX input floats), RL=600Ω, and use the following formula to calculate: L 2- 4 = 20 logarithms (V TX / V TR ) where: V TX, V TR, RL and EG are shown in Figure 8. (Note: The fuse resistance RF affects the insertion loss. The specified insertion loss is R F1=R F2=0).

20. 2-to-4-wire insertion loss (PTG=AGND) Measurement of 2-to-4-wire insertion loss = 0 dBm, 1.0 kHz input signal, E RX=0 (VRX input floats), RL=600Ω, calculated using the following formula : L 2-4 = 20 logarithms (V TX/V TR) where: V TX, V TR, RL and EG are shown in Figure 8. (Note: The fuse resistance RF affects the insertion loss. The specified insertion loss is R F1=R F2=0).

21. Four-to-two-wire insertion loss - Four-to-two-wire insertion loss measurements are based on E RX = 0 dBm, 1.0 kHz input signal, such as power removed from the circuit, RL = 600Ω, calculated using the following formula: L 4 -2 = 20 logarithms (V TR/E RX) where: V TR, RL and E RX are defined in Figure 8.

22. 2-wire to 4-wire gain tracking - 2-wire to 4-wire gain tracking refers to, for example, -10dBm, 1.0kHz signal, E RX=0 (VRX output floats), RL=600Ω, and is calculated using the following formula. G 2-4 = 20 logarithmic (V TX / V TR ) change amplitude -40dBm to +3dBm, or -55dBm to -40dBm, and compare with -10dBm reading. V TX, RL and V TR are shown in Figure 8.

23. Four-to-two-wire gain tracking - Four-to-two-wire gain tracking refers to E RX=-10dBm, 1.0kHz signal, such as power is removed from the circuit, RL=600Ω, and is calculated using the following formula: G 4-2= 20 logarithmic (V TR/E RX) variation amplitude -40dBm to +3dBm, or -55dBm to -40dBm and compared to -10dBm reading. V TR, RL and E RX are shown in Figure 8. The level is specified as a 4-wire receive port, referenced to a 600Ω impedance level.

24. Two-Wire Idle Channel Noise - Two-wire Idle Channel Noise at V TR, 2-wire port is floating with 600Ω (RL) terminated 4-wire receive port (VTX) (refer to Figure 9).

25. 4-Wire Idle Channel Noise - 4-Wire Idle Channel Noise at V TX, 2-wire port terminated in 600Ω (RL). Noise specifications are related to the 600Ω impedance level at V TX. The 4-wire receive port (VTX) is floating (refer to Figure 9).

26. Harmonic Distortion (2-wire to 4-wire) - Harmonics are measured within the vocal fold with the following distortion conditions. For example, G=0dBm and RL=600Ω at 1kHz. Measured at V TX. (Refer to Figure 7).

27. Harmonic Distortion (4-wire to 2-wire) - Harmonics are within the vocal cords measured in the following way of distortion. E RX=0 dBm0. At 300Hz and 3.4kHz, RL=600Ω. Measured at VTR. (Ref. Figure 8).

28. Constant Loop Current - The constant loop current is calculated using the following formula: IL=1000/R LIM=V TR/600 (refer to Figure 10).

29. Ground key detector (trigger) ground ring pin through a 2.5kΩ resistor to confirm if GKD goes low. (Reset) Disconnect the ring pin and verify that GKD is high. (hysteresis) Compare the difference between flip-flop and reset.

30. Electrical Tests - Production tests not performed at -40°C.

The SLIC of the UniSLIC14 series is a voltage-fed current-sensing subscriber line interface circuit (SLIC). Short for loop applications, the voltage terminals between the tip and ring are varied to maintain a constant loop current. Long-standing loop applications, the voltage between the tip and ring terminals is relatively constant, and the loop current varies proportionally to the load. The terminal and loop voltages of various loop resistances are shown in Figure 13. The tip voltage remains relatively constant for short loops as the ring voltage is moved to limit the ring current. The loop currents for various loop resistances are shown in Figure 14. For short loops, the loop current is limited at the programmed current limit, set by RILIM. For long-cycle applications, the loop current resists for a given terminal ring voltage and the loop's Ohm's law.

The following discussion divides the operation of the SLIC into its DC and AC paths, followed by additional circuitry and design information. DC supply curve The DC supply curve of the UniSLIC14 series is user programmable. The user defines the on-hook and off-hook rack voltages (including off-hook overhead voltage hook pulse measurements (if applicable), maximum and minimum loop current limits, switch hook detection thresholds, and battery voltages. Based on these requirements, the DC supply curve is designed for any specific application.

SPM pins For best performance, the PC board will keep the SPM pins as short as possible. If pulse measurement is not used, this pin should be grounded to the device pin as much as possible. RLIM pin current limiting resistor R LIM needs to be used as close as possible to the RLIM pin. 2-Wire Impedance Matched Layout Resistor ZT The correct connection to the ZT pin should have the external ZT network as close as possible to the device pin. The ZT pin is a high impedance pin used to set the appropriate feedback side to match the 2-wire impedance. This will remove the board capacity on that pin to maintain the frequency return loss for 2-wire.

Digital logic input

Table 1 is the logic truth table pins for 3V to 5V logic inputs. The combination of control pins C3, C2 and C1 selects 1 of 6 possible operating states. The 8th state listed is thermal shutdown. Activate thermal shutdown protection if a fault on the tip or ring causes the splice die temperature to exceed 175°C. Each operating state and control logic is described as follows: Open circuit state (C3=0, C2=0, C1=0) In this state, the output of the tip and ring is a high impedance condition (>1MΩ). No monitoring function SHD and GKD outputs are at TTL high level. A 4-wire loopback test can be performed in this state. Floating with the PTG pin, the V TX output signal is 180 o output phase and approximately 2 times the V RX input signal. If the PTG pin is grounded, the amplitude is about the same as the input, 180 degrees out of phase. Ringing state (C3=0, C2=0, C1=1) In this state, the output of the ring relay driver pin (RRLY) goes low (energizes the ring relay to connect the ringing if one of the following two conditions is satisfied : (1) The RSYNC_REV pin is connected to ground through a resistor - this connection causes the RRLY pin to momentarily go low to invoke the ringing state regardless of the ringing voltage (90V RMS-120V RMS) on the relay liaison. Resistor (34.8kΩ to 70kΩ) needs to limit the current into the RSYNC_REV pin. (2) Apply a ring sync pulse to the RSYNC_REV pin - this connection makes the RRLY pin a command for a ring sync pulse. The ring sync pulse should be at the current at the zero voltage crossing of the ring signal. This pulse rise and fall time should be less than 400 microseconds, with a minimum pulse width of 2ms. A zero loop current detection slide is automatically performed internally. This function causes the ring relay to de-energize slightly when zero current occurs to partially compensate for the relay off delay. When the user shuts down, the SHD output will hook low. Once the SHD is activated, the internal latch will inhibit re-ringing and then re-applying until the ring code is removed. The state prior to the call, cannot be the opposite active state. Active in reverse The voltage on the CRT_REV_LVM capacitor in the state will make it appear as if the subscriber has unhooked. This will then activate the internal latch, disabling the line ringing. The GKD_LVM output is in the ringing state.