The HFA1113 is a cache memory with user programmable gain and output limits and ultra-high speed performance. This buffer is for high frequency applications that require output limiting, especially those requiring ultra-fast overload recovery times. The output limit function allows the designer to set maximum positive and negative output levels, thus protecting against damage or input saturation later on. This sub-nanosecond overdrive recovery time quickly returns the amplifier's linear operation under overdrive conditions. The unique feature of the pins allows the user to select a voltage gain of +1, -1 or +2 without using any external components, as described in the "Application Information" section. Pin compatibility with existing op amps provides flexibility to upgrade low-gain amplifiers while reducing component count. Unlike most buffers, the standard pins provide an upgrade path if the closed-loop gain is high as needed at a future date. Component and composite video systems will also benefit from the performance of this buffer to obtain a flat, 0.02%/0.04 degree difference gain/phase specification (RL = 150 Ω).

Note: Intersil lead-free + annealed products feature a special lead-free material set; molding compound/mold join material and 100% matte tinplate finish, RoHS compliant, and compatible with SnPb and lead-free soldering operations. Intersil's lead-free products are classified as MSLs that meet or exceed the IPC/JEDEC J STD-020 lead-free requirements for lead-free peak reflow soldering.

feature

User Programmable Output Voltage Limit User Programmable Closed Loop Gain of +1, -1 or +2 Wide -3dB Bandwidth Without External Resistors. 850 MHz

Excellent gain flatness (to 100MHz). 0.07dB low differential gain and phase. 0.02%/0.04 degree low distortion (HD3, 30MHz). -73dB very fast slew rate. 2400V/µs fast settling time (0.1%). 13 ns high output current. 60mA excellent gain accuracy. 0.99 volts/volt overspeed recovery. <1ns standard op amp pins available lead-free plus annealed (RoHS compliant)

application

RF/IF processor

Drive Flash A/D Converter

high-speed communication

Impedance transformation

line driver

Video switching and routing

radar system

medical imaging system

Absolute Maximum Ratings Thermal Information

The voltage between V+ and V-. 12 VDC input voltage. V supply voltage at the VH or VL terminal. (V+)+2V to (V-)-2V output current (50% duty cycle). 60 mA

Operating Conditions Temperature Range. -40 to 85 degrees Celsius Thermal Resistance (Typical, Note 1) θJA (o C/W) SOIC package. 158 maximum junction temperature (plastic package). 150 degrees Celsius maximum storage temperature range. -65°C to 150°C maximum lead temperature (10s for soldering). 300 degrees Celsius (SOIC - lead only)

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Installation under the above or any other conditions stated in the operating section of this specification is not implied.

Note:

1. θJA is measured in free air with components mounted on an evaluation PC board.

Electrical Specifications V Power = ±5V, AV = +1, RL = 100Ω, unless otherwise specified

Electrical Specifications V Power = ±5V, AV = +1, RL = 100Ω, unless otherwise specified (continued)

notes:

2. This parameter is not tested. Limits are determined based on laboratory characteristics and reflect batch-to-batch variation.

3. See typical performance curves for details.

4. As the input transition time increases, the overshoot decreases, especially for V=+1. Please refer to typical performance curves.

Application Information Closed Loop Gain Selection

The HFA1113 employs a novel design that allows the user to select from three closed-loop gains without requiring any external components. The result is a more flexible product, with fewer parts in stock types, and a more efficient use of board space. This "buffer" operates with a closed loop gain of -1, +1 or +2, with the gain selected by connecting to the input. Applying the input signal to +IN and float -IN selects a gain of +1, while the ground - input selects a gain of +2. By applying the input signal to -ground + input. The following table summarizes these connections:

PC board layout

The frequency response of this amplifier depends to a large extent on the degree of care required in designing the PC board. This use of low inductance components such as chip resistors and chip capacitors is highly recommended, while a solid ground is a must! Care should be taken to disconnect the power supply. Large value (10µF) tantalum and small value tantalum parallel chip (0.1µF) capacitors work well in most cases. It is recommended that the input and output of the device. Capacitance directly at the output must be minimized or isolated, as described in the next section. For unity gain applications, care must also be taken to minimize the reverse input of the amplifier's capacitance to ground. At higher frequencies, this capacitance will tend to short the input to GND, resulting in an increased gain of the closed loop with frequency. This can lead to excessive high frequency peaks and potentially other problems. An example of a good high frequency layout is the evaluation board shown in Figure 3. Driving capacitive loads Capacitive loads, such as A/D inputs, or terminating transmission lines can reduce the phase margin of the amplifier resulting in frequency response peaking and possible oscillation. In most cases, oscillation can be avoided by placing a resistor (RS) in series with the output before the capacitor.

Figure 1 details the selection of this resistor. The points on the curves represent the RS and CL optimal bandwidth, stability, and settling time, but experimental fine-tuning is recommended. Selecting a point above or to the right of the curve will produce an overdamped response, while points below or to the left of the curve show areas of insufficient damping performance. RS and CL form a low-pass network at the output, thus limiting the system bandwidth well below the amplifier bandwidth of 850 MHz. Decreasing RS as CL increases (as shown in the curve), the maximum bandwidth is at the expense of stability. Even so, the bandwidth will move to the right along the curve. For example, at AV=+1, RS=50Ω, CL=30pF, the total bandwidth is limited to 300MHz, the bandwidth is AV=+1, RS=5Ω, CL=340pF.

The performance of the HFA1113 can be achieved using the HFA11XX evaluation board with slight modifications as follows: 1. Remove the 500Ω feedback resistor (R2) and leave the connection open.

2.a. For V=+1 evaluation, remove the 500Ω gain setting resistor (R 1) and leave pin 2 floating. b. For V=+2, use a grounding resistance of 0 ohms. The modified board schematic and layout are shown in Figures 2 and 3. To order the evaluation board (part number HFA11xEval), use a SOIC dip adapter such as Aries Electronics part number 08-350000-10.

General operating limits

The HFA1113 has a user-programmable output clip to limit the output voltage excursion. The clamping action is obtained through the VH and VL terminals (pins 8 and 5) of the amplifier. VH sets the output upper limit, while VL sets the lower clamp level. If the amplifier tries to drive the output above VH or below VL, the clamp circuit limits the output voltage below VH or VL (±clamp accuracy), respectively. The low input bias current of the clamp pins allows them to be driven by simple resistive divider circuits, or active components such as amplifiers or digital-to-analog converters. Clamp Circuit Figure 4 shows a simplified schematic-level and high clamp (VH) circuit for the HFA1113 input. As with all current feedback amplifiers, there is a unity gain buffer (Q X1-Q X2) between the positive and negative inputs. This buffer force-input tracks +input and sets the following slew current: (V-input-output)/R F+V-input/RG This current goes through Q X3-Q X4, where it is converted to a voltage and is is fed to the output through another unity gain buffer. If clamping is not used, the high impedance node may swing within the limits specified by Q P4 and Q N4. Note that when the output reaches a quiescent value, the inflow current is reduced to only a small current (-I bias) required to maintain the output final voltage. Tracing the path from VH to Z illustrates the clamping voltage on the high impedance node. VH drop sets base voltage on Q P5 via 2V BE (Q N6 and Q P6)

When a high impedance node

Achieving a voltage equal to the base voltage of Q P5 + 2V BE (qp5) and question 5). Therefore, Q P5 clamps node Z for five hours when Z arrives. R 1 provides a pull-up network to ensure that the functional clamp input is floating. A similar description applies to a symmetric low-clamp circuit controlled by VL. When the output is clamped, the negative input continues to generate a slew current (I Clamp) in an attempt to force the output to a quiescent voltage defined by the input. Problem 5 must sink current while clamping because the -IN current is always mirrored on the high impedance node. The clamping current is calculated as follows: I clamp = (V-input-V-output clamp)/300Ω+V-input/RG. For example, a unity gain circuit, with V IN = 2V and VH = 1V, would have I clamp = (2V-1V)/300Ω+2V/∞=3.33mA (since -IN is floating in unity gain applications). Note that when the output is a clamp.

Clamping Precision The clamped output voltage will not be exactly equal to the voltage applied to VH or VL. Offset errors, mainly caused by VBE mismatches, require clamping accuracy parameters to be found in the device specification. Clamping accuracy is a function of clamping conditions. Referring again to Figure 4, it can be seen that one component accuracy of the fixture is the VBE mismatch between the Q X6 transistors, and the Q X5 transistors. If the transistor is always at the same current level there will be no voltage mismatch nor will it contribute to the inaccuracy. The QX6 transistor is biased at constant current, but the current through QX5 is equivalent to the I-clamp as previously described. VAT increases as I clamp increases, causing the clamp output voltage to increase as well. Clamping is a function of overdrive (VCL x V input-output clamping), so clamping accuracy decreases as overdrive increases. For example, the specified accuracy for 1.6X overdrive is ±100mV (AV=-1, VH=1V) for 3X (200%) overdrive, downgraded to ±240mV, as shown in Figure 43. It must also be considered that the clamp voltage has an effect on the linearity of the amplifier. This "Nonlinearity around clamping voltage" curve, Figure 48, illustrates the effect of several clamping levels on linearity.

The clamping range differs from some competitor devices in that both VH and VL have a usable range that can cross 0V, while VH must be more positive than VL, both can be positive or negative, as stated in the range specification limit. For example HFA1113 can be limited to ECL output levels VH=-0.8V and VL=-1.8V by setting. VH and VL can be connected to the same voltage (eg GND), but the result will not be a DC output voltage for an AC input signal. A 150mV-200mV AC signal will still appear at the output. Resuming from overdrive as long as the overspeed condition remains. When the input voltage falls below the overdrive level (V Clamp / A VCL), the amplifier will return to linear operation. A time delay, called the overspeed recovery time, is a linear operation necessary for this recovery. "Unrestricted Performance" and "Clamping Performance" (Figures 41 and 42) highlight the sub-nanosecond recovery time of HFA1113. The difference is the overspeed recovery time between unclamped and clamped propagation delays. Proper Propagation Delay is 8.0 ns for the unclamp pulse; for the unclamp pulse, the delay is 8.8 ns The clamping (2X overspeed) pulse produces an overspeed recovery time of 800ps. The measurements continue to say using output transformations to ensure linear operation. NOTE: The propagation delay shown is controlled by the fixture. The displayed increments are accurate, but the real hfa113 transmission delay is 500ps. Overdrive recovery time is also a functional level of overdrive. Figure 47 details the various clamp and overdrive gears.

Unless otherwise specified, typical performance curves V supply = ±5V, TA = 25 oC, RL = 100Ω

Typical Performance Curves V supply = ±5V, TA = 25 oC, RL = 100Ω, unless otherwise specified (continued)

Typical Performance Curves V supply = ±5V, TA = 25 oC, RL = 100Ω, unless otherwise specified (continued)