feature

Broadband; 60 MHz at -1 gain; 33 MHz at -10 gain; Slew Rate: 2000 V/µs; 20MHz Full Power Bandwidth, 20V pp, RL= 500 Ω; Fast Settling: 100 ns to 0.1% (10 V step); Differential gain error: 0.03% at 4.4mhz; Differential phase error: 0.16° at 4.4MHz; Low offset voltage: 150µV max (B-grade); Low quiescent current: 6.5mA; Available According to EIA-481-A standard.

application

Flash ADC input amplifier; high-speed current DAC interface; video buffer and cable driver; pulse amplifier.

General Instructions

The AD844 is a high speed monolithic operational amplifier fabricated using analog equipment, connected to an isolated complementary bipolar (CB) process. It combines high bandwidth with very fast large signal response and excellent DC performance. Although optimized for current-voltage as an inverter mode amplifier, it is also suitable for use in many non-vertical applications.

The AD844 can replace traditional op amps, but the current feedback architecture results in better ac performance, high linearity, and exceptionally sharp impulse response.

The closed-loop bandwidth provided by this op amp is determined primarily by the feedback resistor and is independent of the closed-loop gain. The AD844 does not have traditional op amps and other current feedback op amps. The peak output rate of change exceeds 2000 V/µs over the entire 20 V output step. Settling times are typically 100 nanoseconds to 0.1%, essentially independent of gain.

The AD844 can drive 50Ω loads to ±2.5 V and is short-circuit protected to 80 mA with low distortion. The AD844 is available in four performance grades and three package options. In a 16-lead SOIC (RW) package, the AD844J is specified for a commercial temperature range of 0°C to 70°C.

The AD844A and AD844B are suitable for the industrial temperature range of -40°C to +85°C and are available in the CERDIP(Q) package. The AD844A also has an 8-lead PDIP (N). The AD844S has an over-military temperature range of -55°C to +125°C. Available in 8-lead cermet (Q) wrap. Class A and Class S chips and devices MIL-STD-883B, revision. C is also available.

Product Highlights

1. AD844 is a versatile, low-cost component that provides a perfect combination of AC and DC performance.

2. It basically has no slew rate limit. Rise and fall times are largely independent of output levels.

3. The AD844 can operate from ±4.5 V to ±18 V power supplies and can drive loads up to 50Ω, as well as using an external network.

4. The bias voltage and input bias current of the AD844 are laser trimmed to reduce DC errors; the VOS drift is typically 1μV/°C, and the bias current drift is typically 9na/°C.

5. AD844 has excellent differential gain and differential phase characteristics, making it suitable for various video applications with bandwidths up to 60 MHz.

6. The AD844 combines low distortion, low noise and low wideband drift, making it an input amplifier for a flash analog-to-digital converter (adc).

Absolute Maximum Ratings

28-lead PDIP package: θJA=90°C/W.

8-lead CERDIP package: θJA=110°C/W.

16 lead SOIC package: θJA=100°C/W.

Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; equipment at these or any other conditions beyond the operating conditions is not implied by this section of this specification. Exposure to absolute long-term maximum rated conditions may affect device reliability.

metallized photo

Contact factory for latest sizes.

Dimensions are in inches and (millimeters).

Typical performance characteristics

T=25°C, V=±15 V unless otherwise noted.

Inverter gain/1 AC characteristic

10 Inverse Gains for AC Characteristics

10 Inverse Gain of Impulse Response

10 times AC gain characteristics

Learn about the AD844

The AD844 is used in a similar way to traditional op amplifier applications that offer wideband performance advantages. However, there is a need to understand the internal structure in order to optimize the performance of the AD844 op amp.

open loop behavior

Figure 28 shows a current feedback amplifier reduced to basic. Fixed sources of DC errors, such as reverse node bias, current and offset voltage are not included in this model. The most important parameter limiting the DC gain is the resistance, Rt, which is ideally infinite. The finite value of Rt is similar to a finite open-loop voltage gain op amp in conventional systems.

The current applied to the inverting input node is carried by the current conveyor flowing in the resistor Rt. The resulting voltage is buffered by a unity-gain voltage follower through Rt. Voltage gain is the ratio of Rt/RIN. Typical values are Rt=3MΩ and RIN=50Ω, and the voltage gain is about 60000. The open-loop current gain, another form of beta product by the voltage follower stage transistors (see Figure 31), is typically 40,000.

Important parameters that define AC behavior are transcapacitance, Ct, and external feedback resistance (not shown). The time constant formed by these components is similar to the dominant pole of a conventional op amp so if a closed loop system the system is to be stable. In practice, the Ct value is kept as low as possible (typically 4.5 pF) so that the feedback resistor can be maximized while maintaining a fast response. Finite RIN can also affect the closed-loop response in some applications.

Open-loop AC gain can also be used with transimpedance instead of open-loop voltage gain. This open-loop pole is formed by Rt and Ct in parallel. Since Ct is typically 4.5 pF, the open loop corner frequency occurs at 12 kHz. However, this parameter determines the closed loop response.

as an inverting amplifier response

Figure 29 shows the connection of the inverting amplifier. Unlike conventional amplifiers, the transient response and small signal bandwidth are dominated by the external feedback resistor R1 rather than R1/R2 which is often the case in op amp applications. This is a direct result of the low input impedance of the inverter. As for a conventional op amp, the closed loop gain is -R1/R2. The closed loop resistance is the parallel sum of R1 and Rt. Because R1 is typically between 500Ω and 2kΩ and Rt is about 3mΩ, the closed loop resistance is only 0.02% lower than R1 by 0.07%. This small error is usually smaller than the resistor tolerance.

When R1 is quite large (greater than 5 kΩ) but still much smaller than Rt, the closed-loop high-frequency response is governed by a time constant of 1 ct. In this case, overloading the AD844 provides only a fraction of its bandwidth potential. Because under these conditions, there is no slew rate limit, the circuit exhibits a simple unipolar response signal condition even at very large scales.

In Figure 29, R3 is used to properly terminate the input if needed. R3 is connected in parallel with R2 to create a terminating resistor. Because R1 is lowered, the signal bandwidth increases, but the time constant R1 Ct responds fairly well to higher-order poles in the closed loop. Consequently, the closed-loop response becomes complex and the impulse response exhibits overshoot. When R2 is much larger than the input resistance, RIN, at pin 2, most of the feedback current in R1 is passed to this input, but as R2 is compared to RIN at pin 2, resulting in a more severely damped response. Therefore, for low values of R2, R1 can be lowered without causing instability in the closed-loop response. Table 3 lists the combinations of R1 and R2 and the resulting circuit frequency response shown in Figure 29. Figure 16 shows the pulse response of the very clean and fast ±10 VAD844.

Response of the IV Converter

The AD844 works well as an active component in combat current-to-voltage converter, with an external scaling resistor, R1, as shown in Figure 30. This analysis includes the stray capacitance CS of the current source, which can be a high speed DAC. With conventional op amps, this capacitor forms an interference pole with R1, making the closed-loop unstable system response. Most op amps are internally compensated for the fastest response at unity gain, so the poles are reduced by R1 and CS to reduce the system's already narrow phase margin. For example, if R1 is 2.5 kΩ, a CS of 15 pF puts the pole at a frequency of about 4 MHz, even at mid-speed op amps. In a current feedback amplifier, this pesky pole is no longer determined by R1, but by the input resistance, RIN. Since this is about 50Ω for the AD844, the same 15pf forms a pole at 212mhz, causing little trouble. It can be seen that the response of the system is:

where: K is a very close to unity factor representing the finite DC gain of the amplifier; Td is the dominant pole; Tn is the nuisance pole.

Using typical values of R1=1 kΩ and Rt=3 MΩ, k=0.9997; that is, the gain error is only 0.03%. This is larger than the scaling error of nearly all digital-to-analog converters, and if necessary, fine-tuned by precision systems.

In the AD844, Rt is fairly stable over temperature and supply voltage, so the effect of finite gain is negligible unless a high value feedback resistor is used. Because that results in a slower response time than possible, the low Rt value in the AD844 is rarely a significant source of error.

Circuit description of AD844

A simplified schematic is shown in Figure 31. The AD844 differs from a conventional op amp in that it has a completely different impedance at the signal input. The non-vertical input (pin 3) presents the usual high impedance. The voltage at this input is delivered to the inverting input (pin 2) at a low offset voltage, guaranteed to be under substantially the same bias conditions by closely matching transistors of similar polarity. Laser zeroing the remaining bias voltage, down to tens of microvolts. This inverting input is a complementary common transmit node pair of grounded bases that act as a current summing node. In an ideal current feedback op amp, the input resistance is zero. In the AD844, it is about 50Ω.

The current applied to the inverting input is passed to a complementary pair of unity-gain current mirrors to the same current at the internal node (pin 5) to produce the output voltage. A unity-gain complementary voltage follower then buffers this voltage and provides the load drive. This buffer is designed to drive low impedance loads, such as terminated cables, and can deliver ±50mA into a 50Ω load while maintaining low distortion, even when operating from a supply voltage of only ±6V, with current limiting ( not shown) to ensure safe operation under short-circuit conditions.

It is important to understand

The reverse input is generated locally and does not depend on feedback. This is in contrast to the regular op-amp mode for current summing, which is essentially an open circuit until the loop stabilizes. In the AD844, transient currents at the input do not cause the amplifier to settle down. Also, all transient currents go through a short signal path (ie grounded base and broadband current mirror).

The current available to charge the capacitor (about 4.5 pF) at the TZ node is always proportional to the input error current, and the slew rate limiting op amp associated with large signals does not respond. Therefore, the rise and fall times are almost independent of the signal level. In fact, the input current eventually causes the mirror to saturate. At about 10 mA (or ±200 V/µs) when using a ±15 V supply. Because signal currents are rarely this large, there are no classic slew rate limitations.

There is a slew rate limit if the voltage follower uses a buffered output. The AD844 is designed to avoid this problem and, therefore, the output buffer exhibits a clean large-signal transient response, free of anomalous effects caused by internal saturation. The response as a non-rotating amplifier is because current feedback amplifiers are asymmetric in terms of their two inputs, in non-inverting and inverting modes. The large-signal high-speed performance of the AD844 in non-vertical mode is at low gain because the bias circuit of the input system (not shown in Figure 31) is not designed for high input voltage slew rates. However, to achieve good results, one must be cautious. This non-vertical input does not allow for large transient inputs; it must be kept below ±1 V for best results. Therefore, this mode is more suitable for high gain applications (greater than ×10). Figure 23 shows a non-vertical amplifier with a gain of 10 with a bandwidth of 30 MHz. The transient response is shown in Figure 26 and Figure 27. To add higher bandwidth gain, a capacitor can be added to R2 with a value of approximately (R1/R2) × Ct.

irreversible gain 100

The AD844 provides a very clean impulse response at high voltage with non-value added gains. Figure 32 shows a typical configuration providing a gain of 100 with high input resistance. Feedback resistors are kept as low as possible to maximize bandwidth, and a peak capacitor (CPK) can optionally be added to further extend bandwidth. Figure 33 shows small-signal CPK=3nF, RL=500Ω, and supply voltages of ±5 V or ±15 V. Gain bandwidth products as high as 900 MHz can be achieved with this method.

The bias voltage of the AD844 is laser trimmed to the 50µV level and exhibits very low drift. In effect, there is an additional offset term input (IBN) due to reverse bias current flowing into the feedback resistor (R1). The can is optionally zeroed by trimming the potentiometer, as shown in Figure 32.

Using AD844

board layout

As with all high frequency circuits, great care must be taken with the placement of components used around the AD844. The ground planes of the power supply decoupling capacitors are connected by the shortest possible wires for achieving a clean impulse response. Even a continuous ground plane exhibits a limited voltage drop between points on the plane, and ground points must be chosen with this in mind. In general, decoupling capacitors should be placed somewhere close to the load (or output connector) because load current flows at high frequencies in these capacitors. The + and - input circuits in the (for example, termination resistors and pin 3) must be brought to the ground plane close to the amplifier components.

Use a low impedance 0.22µF capacitor (AVX SR305C224KAA or equivalent) where AC coupling is required. Includes ferrite beads and/or small series resistors (approximately 4.7Ω).

input resistance

At low frequencies, negative feedback keeps the resistance close to zero at the inverting input. As frequency increases the impedance of this input increases from near zero to open loop input resistance due to bandwidth limitations, making the input appear inductive. If it is desired to keep the input impedance flat, a series RC network can be inserted through the input. The resistors are chosen so that in parallel and where R2 equals the desired termination resistor. The capacitors are set so that the pole determined by this RC network is about half the op amp bandwidth. This network does not matter if the input resistance is much larger than the termination used, or if the frequency is relatively low. Small spikes that occur without a network in some cases can be used to extend the -3db bandwidth.

Driving large capacitive loads

Capacitive drive capability of 100 pF requires no external network. Together with the network shown in Figure 34, the capacitive drive can be scaled beyond 10000 pF with limited internal power dissipation. For capacitive loads, the output speed becomes a function of the overdrive output current limit. Since this is about ±100 mA, the maximum slew rate for a 1000 pF load under these conditions is ±100 V/µs. Figure 35 shows the transient response of the inverting amplifier (R1 = R2 = 1 kΩ), using the feedforward network shown in Figure 34, driving a 1000 pF load.

Settling time

Settling time was measured using the circuit of Figure 36. This circuit uses a false summing node, with two nodes holding Schottky diodes, which generate false signals and limit the input to the oscilloscope. To measure the settling time, the ratio R6/R5 is equal to R1/R2. For unity gain, R6=R5=1kΩ, and RL=500Ω. For a gain of -10, R5 = 50Ω, R6 = 500Ω, and RL is not used because the summing network loads the output about 275Ω. Using this network configuration in unity gain, a –5 V to +5 V settling time of 100 ns to 0.1% in CL=10 pF steps.

DC Error Calculation

Figure 37 shows the AD844. The reverse input bias current, IBN, flows into the feedback resistor. IBP, the non-vertical input bias current is in the resistor at pin 3 (RP), and the resulting voltage (plus any offset voltage) appears at the inverting input. The error VO at the total output is:

Because IBN and IBP are uncorrelated in both sign and number, inserting resistors in series with non-vertical inputs does not necessarily reduce DC error, and may actually increase DC error.

noise

The noise source can model the current in a similar way to DC bias, but the noise source is INN, INP, VN and the induced noise VON at the amplifier output is:

By keeping all resistor values to a minimum. For typical numbers, R1=R2=1kΩ, RP=0Ω, VN=2nV/√Hz, INP=10pa/√Hz, INN=12pa/√Hz, and VON is calculated to 12 nV/√Hz. Current noise dominates in this regard as it is in most low gain applications.

Video cable driver using ±5 V supply

The AD844 can be used to drive low impedance cables. Using a ±5 V supply, a 100Ω load can be driven to ±2.5 V twist at low voltages. Figure 38 shows an example application that provides a non-vertical gain of +2, allowing reverse termination of the cable while loading. The -3db bandwidth of this circuit is typically 30mhz. Figure 39 shows the differential gain and phase test setup. In video applications, both differential phase and differential gain characteristics are often important. Figure 40 shows the change in phase load voltage change. Figure 41 shows the gain variation.

High-speed DAC buffer

The AD844 performs well in applications requiring current-to-voltage conversion. Figure 42 shows the current output DAC with the AD568. In this application, a bipolar offset is used to make a full-scale current of ±5.12 mA using a 1 kΩ application resistor to produce an output of ±5.12 V on the AD568. Figure 43 shows the full-scale transient response. Take care when decoupling and grounding power to achieve full 12-bit accuracy and fast settling capabilities of the system. AD568 Product Introduction Please consult for details on its use.

20 MHz Variable Gain Amplifier

The AD844 is the AD539 multiplier in all its connected modes. (See the AD539 data sheet for full details.) Figure 44 shows a simple multiplier that provides the output:

where VX is the gain control input, a positive voltage of 0 V to 3.2 V (max), and VY is the signal voltage, nominally ±2 V full scale, but operable to ±4.2 V. Therefore, the peak output in this configuration is ±6.7 V. Using the four internal application resistors provided on the AD539 in parallel, the feedback resistance is 1.5 kΩ, which at this point gives the AD844 a bandwidth of approximately 22 MHz and is inherently independent of VX. The gain is 4db when VX=3.16v.

Figure 45 shows the small-signal response range (VX = 10 mV to 3.16 V) for a 50-dB gain control. For small values of VX, feedthrough on capacitive PC boards becomes very troublesome and requires careful layout techniques to minimize this problem. A ground strap between the AD539 pins helps with respect. Figure 46 shows the response to a 2V pulse on VY for VX = 1 V, 2 V, and 3 V. For these results, a load resistance of 500Ω was used and the power supply was ±9V. The multiplier operates from a supply between ±4.5 V and ±16.5 V.

Disconnecting pins 9 and 16 on the AD539 changes the denominator in the equation 1 to 1V, with a bandwidth of about 10MHz and a maximum gain of 10dB. Using only pin 9 or pin 16 yields a denominator of 0.5 V with a bandwidth of 5 MHz and a maximum gain of 16 dB.

Dimensions

1. Z = RoHS compliant parts.

2. For test specifications, please refer to the explanatory drawings.