Features and Benefits

• ±2.5 A, 35 V output rating

• Low R output, 0.28Ω source, 0.22Ω sink typical DS (on)

• Automatic current decay mode detection/selection

• 3.0 to 5.5 V logic supply voltage range

• Mixed, fast and slow current decay modes

• Household output

• Low power synchronous rectification

• Internal UVLO and thermal shutdown circuitry

• Cross current protection

Package: 28-pin TSSOP (suffix LP) with exposed thermal pad

illustrate

The A3977 is a complete microstepping motor driver with built-in translation. It is designed to operate bipolar stepper motors in full-, half-, fourth-, and eighth-order modes with an output drive capability of 35 V and ±2.5 A. The A3977 includes a fixed off-time current regulator capable of operating in slow, fast or mixed decay modes. This current decay control scheme reduces motor audible noise, improves step accuracy, and reduces power consumption.

Translation is the key to the ease of implementation of the A3977. Just a single pulse at the step input can drive the motor one step (two logic inputs determine whether it is a full step, half step, quarter step or eight steps). There are no phase sequence tables, high frequency control lines or complex programming interfaces. The A3977 interface is ideal for applications where complex microprocessors are unavailable or overburdened.

Internal synchronous rectification control circuitry is provided to improve power consumption during PWM operation.

Internal circuit protection includes hysteretic thermal shutdown, undervoltage lockout (UVLO), and cross-current protection. No special power-up sequence is required.

The A3977 features a thin (<1.2 mm) 28-pin TSSOP with exposed thermal pads (suffix LP). The A3977 is lead free, 100% matte tin plated lead frame.

Function description

Equipment operation

The A3977 is a complete microstepper motor driver with built-in converter for easy operation and minimal control lines. It is designed to operate bipolar stepper motors in full-step, half-step, four-step and eight-step modes. Each of the two output full bridges is an N-channel dmo whose current is regulated by a fixed off-time pulse-width modulation (PWM) control circuit. The full-bridge current for each step is set by the value of the external current-sense resistor (R), the reference voltage (V), and the output voltage of the DACs controlled by the converter output.

On power-up or reset, the converter sets the DAC and phase current polarity to the initial initial state (see initial state conditions in the figure), and sets the current regulators for both phases to mixed decay mode. When a step command signal appears on the step input, the converter automatically sequences the DAC to the next stage (see Table 2 for the current stage sequence and current polarity). The microstep resolution is set by the input MS and MS as shown in Table 1. If the new DAC output level is lower than the previous level, the decay mode of this full bridge will be set by the PFD input (fast, slow or mixed decay). If the new DAC level is higher than or equal to the previous level, the decay mode of the full bridge will be slow decay. This automatic current decay selection will improve microstepping performance by reducing current waveform distortion caused by motor BEMF.

reset input (reset)

The reset input (active low) sets the converter to a predefined initial state (see initial state conditions in the figure) and turns off all DMOS outputs. The main output goes low and all step inputs are ignored until the reset input goes high.

local output (local)

The HOME output is a logical output indicator of the initial state of the converter. On power-up, the converter will reset to its initial state (see initial state conditions in the diagram).

Step input (step)

A low-to-high transition on the step input causes the shifter to sequence and advance the motor one increment. The converter controls the input of the DAC and the current flow in each winding. The size of the increment is determined by the state of the input MS and MS (.

Microstep selection (MS1 and MS2)

Input terminals MS1 and MS select the microstepping format according to Table 1. Changes to these inputs remain until the STEP command takes effect (see figure).

Direction Input (DIR)

The state of the direction input will determine the direction of rotation of the motor.

Internal PWM current control

Each full bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to the desired value (I). Initially, a pair of diagonal source and sink DMO outputs are enabled and current flows through the motor windings. When the voltage across the current sense resistor equals the DAC output voltage, the current sense comparator resets the PWM latch, which turns off the source driver ( slow decay mode) or receiver and source drivers (fast decay mode or mixed decay mode).

The maximum value of the current limit is set by selecting the voltage at the R and V inputs, and the transconductance function is approximated as:

The DAC output reduces V to the current sense comparator in precise steps.

It must be ensured that the maximum rating (0.5 V) on the sense terminal is not exceeded. For full-step mode, V can be applied to the maximum rated value of V because the sensed value is 0.707 x V/8. In all other modes, V should not exceed 4 V.

Fixed working hours

An internal PWM current control circuit uses one trigger to control how long the driver remains off. There is only one chance, t, determined by the choice of external resistor (R) and capacitor (C) connected from the RC timing terminal to ground.

Over the range of C=470 pF to 1500 pF and R=12 kΩ to 100 kΩ, the off-time is approximately:

Reinforced concrete blanking

In addition to the fixed PWM control circuit off time, the C element also sets the comparator blanking time. This function will blank the output of the current sense comparator when the internal current control circuit switches the output. The comparator output is shielded to prevent false overcurrent detection due to reverse recovery current of the clamp diode and/or switching transients related to load capacitance. The blank time t can be approximated as:

Fill pump. (CP1 and CP2)

A charge pump is used to generate a gate supply greater than V to drive the source-side DMOS gate. A 0.22µF ceramic capacitor should be connected between CP and CP for pumping purposes. A 0.22µF ceramic capacitor is required between V and V as a reservoir to operate the high-side DMOS device.

VREG

This internally generated voltage is used to operate the receiver side DMOS output. A 0.22µF capacitor should be used to separate the V terminal from ground. V is internally monitored, and in the event of a fault, the output of the device is disabled.

Enable input (enable)

This low input enables all DMOS outputs. When logic high, the output is disabled. The inputs of the converter (step, direction, MS, MS) are all active regardless of the enabled input state.

closure

In the event of a fault (too high junction temperature or too low voltage on V), the output of the device will be disabled until the fault condition is removed. At power-up, if the voltage gets too low, an under-voltage lockout (UVLO) circuit disables the driver and resets the converter to its initial state.

sleep mode (sleep)

An effective low control input for minimizing power consumption when not in use. This disables many internal circuits, including the output DMO, regulator, and charge pump. A logic high allows the device to function and start normally in its initial position. When leaving sleep mode, wait 1 ms before issuing a step command for the charge pump (gate drive) to stabilize.

Percentage of Fast Decay Input (PFD)

When the step input signal commands a lower output current from the previous step, it switches the output current decay to slow, fast or mixed decay according to the voltage level of the PFD input. If the voltage at the PFD input is greater than 0.6 V, then slow decay mode is selected. If the voltage at the input of the PFD is less than 0.21v, the fast decay mode is selected. Mixed decay is somewhere in between these two levels. This terminal should be separated from the 0.1µF capacitor.

Mixed Decay Operation

If the voltage at the PFD input is between 0.6V and 0.21V, the bridge will operate in mixed decay mode according to the step sequence (see picture). When the trigger point is reached, the device will enter a fast decay mode until the voltage on the RC terminal decays to the voltage applied to the PFD terminal. The time for the device to operate under fast decay is approximately:

After this fast decay portion t, the device will switch to slow decay mode for the remainder of the fixed off period.

Synchronous rectification

When an internally fixed off time period triggers a PWM off period, the load current is recirculated according to the decay mode selected by the control logic. The A3977 synchronous rectification feature will turn on the proper mosfet during current decay and effectively drive it with a low R. This will significantly reduce power dissipation and eliminate the need for an external Schottky diode DS(on) for most applications.

Synchronous rectification can be set to active mode or disabled mode.

active mode

When the SR input is logic low, active mode is enabled and synchronous rectification will occur. This mode prevents load current reversal by turning off synchronous rectification when a zero current level is detected. This prevents reverse conduction of the motor windings.

Disable mode

When the SR input is logic high, synchronous rectification is disabled. This mode is typically used when an external diode is required to transfer power dissipation from the A3977 package to the external diode.

application information

layout.

Printed wiring boards should use heavy duty ground planes.

For best electrical and thermal performance, the driver should be soldered directly to the board.

The load supply terminal V should be separated from an electrolytic capacitor (greater than 47µF recommended) placed as close as possible to the device.

To avoid problems due to capacitive coupling of high dv/dt switching transients, move the bridge output traces away from the sensitive logic input traces. Always drive logic inputs with low source impedance for improved noise immunity.

ground

A star grounding system close to the driver is recommended.

The 44-wire PLCC has an analog ground and a power ground that is internally connected to the package's power tabs (wires 44, 1, 2, 11–13, 22–24, and 33–35).

On a 28-wire TSSOP assembly, the analog ground (wire 7) and power ground (wire 21) must be connected externally together. The copper ground plane located under the exposed thermal pad is usually used as the star ground.

Current sensing

To minimize inaccurate sensing of output current levels caused by ground tracking IR drops, the current sense resistor (R) should have a separate ground return return to the device's star ground. This path should be as short as possible. For low value sense resistors, the IR drop across the traces of the printed circuit board sense resistor can be large and should be considered. Sockets should be avoided as the contact resistance of the socket will cause a change in R.

Allegro MicroSystems recommends by:

Thermal Protection

Typically, the circuit shuts down all drivers when the junction temperature reaches 165°C. Its purpose is only to protect the device from faults caused by excessive connection temperature and should not imply that the output is short-circuited. Thermal shutdown has a hysteresis of about 15°C.

Customer Packing Diagram

FYI - Not for tool use (ref MO-153 AET)

Dimensions are in mm - not to scale

Dimensions exclude mold flash, gate flash, and baffle protrusions

Within the limits shown, the exact housing and lead configuration is at the supplier's discretion