HMP8117 is a high quality NTSC and PAL video decoder with internal A/D converter. It is compatible with NTSC M, PAL B, D, G, H, I, M, N and Combined N (NC) video standards. Both composite and S-video (Y/C) input formats are supported. A 2-line comb filter plus a user-selectable chroma trap filter provides high-quality Y/C separation. User adjustments include brightness, contrast, saturation, hue and sharpness. Vertical Blanking Interval (VBI) data, such as closed captions, widescreen signals and teletext, can be captured and output as BT.656 ancillary data. Closed captioning and widescreen signal information can also be read out via the I 2 C interface. VCR 8482 ; feature provides approved MacroVision™ copy protection bypass and detection.

notes:

1. Intersil lead-free + annealed products use special lead-free material sets; molding compound/die attach material and 100 % matte tin flat termination finish, RoHS compliant and compatible with both SnPb and lead-free soldering operations. Intersil lead-free products are classified as MSL meeting or exceeding the lead-free requirements of IPC/JEDEC J STD-020 at lead-free peak reflow temperatures.

2.PQFP is also known as QFP and MQFP.

feature

(M)NTSC and (B,D,G,H,I,M,N,NC)PAL operation - optional automatic detection of video standards - ITU-R BT.601 (CCIR601) and square pixel operation

Video Analyzer Features - Macro Vision™ Bypass and Detect Digital Anti-Aliasing Filter Power Down Mode Digital Output Format - VMI Compatible - 8-bit, 16-bit 4:2:2 YCbCr - 15-bit (5, 5, 5), 16-bit (5, 6, 5) RGB - linear or gamma corrected - 8-bit BT.656 analog input format - three analog composite inputs - analog Y/C (S-video) input "raw" (oversampled) VBI Data Capture "Slices" VBI Data Capture Capabilities - Closed Captioning - Widescreen Signal (WSS) - BT.653 System B, C and D Teletext - North American Broadcasting Text (NABTS) - World System Teletext (WST) 2 line (1H) Comb Filter Y/C Separator Fast I2C Interface Provides Lead Free Plus Annealing (RoHS Compliant)

application

Multimedia PC

video conference

video compression system

Video Security System

LCD projectors and ceiling panels

introduce

The HMP8117 is designed to decode baseband composite or S-video NTSC and PAL signals and convert them to digital YCbCr or RGB data. In addition to performing basic decoding operations, these devices include hardware decoding of different types of VBI data to generate full-screen blue, black, and color bar patterns. A digital phase locked loop is used to synchronize with all NTSC and PAL standards. Chroma PLL is used to maintain vertical spatial alignment for chroma demodulation implemented with PLL. The PLL is designed to maintain lock-trick mode and multipath noise in the presence of VCR head switches, VCRs. HMP8117 for macro vision (MV) copy protection bypass and detection. External Video Processing Before the video signal is digitized, the decoder has some external processing considerations that are required. This section discusses the HMP8117. Analog Video Inputs The HMP8117 supports three combined or two composite and one S-video input. The three analog video inputs (CVBS 1-3) are used to select which of the three composite video sources to decode. To support S-video applications, the Y channel drives the CVBS3 (Y) analog input, and the C channel drives the C analog input. The analog input must be AC coupled to the video signal, as shown in the application section.

Anti-aliasing filter

Although a 23-tap digital half-band antialiasing filter is provided for each A/D channel, an external passive filter is recommended for best performance. The digital filter has a flat response of 5.4MHz, which is about -3dB using a 6.3MHz bandwidth speed of 27MHz input CLK2 samples. For the CVBSx input, the filter is connected between your and female pins. For the C (chroma) input, the anti-alias filter should be connected before the C input. The recommended filter configuration is shown with reference to the schematic in Figure 20. These filters are flat with a response frequency of 4.2 MHz and a bandwidth of approximately -3 dB at 8MHz. If upgrading from the HMP8115 or the HMP8112A, the previous filter configuration can be used with a slight reduction in bandwidth. Other higher or lower performance filter configurations can be substituted. Video digitization The input signal is offset and scaled to a known video level prior to A/D conversion. After digitization, sample rate converter comb filters are used for color separation and demodulation. A/D conversion Each CVBSX video input channel has a video clamp circuit which is independent of PLL timing. The input clip provides a rough signal offset for locating the sync end in the A/D converter sample range so that the AGC and DC-recovery logic can operate. A/D converted video data is sampled at the CLK2 frequency and then processed through the input sample rate converter. The output level of AGC and ADC after DC restoration processing is:

AGC and DC Restoration

The AGC amplifier attenuates or amplifies the analog video signal to ensure that the blank level generates code 56 or 59. Depends on video standard. Different from the ideal blank level 56 or 59 is used to control the attenuation or gain of the analog video signal. Obtaining a stable DC reference for the digital low-pass filter AGC removes chroma bursts from the back porch of the input signal. DC restore locates the video signal so that the synchronous cue generates code 0. The internal timing window DC recovery of the AGC is shown in Figure 3. Appropriate when the input signal is automatically detected or manually selected.

Input Signal Detection If no input video signal period is detected for 16 consecutive lines, it is the previously detected or programmed video standard. The mask provides an interrupt in the case of "loss of input signal" allowing the host to enable the blue field output if needed. Vertical Sync and Field Detection The vertical sync and magnetic field detection circuits use short time counters to detect the vertical sync sequence data stream in the video. The low time counter accumulates the low time encountered during any sync pulse, including sawtooth and equalization pulses. When the low time count exceeds the vertical sync detection threshold, VSYNC is asserted immediately. Field also asserts that VSYNC is asserted. High for odd fields and even fields. The field is determined by the position in the video line where VSYNC was detected. If VSYNC is detected in the first half of the line, this field is odd. If VSYNC is detected in the second half of a line, the field is uniform. Field outputs will continue to toggle if vertical sync is lost or if there is too much noise to prevent vertical sync from being detected. If lines after 337, 1 or 3 vertical sync cycles are not detected (optional) controlled by GENLOCK register 04H. When this happens the PLL is initialized to the acquisition state. Y/C split composite video signal has luma(Y) and chroma(C) information mixed in the same video signal. The Y/C separation process is responsible for separating and combining the video signal into these two components. The HMP8117 uses a comb filter to minimize correlation with the Y/C separation process. Input Sample Rate Converter The input sample rate converter is used to convert video data sampled at the CLK2 rate to a virtual 4xf SC sample rate for comb filtering and color demodulation. An interpolation filter is used to generate the 4xf SC example, as shown in Figure 2.

comb filter

Perform part of the Y/C separation process using a 2-line comb filter with a single-line delay. When operating during S-video, the Y signal bypasses the comb filter; the C signal is processed by the comb filter because it is a chroma demodulator. Chroma should also enable trap filters to improve performance during PAL operations. Since single-line storage is used, the chrominance is usually vertically offset by half a line from the luma data. Eliminated this May, vertically calibrating chrominance and luminance samples, at the expense of luma's vertical resolution. Bit 0 in Bit Output Format Register 02H controls this option. The output of the chroma demodulation comb filter uses a patented frequency domain conversion to perform Y/C separation and dechroma. Demodulation is performed at a virtual 4xfsc sample rate, using interpolated data samples to generate U and V data. This demodulation process is determined by the 2 U/V sampling rates. Output Sample Rate Converter The output sample rate converter converts the Y, U and V data from the virtual 4xf SC sample rate to the desired output sample rate (ie 13.5MHz). It also aligns the data stream vertically based on the horizontal synchronization information embedded in the digital video. The output sample rate is determined by the input video standard and the selected rectangle/square pixel mode. The output pixel rate is 1/2 the frequency of the CLK2 input clock. Except for the RGB mode that uses the 4:4:4 output format. The CLK2 input decoder requires a stable clock source input from CLK2. For best performance, use termination resistors to minimize pulse overshoot and reflections on the CLK2 input. Since chrominance demodulation uses a virtual 4xf SC, any dither on CLK2 will be in the output pixel as chrominance error. The CLK2 clock frequency must be a valid option standard and desired pixel pattern selected from Table 1 below according to the video.

Pixel output port

Pixel data is output through pins P0-P15. See Table 4 for output pin definitions as a function of output mode. See the "Cyclic Slippage and Real Time" section "Pixel Jitter" for PLL and interface considerations. 8-bit YCbCr output Each YCbCr data byte is output on CLK2. The Y Cb Cr data is multiplexed into [Cb Y cry'cbyCr Y'...], the first active data contains the Cb data. The pixel output timing is shown in the figure. The BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD outputs follow the rising edge of CLK2. When blank is asserted and VBIVALID is de-asserted, YCbCr outputs Y with a value of 16, and Cb and Cr with a value of 128. The outputs are controlled by the GENLOCK register 04H.

Note:

1. Y 0 is the first active luminance pixel data of the line. Cb 0 and cr0 are the first active chroma pixel data in a row. Cb and Cr will cycle every time due to 4:2:2 subsampling. Pixel data is not output during blanking, but values are forced to the blanking level.

16-bit YCbCr, 15-bit RGB, or 16-bit RGB output For 16-bit YCbCr, 15-bit RGB data, or 16-bit RGB output mode, the data output follows the rising edge of CLK2 with DVALID asserted. Linear or gamma correction can output RGB data. Pixel output timing is shown in Figures 10 to 13. The BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD outputs follow the rising edge of CLK2. When blank is asserted and VBIVALID is de-asserted, YCbCr outputs a value of 16 for Y and 128 for Cb and Cr; RGB outputs a value of 0. The behavior of the DVALID output is determined by bit 4 (DVLD_LTC) and bit 5 of the GENLOCK (DLVD_DCYC) control register 04H

notes:

2. Y 0 is the first active luminance pixel data of the line. Cb 0 and cr0 are the first active chroma pixel data in a row. Cb and Cr will cycle every time due to 4:2:2 subsampling. Pixel data is not output during blanking, but values are forced to the blanking level.

3. When DVLD_LTC is set to 1, the polarity of DVALID needs to be set to active low, otherwise DVALID will remain low during active video and only gated with a clock during blanking.

Teletext

The HMP8117 supports ITU-R BT.653 625-line and 525-line teletext systems B, C and D capture. NABTS (North American Broadcasting Teletext Specification) is the same 525-line System C as BT.653, and is also used to transmit Intel Intercast™ information. WST (World System Teletext) is the same as BT.653 System B. Figure 16 shows the structure of a video signal containing teletext data. Monitor scanlines that contain graphic information. If teletext is enabled and teletext data exists, the teletext data is output as BT.656 auxiliary data. Teletext detection teletext decoders monitor scan lines for 16-bit clock break-ins (sometimes called clock sync codes). If found, it locks the clock while the teletext data is sampled and loaded into the shift register, then transfers the data to the internal holding register. If no clock break-in is found, the scanline is assumed to contain video data unless other VBI information such as WSS is detected. If NTSC and (M)PAL, or (B,D,G,H,I,N,NC)PAL line 336 are found before line 23 or 289, the VBI Teletext detection status bit is immediately set to '1' . If not found through these lines, the status bit is reset to "0" immediately. To access teletext data teletext data must be output as BT.656 ancillary data. The I 2 C interface provides graphic information when there is no output bandwidth required. The teletext BT.656 ancillary data format is illustrated. The diagram describes the part of incoming teletext that is sliced and output as part of ancillary data. Blanking interval information after lines containing teletext in the horizontal direction. The actual BT.656 bytes containing the teletext data only contain 4 bits of the actual packet. Note that only the data packets of Figure 16 are sent as auxiliary data; clock run-ins are not included in the data stream.

notes:

4. MSB is the bit number: 271 for system C, row 279 for system B 525, and row 343 for system B 625.

5. Both systems have a clock operating range of 16 bits, not included in the BT.656 auxiliary data stream.

6. On the 525/60 system, the bit rates of the B and C systems are 5.727272mbits/s and the 625/50 systems are 6.9375 and 5.734375mbits/s, respectively.

7. Teletext VBI video signal

notes:

8.ep=even parity of P8-P13.

9. CRC=P8-P14 sum of data ID through last user data word. Defaults to all zeros, ignoring carry.

10. For 525-line System B, bits 280-343 are "0".

11. For System C, bits 272-343 are "0".

"Raw" VBI Data Capture "Raw" data capture of VBI data during blank scan lines may optionally be achieved. In this example, the active samples the line time of the blank scan line at the CLK2 rate to output to the pixel output. This allows software to decode VBI data. The line mask registers specify on which scan lines the "raw" VBI data is to be generated. If the raw VBI All bit is enabled, the video lines are treated as raw VBI data, excluding equalized and jagged lines. The start and end times of the captured "raw" VBI data for the scanline are determined by the start and end of the raw VBI register. This allows "raw" VBI data to be captured correctly regardless of the blank output timing of the active video. Subtract blank level samples from the "raw" VBI data and output the result to the pixel output. NOTE Both "slice" and "raw" VBI data can be on the same line. During NTSC operation, the first line of VBI data may be line 10 and line 272, and the last possible line is the last blank scan line. Lines 1-9 and 264-271 are always bland.

real-time control interface

The real-time control interface (RTCI) outputs timing information data of NTSC/PAL encoder as BT.656 auxiliary equipment. This allows the encoder to generate "clean" output video. RTCI information No. 9 obtained through BT.656 ancillary data is shown in the table. If enabled, this transfer occurs once per line and completes before the start of the SAV sequence. For NTSC encoding, the PSW bit is always "0". Encoded during PAL, representing the sign of V ("0" = negative; "1" = positive) scan line. All internal registers of the host interface can be written to or read by the host processor at any time, except those marked as read-only. The bit descriptions of the control register are listed below starting from Table 10. The HMP8117 supports fast mode (up to 400kbps) I 2 C interface consisting of SDA and SCL pins. device is used via the serial interface. When the interface is not active, SCL and SDA must be pulled high using an external 4kΩ pull-up resistor. The SA input pin determines the HMP8117. If the SA pin is pulled low, the address is 1000100xB. If the SA pin is pulled high through a 10kΩ pull-up resistor, the address is 1000101xB. (At address is the i2cread flag.) Stable when the SCL line is low and when the SCL line is pulled high. Changing the state of the SDA line when SCL is high will be interpreted as an I2C bus start or stop condition, as shown in the figure. During an I 2 C write cycle, the first data byte address after the slave is treated as a control register subaddress and the internal address register is written. Any remaining data bytes sent in the I2C write cycle are written to the control register, slave address register, as indicated by the first byte. The address then register is automatically incremented after each additional data byte sent on the I2C bus in a write cycle. Writes to registers or reserved bits in reserved registers are ignored.

In order to perform a read from a specific control register in the HMP8117, an I2C bus write must first be performed to properly set the address register. One can then perform an I 2 C bus read from the desired control register. Since a read cycle is required there are actually two start conditions as shown. The address register is looped automatically after each byte read during an I2C read. Reserved register return value 00 H