feature

8-bit analog-to-digital converter; 140 MSPS low PLL clock jitter at 140 MSPS maximum slew rate automatic gain matching automatic offset adjustment; 2: 1 input multiplexer; power down via dedicated pin or serial register; 4: 4:4, 4:2:2 and DDR output format modes; variable output drive strength; odd and even field detection; external clock input; regenerated Hsync output; programmable output high impedance control; Hsyncs per Vsync counter ; Lead-free packaging.

application

Premium TVs; Plasma Displays; LCD Digital TVs; HDTVs; RGB Graphics Processing; LCD Monitors and Projectors; Scan Converters.

General Instructions

The AD9983A is a complete 8-bit, 140 ms/sec monolithic analog interface optimized for capturing YPbPr video and RGB graphics signals. Its 140 MSPS encoding rate capability and 300 MHz full power analog bandwidth support all HDTV video modes up to 1080i and 720p and graphics resolutions up to SXGA (1280 x 1024 at 75 Hz).

The AD9983A includes a 140 MHz triple ADC with an internal reference, a PLL, and programmable gain, offset, and clamp controls. The user only provides 1.8V power supply and analog input. The tri-state CMOS output can be powered from 1.8v to 3.3v.

The AD9983A on-chip PLL generates the sampling clock from tri-level sync (for YPbPr video) or horizontal sync (for RGB graphics). The sampling clock output frequency ranges from 10 MHz to 140 MHz. With internal coast generation, the PLL maintains its output frequency without a synchronization input. 32 steps provide sample clock phase adjustment. The output data, synchronization, and clock phase relationships are maintained.

The auto-offset function automatically restores the signal reference level and automatically calibrates any offset differences between the three channels. Automatic channel-to-channel gain matching can be enabled to minimize any gain mismatch between the three channels.

The AD9983A also provides full synchronization processing for composite synchronization and synchronization on green applications. The clamp signal is generated internally or can be provided by the user through the clamp input pin.

Fabricated on an advanced CMOS process, the AD9983A is housed in a space-saving 80-lead, lead-free, LQFP surface-mount plastic package and specified over the 0°C to 70°C temperature range.

Absolute Maximum Ratings

Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions described in the operating section of this specification or any other conditions above is not implied. Long-term exposure to absolute maximum rating conditions may affect device reliability.

Test Level Description

1. 100% production test.

2. 100% products are tested at 25°C, and samples are tested at the specified temperature.

3. Only test samples.

4. Parameters are guaranteed by design and characteristic testing.

5. The parameters are only typical values.

6. 100% production tested at 25°C; guaranteed by design and feature testing.

Thermal resistance

θJA is specified for worst-case, devices soldered in circuit boards intended for surface mount packages.

theory of operation

The AD9983A is a fully integrated solution for capturing and digitizing analog RGB or YPbPr signals for display on advanced TVs, flat panel monitors, projectors and other types of digital displays. The interface is implemented in a high-performance CMOS process and can capture signals at pixel rates up to 140mhz.

The AD9983A includes all necessary input buffering, signal DC recovery (clamping), offset and gain (brightness and contrast) adjustments, pixel clock generation, sample phase control, and output data formatting. All controls are available through a 2-wire serial interface (IC). The full integration of these sensitive analog functions enables straightforward system design with low sensitivity to physical and electrical environments.

The typical power consumption of the device is less than 800mW and the operating temperature range is 0°C to 70°C without special consideration of environmental factors.

digital input

All digital inputs on the AD9983A operate to 3.3V CMOS levels. The following digital inputs are 5 V tolerant (i.e. applying 5 V to them will not cause any damage): HSYNC0, HSYNC1, VSYNC0, VSYNC1, SOGIN0, SOGIN1, SDA, SCL, and CLAMP.

Analog Input Signal Processing

The AD9983A has six high-impedance analog input pins for the red, green, and blue channels. They can accommodate signals from 0.5 V to 1.0 V pp.

The signal is usually brought to the interface board via a DVI-I connector, a 15-pin D connector, or an RCA connector. The AD9983A should be placed as close as possible to the input connectors. Signals should be routed to the IC input pins using matched impedance traces (typically 75Ω).

At the input pins, the signal should be resistor terminated (75Ω to the signal ground return) and capacitively coupled to the AD9983A input through a 47 nF capacitor. These capacitors form part of the DC recovery circuit.

In an ideal world with perfectly matched impedances, the widest possible signal bandwidth would yield the best performance. The wideband input (300 MHz) of the AD9983A can continuously track the input signal as it moves from one pixel level to the next, and can digitize the pixel over long flat pixel times. In many systems, however, there are mismatches, reflections, and noise, which can cause excessive ringing and distortion of the input waveform. This makes it more difficult to build a sampling stage that provides good image quality. A small inductor in series with the input can effectively reduce the input bandwidth slightly and provide a high-quality signal over a wider range of conditions. In the circuit shown in Figure 3, a Fair Rite #2508051217Z0 high-speed, signal chip bead inductor provides good results in most applications.

HSYNC and VSYNC inputs

The interface also accepts Hsync and Vsync signals for generating pixel clock, clamp timing, coast and field information. These signals can be sync signals directly from the graphics source or preprocessed TTL or CMOS level signals.

The Hsync input includes a Schmitt trigger buffer for noise immunity and long rise time signals. In a typical PC-based graphics system, the sync signal is just a TTL-level driver, supplied with an unshielded wire in the monitor cable. Therefore, no termination is required.

Serial control port

The serial control port is designed for 3.3V logic; however, it can tolerate 5V logic signals. See the 2-Wire Serial Control Port section.

output signal processing

The digital outputs operate from 1.8 V to 3.3 V (VDD).

clamp

RGB clamping

To properly digitize the input signal, the DC offset of the input must be adjusted to fit the range of the onboard ADC.

Most graphics systems produce RGB signals that are black at ground and white at around 0.75 volts. However, if the sync signal is embedded in the graph, the sync tip is usually at ground, 300mV for black and about 1.0v for white. Some common RGB line amplifier boxes use a transmitter follower buffer to split the signal and increase drive capability. This introduces a 700 mV DC offset to the signal, which must be removed for the AD9983A to capture properly.

The key to clamping is to identify the part (time) of the signal when the graphics system is known to produce black. Then an offset is introduced which causes the ADC to produce a black output (code 0x00) when there is a known black input. Then, when other signal levels are processed, the offset remains in place and the entire signal is shifted to remove the offset error.

In most PC graphics systems, black is transmitted between the active video lines. With a CRT monitor, when the electron beam finishes writing the horizontal lines on the screen (right side), the electron beam is deflected quickly to the left side of the screen (called the horizontal return) and provides a black signal to prevent the electron beam from interfering with the image.

In systems with embedded sync, a signal darker than the black signal (Hsync) is briefly generated, signaling the CRT to start backtracking. Since the input is not at the black level at this point, it is important to avoid clamping during Hsync. Of course, there is usually a period of time behind Hsync, called the back porch, and here's a good black reference. Clamping should be done at this point.

Clamp timing can be established by simply executing the clamp pin at the appropriate time with Clamp Source (Register 0x18, Bit 4) = 1. The polarity of this signal is set by the clamp polarity bits (Register 0x1B, Bits[7:6]).

A simpler clamp timing method uses the AD9983A internal clamp timing generator. The Clamp Placement register (Register 0x19) is programmed with the number of pixel cycles that should elapse after the trailing edge of Hsync before clamping begins. The second register clamp duration (Register 0x1A) sets the duration of the clamp. Both of these are 8-bit values, providing considerable flexibility in clamp generation. The clamp timing is referenced to the trailing edge of the Hsync because the back porch (black reference) always follows the Hsync, although the Hsync duration varies widely. A good starting point for establishing the clamp is to set the clamp to 0x04 (provides 4 pixel periods for the graphics signal to settle after sync) and the clamp duration to 0x28 (provides 40 pixel periods to re-establish the black reference ).

Clamping is done by placing an appropriate charge on the external input coupling capacitor. The value of this capacitor affects the performance of the clamp. If it is too small, there will be significant amplitude changes within the horizon time (between clamping intervals). If the capacitor is too large, the clamp will take too long to recover from large changes in the input signal offset. The recommended value (47 nF) resulted in recovery from a 100 mV step error on an 85 Hz XGA signal to within 30 lines of 1 LSB with a clamp duration of 20 pixel periods.

YPbPr clamping

YPbPr graphics signals are slightly different from RGB signals because the dc reference level (the black level in an RGB signal) for a color-difference signal is at the midpoint of the video signal, not at the bottom. The three inputs consist of luminance (Y) and color difference (Pb and Pr) signals. For color difference signals, it needs to be clamped to the mid-scale range of the ADC range (512) instead of the bottom of the ADC range (0), while the Y channel is clamped to ground.

The clamp can be locked to midscale instead of ground by setting the clamp select bits in the serial bus register. Each of the three converters has its own select bit so they can be clamped independently on mesoscale or ground. These bits are located in Register 0x18, Bits[3:1]. The mid-scale reference voltage is generated internally by each converter.

Gain and offset controls

The AD9983A contains three PGAs, one for each of the three analog inputs. The range of the PGA is sufficient to accommodate the input signal, with the input range from 0.5 V to 1.0 V full scale. Gains are set in three 7-bit registers (Red Gain [0x05], Green Gain [0x07], Blue Gain [0x09]). For each register, a gain setting of 0 corresponds to the highest gain, while a gain setting of 127 corresponds to the lowest gain. Note that increasing the gain setting will result in a reduction in the contrast of the image.

The offset control moves the analog input, resulting in a change in brightness. Three 9-bit registers red offset [register 0x0B and register 0x0C], green offset [register 0x0D and register 0x0E] and blue offset [register 0x0F and register 0x10] provide independent settings for each channel. Note that the function of the offset register depends on whether automatic offset is enabled (Register 0x1B, Bit 5).

If manual offset is used, seven bits of the offset register (for red channel register 0x0B, Bits[6:0]) control the absolute offset added to the channel. The offset control provides an adjustment range of ±63 LSB, with an offset of 1 LSB corresponding to an output code of 1 LSB.

Auto offset

In addition to the manual offset adjustment mode, the AD9983A includes circuitry to automatically calibrate each channel's offset. By monitoring the output of each ADC during the back porch of the input signal, the AD9983A can adjust itself to remove any offset error in its own ADC channel and any offset error present in the incoming graphics or video signal.

To activate auto-offset mode, set Register 0x1B, Bit 5 to 1. Next, the target code registers (Register 0x0B to Register 0x10) must be programmed. The value programmed into the target code register should be the output code required by the AD9983A ADC, which is generated within the back porch reference time. For example, for RGB signals, all three registers are usually programmed to code 2, while for Y Pb Pr signals, the green (Y) channel is usually programmed to code 2, and the blue and red channels (Pb and Pr) are usually set to 128. Target The code register has 9 bits per channel and is in two's complement format. This allows programming of any value between -256 and +255. Although any value within this range can be programmed, the AD9983A offset range may not reach every value. Expected target code values range from (but are not limited to) –40 to –1, 1 to 40 when ground clamped, and 88 to 168 when midscale clamped. Note that target code 0 is invalid.

Negative target codes are included to replicate features present in manual offset adjustments. The benefit of being imitated is the ability to easily adjust the brightness of the display. By setting the target code to a value that does not correspond to the ideal ADC range, the end result is a lightened or darkened image. Object codes higher than ideal produce brighter images. Target codes that are lower than ideal will result in darkened images.

The ability to program object code provides a great deal of freedom and flexibility. In most cases, all channels are set to 1 or 128, but the flexibility to choose other values allows intentional skew to be inserted between channels. It also allows the ADC range to be tilted so that voltages outside the normal range can be digitized. For example, setting the target code to 40 allows digitization and evaluation of sync cues that are typically below black levels.

The internal logic of the auto-skew circuit requires 16 data clock cycles to perform its function. This operation is performed immediately after the clamping pulse. Therefore, it is important to end the clamp signal at least 16 data clock cycles before activating the video. This is true regardless of whether the AD9983A internal clamp circuit or an external clamp signal is used. The auto-offset function can be programmed to run continuously or in one shot (see Auto-Offset Hold, Register 0x2C, Bit 4). In continuous mode, the update frequency can be programmed (Register 0x1B, Bits[4:3]). It is recommended to update every 64 Hsyncs.

Guidelines for basic auto-offset operation are shown in Tables 6 and 7.

Automatic gain matching

The AD9983A includes circuitry to match the gain between the three channels to within 1% of each other. Matching the gain of each channel is necessary to achieve a good color balance on the monitor. On products without this feature, gain matching is achieved by writing software that evaluates each channel's output, calculates the gain mismatch, and then writes the value to each channel's gain register to compensate. With automatic gain matching, this software routine is no longer required. To activate automatic gain matching, set Register 0x3C, Bit 2 to Bit 1.

Automatic gain matching and automatic offset have similar timing requirements. It requires 16 data clock cycles to perform its function, starting immediately after the end of the clamp pulse. Unlike automatic offset, it does not require these 16 clock cycles to occur within the back porch reference time, although this is recommended. During the automatic gain match operation, the data output of the AD9983A is frozen (held at the value before the operation). The automatic gain matching function can be programmed to run continuously or in one shot (see 0x3C Bit[3] Automatic gain matching hold section).

Sync on Green

Synchronization on the green input (SOGIN0, SOGIN1) operates in two steps. First, they set the baseline clamp level of a negative peak detector. Second, they set the sync trigger level to a programmable (Register 0x1D, Bits[7:3]) level above the negative peak (typically 128 mV). The green sync input must be AC coupled to the green analog input through its own capacitor. The value of the capacitor must be 1 nF±20%. This connection is not required if sync on green is not used. The sync on green signal always has a negative polarity.

reference bypass

REFLO and REFHI are connected to each other through 10µF capacitors. The input ADC circuit uses these references.

clock generation

The PLL is used to generate the pixel clock. The Hsync input provides the reference frequency to the PLL. A voltage controlled oscillator (VCO) produces a higher pixel clock frequency. The pixel clock is divided by the PLL division value (Register 0x01 and Register 0x02) and compared to the Hsync input. Any errors are used to shift the VCO frequency and maintain lock between the two signals.

The stability of this clock is a very important factor in providing the sharpest and most stable images. During each pixel time, there is a period in which the signal is shifted from the old pixel amplitude and fixed at its new value. Then for a while, when the input voltage stabilizes, the signal must transition to a new value (see Figure 6). The ratio of slew time to settling time is a function of graphics DAC bandwidth and transmission system bandwidth (cable and termination). It is also a function of the overall pixel rate. Obviously, if the dynamics of the system remain the same, then the slew and settling times are also fixed. This time must be subtracted from the total pixel period to preserve stable periods. At higher pixel frequencies, the overall cycle time is shorter, as is the stable pixel time.

Any jitter in the clock reduces the accuracy of determining the sample time, which must also be subtracted from the stable pixel time. In the design of the AD9983A clock generation circuit, considerable care has been taken to minimize jitter. In all operating modes, the AD9983A has low clock jitter such that the reduction in effective sampling time due to jitter is negligible.

PLL characteristics are determined by loop filter design, PLL charge pump current, and VCO range settings. The design of the loop filter is shown in Figure 7. Table 10 lists the recommended settings for the VCO range and charge pump current for VESA standard display modes.

Four programmable registers are provided to optimize the performance of the PLL. These registers are a 12-bit divisor register, a 2-bit VCO range register, a 3-bit charge pump current register, and a 5-bit phase adjustment register.

12-bit divisor register

The incoming Hsync frequency can accommodate any Hsync as long as the product of Hsync and the PLL divisor is within the operating range of the VCO. The PLL multiplies the frequency of the Hsync signal to produce a pixel clock frequency in the range of 10mhz to 140mhz. The divisor register controls the exact multiplication factor. This register can be set to any value between 2 and 4095 as long as the output frequency is within range.

2-bit VCO Range Register

To improve the noise performance of the AD9983A, the operating frequency range of the VCO is divided into four overlapping regions. The VCO range register sets this operating range. The frequency ranges of the four regions are shown in Table 8.

Three-bit charge pump current register

This register changes the current driving the low-pass loop filter. Table 9 lists possible current values.

5-bit phase adjustment register

The phase of the generated sampling clock can be shifted to locate the optimal sampling point within the clock cycle. The phase adjustment register provides 32 phase shift steps of 11.25° each. The Hsync signal with the same phase shift is available on the HSOUT pin. Phase adjustment is still available if an external pixel clock is used. The COAST pin or internal COAST is used to allow the PLL to continue operating at the same frequency without an incoming Hsync signal or during disturbances in Hsync (eg from equalization pulses). This can be used during vertical sync or any other time when the Hsync signal is not available.

The polarity of the coast signal can be set through the coast polarity register (Register 0x18, Bits[6:5]). Additionally, the polarity of the Hsync signal can be set through the Hsync Polarity register (Register 0x12, Bits[5:4]). For Hsync and coast, a value of 1 is highly active. The internal glide function is driven by the Vsync signal, which is usually when the Hsync signal can be disturbed by extra equalization pulses.

Synchronous processing

The inputs to the sync processing section of the AD9983A are a combination of digital Hsyncs and Vsyncs, an analog green sync or sync-on-Y signal, and an optional external coast signal. From these signals, it generates an accurate, jitter-free clock from the PLL; odd and even field signals; HSOUT and VSOUT signals; an hsync count per Vsync; and a programmable SOGOUT. The main sync processing blocks are sync slicer, sync separator, Hsync filter, Hsync regenerator, Vsync filter and coast generator.

• Hsync regenerator is used to recreate clean Hsync signal, although not low jitter, but can be used for pattern detection and calculation of Hsync per Vsync.

• The Vsync filter is used to eliminate spurious Vsync, maintain a stable timing relationship between the Vsync and Hsync output signals, and produce odd and even field outputs.

• The coast generator produces a robust coast signal, allowing the PLL to maintain its frequency without Hsync pulses.

• The sync slicer extracts the sync signal from the green graphics or luma video signal connected to the SOGINx input and outputs a digital composite sync.

• The task of the sync splitter is to extract Vsync from the composite sync signal, which can come from the sync slicer or the HSYNCx input.

• The Hsync filter is used to remove any extraneous pulses from the HSYNCx or SOGINx inputs, outputting a clean, low-jitter signal suitable for pattern detection and clock generation.

Sync Slicer

The purpose of the sync slicer is to extract the sync signal from the green graphics or luma video signal connected to the SOG input. The synchronization signal is extracted in a two-step process. First, the SOG input is clamped to the negative peak (typically 0.3V below black level). Next, the signal goes to a comparator with a variable trigger level (set by Register 0x1D, Bits[7:3]), but nominally 0.128 V above the clamp level. The sync slicer output is a digital composite sync signal containing Hsync and Vsync information (see Figure 9).

sync separator

As part of the synchronization process, the task of the sync separator is to extract Vsync from the composite sync signal. It works by keeping the Vsync signal active much longer than the Hsync signal. By using a digital low-pass filter and a digital comparator, it rejects pulses with small durations (like hsync and equalization pulses), and only passes pulses with large durations, like Vsync (see Figure 9).

The thresholds of the digital comparators are programmable for maximum flexibility. To program the threshold duration, write a value (N) to Register 0x11. The resulting pulse width is N×200 ns. Therefore, if N=5, the digital comparator threshold is 1µs. Any pulses less than 1 μs are rejected, while any pulses greater than 1 μs are passed.

There are two factors to consider when using sync delimiters. First, the resulting clean Vsync output is delayed from the original Vsync for a duration equal to the digital comparator threshold (N × 200ns). Second, there is some variability in the 200ns doubling value. Maximum variability across all operating conditions is ±20% (160 ns to 240 ns). Since normal Vsync and Hsync pulse widths differ by a factor of about 500 or more, 20% variability is not a problem.

Sync Filters and Regenerators

The Hsync filter is used to remove any extraneous pulses from the Hsync or SOGIN input, outputting a clean, low-jitter signal suitable for pattern detection and clock generation.

The Hsync regenerator is used to recreate a clean Hsync signal, although not low jitter, but can be used for pattern detection and calculation of Hsync per Vsync. The Hsync regenerator's tolerance for extraneous and missing pulses on the Hsync input, but not suitable for PLL use when creating pixel clocks due to jitter.

The Hsync regenerator runs automatically and requires no setup to run. Hsync filters require a setup filter window. The filter window sets a periodic time window around the leading edge of the regenerated Hsync that allows a valid Hsync to occur. The general idea is that extraneous pulses on the sync input occur outside this filter window and are therefore filtered out. To set the filter window timing, program a value (x) into register 0x23. The resulting filter window time is ±x times 25 ns around the leading edge of the regenerated Hsync. As with the sync separator threshold multiplier, a ±20% variance in the 25 ns multiplier is allowed to account for all operating conditions (20 ns to 30 ns range).

The second output of the Hsync filter is a status bit (Register 0x25, Bit 1) that tells the incoming sync signal whether there are extraneous pulses. Usually, extraneous pulses are included for copy protection purposes, so this status bit can be used to detect.

The filtered Hsync of the pixel clock generated by the PLL (instead of the raw HSYNCx/SOGINx signals) is controlled by Register 0x20 Bit 2. The regenerated Hsync (rather than the original Hsync/SOGIN signal) used for synchronization is controlled by Register 0x20 Bit 1. It is recommended to use filtered Hsync and regenerated Hsync. See Figure 10 for filtered Hsync.

Vsync filter and parity field

The Vsync filter is used to remove spurious Vsync, maintain a stable timing relationship between the Vsync and Hsync output signals, and produce odd and even field outputs.

The filter works by checking the position of Vsync relative to Hsync and moving it slightly in time if necessary. Its purpose is to prevent the Vsync and Hsync leading edges from switching at the same time, thereby eliminating confusion about when the first line of the frame occurs. Register 0x14, Bit 2 enables the Vsync filter. The Vsync filter is recommended in all cases (including interlaced video) and is required when using hsync per Vsync counter. Figures 11 and 12 illustrate the parity field determination in both cases.

power management

To meet display requirements for low standby power, the AD9983A includes a power-down mode. The power down state can be controlled manually (via pin 17 or register 0x1E, bit 3) or automatically by the chip. If automatic control (Register 0x1E, Bit 4) is selected, the AD9983A decision is based on the state of the Sync Detect bits (Register 0x24, Bit 2, Bit 3, Bit 6, and Bit 7). If the Hsync or sync on green input is detected on any input, the chip will power up, otherwise it will power down. For manual control, the AD9983A allows flexible control through dedicated pins and register bits. Dedicated pins allow a hardware watchdog circuit to control power-down, while register bits allow software-controlled power-down. When using manual power-down control, the polarity of the power-down pin must be set (Register 0x1E, Bit 2) regardless of whether this pin is used. If not used, it is recommended to set the polarity to active high and hardwire the pin to ground with a 10 kΩ resistor.

In power-down mode, several circuits continue to function normally. The serial registers and sync detection circuitry maintain power so that the AD9983A can wake up from a power-down state. The bandgap circuit maintains the power supply as it is required for synchronous detection. The sync on green and SOGOUT functions continue to work because the SOGOUT output is required when sync detection is performed by the secondary chip. All of these circuits require minimal power to work. Typical standby power for the AD9983A is approximately 50 megawatts.

There are two options to choose from when power is off. These are controlled by Bit 0 and Bit 1 in Register 0x1E. Bit 0 controls whether the SOGOUT pin is in high impedance. In most cases, the user will not put the exudate into a high impedance state during normal operation. The options for placing the seepage trenches in high impedance consist primarily of allowing factory test mode. Bit 1 keeps the AD9983A powered up while only placing the output in high impedance. This option is useful when the data outputs of two chips are connected to one PCB and the user wants to switch between the two chips on the fly.

1. The automatic power-off control is set by bit 4 of register 0x1E.

2. Power down is controlled by OR "ing" pin 17 with register 0x1E bit 3. The polarity of pin 17 is set by Register 0x1E Bit 2.

3. Sync detection is determined by Register 0x24, Bit 2, Bit 3, Bit 6, and Bit 7.

Timing diagram

The timing diagrams in Figure 13 through Figure 16 show the operation of the AD9983A. When creating the output data clock signal, its rising edge always occurs between data transitions and can be used to externally latch the output data. There is a pipe in the AD9983A that must be flushed before valid data can be obtained. This means that six datasets will be displayed before valid data is available.

Sync timing

Hsync is processed in the AD9983A to remove the ambiguity of the leading edge timing relative to the phase delayed pixel clock and data.

The Hsync input is used as a reference to generate the pixel sampling clock. The sampling phase can be adjusted relative to Hsync in 32 steps through the full 360° via the phase adjustment register (to optimize pixel sampling time). Display systems use Hsync to adjust memory and display write cycles, so it is important to maintain a stable timing relationship between the Hsync output (HSOUT) and the data clock (DATACK).

In the AD9983A, there are three cases for Hsync: First, the Hsync input polarity is determined and therefore has a known output polarity. The known output polarity can be programmed as active high or active low (Register 0x12, Bit 3). Second, HSOUT is aligned with the packet and data output. Third, the duration of HSOUT (pixel clock) is set via Register 0x13. HSOUT is the sync signal that should be used to drive the rest of the display system.

taxi time

In most computer systems, the Hsync signal is provided continuously over a dedicated line. In these systems, coast inputs and functions are unnecessary and should not be used.

However, in some systems, Hsync is disturbed during vertical synchronization (Vsync). In some cases, the Hsync pulse disappears. In other systems, such as those employing a composite sync (Csync) signal or embedded sync on green, Hsync may include equalization pulses or other distortion during Vsync. It is important to ignore these distortions in order to avoid disturbing the clock generator during Vsync. If the pixel clock PLL sees extraneous pulses, it tries to lock to this new frequency and changes the frequency at the end of the Vsync period. Then it takes a few lines of correct Hsync timing to recover at the start of a new frame, causing the image to tear at the top of the display.

Coast input is provided to eliminate this problem. It is an asynchronous input that disables the PLL input and keeps the clock at its current frequency. The PLL can run several lines freely without significant frequency drift. Coast can be generated internally by the AD9983A (see Register 0x18) or provided externally by the graphics controller.

When the internal coast is selected (Register 0x18, Bit 7 = 0, Register 0x14, Bits[7:6] select the source), Vsync is used as the basis for determining the coast position. The internal coast signal enables the programmed number of Hsync cycles before the periodic Vsync signal (pre-broadcast register 0x16) and discards the programmed number of Hsync cycles after Vsync (post coast register 0x17). It is recommended to enable the Vsync filter when using the internal coast function to allow the AD9983A to accurately determine the amount and location of hsync/Vsync. In many applications where interrupts occur and coast is used, a value of 2 for pre-baking and a value of 10d for post-baking is sufficient to avoid most extraneous pulses.

output formatter

The output formatter can generate several output formats for presentation to the 24 data output pins. Table 12 lists the output formats and pin assignments for each format. Additionally, there are several clock options for the output clock. Users can select pixel clock, 90° phase-shifted pixel clock, 2x pixel clock or fixed frequency 40mhz clock for testing purposes. The output clock can also be inverted.

Data outputs are available as 24-pin RGB or YCbCr, or an auxiliary channel if 4:2:2 or 4:4:4 DDR is selected. This second channel is always 4:2:2 DDR and allows the flexibility of using a second channel with the same video data that can be utilized by another display or even a storage device. Depending on the output mode selection, the main output can be 24 pins, 16 pins, or just 12 pins.

Mode description

4:4:4

All channels output 8 data bits simultaneously.

Data is aligned to the negative edge of the clock for easy capture.

This is the normal 24-bit output mode for RGB or 4:4:4 YCbCr.

4:2:2

The red and green channels contain 4:2:2 formatted data (16 pins), with Y data on the green channel and Cb, Cr data on the red channel. Data is aligned to the negative edge of the clock. The blue channel contains the secondary channel with 4:2:2 DDR data in Cb, Y, Cr, Y format. The data edges are aligned with both edges of the pixel clock, so a 90° clock may be required to capture DDR data.

4:4:4 demethylation reductase

This mode outputs full 4:4:4 data on 12-bit red and green channels, saving 12 pins. The top half (RGB[11:0]) of the 24-bit data is sent on the rising edge, and the bottom half (RGB[23:12]) is sent on the falling edge. DDR4:2:2 data is sent on the blue channel, same as 4:2:2 mode.

RGB[23:0] = R[7:0] + G[7:0] + B[7:0], so RGB[23:12] = R[7:0] + G[7:4] and RGB[11:0] = G[3:0] + B[7:0]

2-wire serial control port

Provides a 2-wire serial interface control interface. Up to two AD9983A devices can be connected to the 2-wire serial interface, each with a unique address.

The 2-wire serial interface includes clock (SCL) and bidirectional data (SDA) pins. The analog tablet interface acts as a slave to receive and transmit data over the serial interface. When the serial interface is inactive, the logic levels on SCL and SDA are pulled high by external pull-up resistors.

Data received or transmitted on the SDA line must remain stable for the duration of the SCL positive pulse. Data on SDA can only be changed when SCL is low. If SDA changes state while SCL is high, the serial interface interprets the operation as a start or stop sequence.

The following are the five components of serial bus operation:

• Start signal

• Slave address byte

• Base register address byte

• Read or write data bytes

• Stop signal

Communication is initiated by sending a start signal when the serial interface is inactive (SCL and SDA high). When SCL is high, the start signal on SDA is a high-to-low transition. This signal alerts all slave devices that a data transfer sequence is imminent.

The first 8 bits of data transferred after the start signal include the 7-bit slave address (first 7 bits) and a single R/W bit (8th bit). The R/W bit indicates the data transfer direction for reading from 1 or writing 0 on the slave device. If the transmitted slave address matches the device address, the AD9983A confirms the match by driving SDA low on the ninth SCL pulse. If the addresses do not match, the AD9983A does not acknowledge.

Data transfer via serial interface

For each data byte read or written, the MSB is the first bit in the sequence.

If the AD9983A does not acknowledge the master during the write sequence, SDA is held high so that the master can generate a stop signal. If the master device does not acknowledge the AD9983A during the read sequence, the AD9983A interprets this as an end of data. SDA is held high so that the host can generate a stop signal.

Writing data to a specific control register of the AD9983A requires writing the 8-bit address of the control register of interest after the slave address is established. This control register address is the base address for subsequent write operations. After the base address is auto-incremented by one byte of data, the data byte written is expected to be the base address. If the number of bytes transferred exceeds the number of available addresses, the address is not incremented and remains at its maximum value of 0x2E. Any base address above 0x2E will not generate an acknowledge signal. Data is read from the AD9983A's control register in a similar fashion. A read requires two data transfer operations:

The base address must be written with the lower R/W bits of the slave address byte to set up sequential read operations. Reads (high R/W bits of the slave address byte) start from the previously established base address. The address of the read register is automatically incremented after each byte transfer.

To terminate the read/write sequence to the AD9983A, a stop signal must be sent. The stop signal consists of a low-to-high transition of SDA when SCL is high.

Repeated start signals occur when a master device driving a serial interface generates a start signal without first generating a stop signal to terminate the current communication. This is used to change the communication mode (read, write) between slave and master without releasing the serial interface line.

Serial Interface Read/Write Example

1. Start signal

2. Slave address byte (R/W bit = low)

3. Base address byte

4. Data byte to base address

5. Stop signal

Write four consecutive control registers

1. Start signal

2. Slave address byte (R/W bit = low)

3. Base address byte

4. Data byte to base address

5. Data byte to (base address + 1)

6. Data byte to (base address + 2)

7. Data byte to (base address + 3)

8. Stop signal

read from a control register

1. Start signal

2. Slave address byte (R/W bit = low)

3. Base address byte

4. Start signal

5. Slave address byte (R/W bit = high)

6. Data bytes from base address

7. Stop signal

read from four consecutive control registers

1. Start signal

2. Slave address byte (R/W bit = low)

3. Base address byte

4. Start signal

5. Slave address byte (R/W bit = high)

6. Data byte from base address

7. Data byte slave (base address + 1)

8. Data byte slave (base address + 2)

9. Data byte slave (base address + 3)

10. Stop signal

2-Wire Serial Register Map

The AD9983A is initialized and controlled by a set of registers that determine the mode of operation. Control registers are written and read by an external controller through the 2-wire serial interface port.

2-Wire Serial Control Register

Chip identification

0x00 Bits[7:0] Chip version

An 8-bit register representing the silicon version.

Crossover Control

0x01 Bits[7:0] PLL divide ratio MSBs

The 12-bit PLL is divided by the 8 MSBs of the PLLDIV.

The PLL derives the pixel clock from the incoming Hsync signal. The pixel clock frequency is then divided by an integer value so that the output is phase locked to Hsync. The PLLDIV value determines the number of pixels per line (pixels plus horizontal blanking overhead). This is typically 20% to 30% more than the number of active pixels in the display.

The 12-bit value of the PLL divider supports division ratios from 2 to 4095 as long as the output frequency is within range. The higher the value loaded in this register, the higher the resulting clock frequency relative to the fixed Hsync frequency.

VESA has established some standard timing specifications that will help determine the PLLDIV value as a function of horizontal and vertical display resolution and frame rate (see Table 10). However, many computer systems do not fully comply with these recommendations and these numbers should only be used as a guide. The display system manufacturer should provide a means to automatically or manually optimize the PLLDIV. An incorrectly set PLLDIV will often produce one or more vertical noise bars on the display. The larger the error, the higher the number of bars produced.

The power-on default for PLLDIV is 1693. PLLDIVM=0x69, PLLDIVL=0xDX.

The AD9983A only updates the full divide ratio when writing to the LSB. Writing to this register alone will not trigger an update.

0x02 Bits[7:4] PLL divide ratio lsb

12-bit PLL divided by 4 lsb than PLLDIV.

The power-on default for PLLDIV is 1693.

PLLDIVM=0x69, PLLDIVL=0xDX.

Clock Generator Control

0x03 Bits[7:6] VCO range selection

Two bits that determine the operating range of the clock generator. The VCO range must be set to correspond to the desired operating frequency (input pixel rate). Phase-locked loops have the best jitter performance at high frequencies. For this reason, in order to output a low pixel rate and still get good jitter performance, the PLL actually operates at a higher frequency, but then divides the clock rate by . See Table 15 for pixel rates set for each VCO range. The PLL output divisor is automatically selected by the VCO range setting. The power-up default is 01.

0x03 Bits[5:3] Charge Pump Current

Three bits of current that drive the loop filter are established in the clock generator. The current must be set to correspond to the desired operating frequency. The power-on default is current=001.

0x03 Bit[2] External clock enable

This bit determines the source of the pixel clock.

A logic 0 enables the internal PLL that generates the pixel clock from an externally supplied Hsync.

A logic 1 enables the external EXTCK input pin. In this mode, the PLL divide ratio (PLLDIV) is ignored. Clock phase adjustment (phase) still works. The power-on default value is EXTCK=0.

Phase adjustment

0x04 Bits[7:3]

Phase adjustment for the dynamic link library used to generate the ADC clock. A 5-bit value that adjusts the sampling phase in 32 steps per pixel time. Each step represents an 11.25° displacement of the sampling phase. The boot default value is 16.

input gain

0x05 Bits[6:0] Red channel gain adjustment

7-bit red channel gain control. The AD9983A accommodates a full-scale range between 0.5 V and 1.0 V pp. Setting the red gain to 127 corresponds to an input range of 1.0 V. A gain of 0 in red will establish a 0.5 V input range. Note that increasing the red gain results in an image with less contrast (the input signal uses fewer available converter codes). The value written to this register will not be updated until the following register (register 0x06) is written to 0x00. The boot default value is 100 0000.

0x07 Bits[6:0] Green channel gain adjustment

7-bit green channel gain control. See the red channel gain adjustment above. A register update requires writing 0x00 to register 0x08.

0x09 Bits[6:0] Blue channel gain adjustment

7-bit blue channel gain control. See the red channel gain adjustment above. Register updates require writing 0x00 to register 0x0A.

input offset

0x0B Bits[7:0] Red channel offset

8-bit MSB of the red channel offset control. Together with the LSB in the register below, there are 9 bits of dc offset control in the red channel. The offset control moves the analog input, resulting in a change in brightness. Note that the function of the offset register depends on whether automatic offset is enabled (Register 0x1B, Bit 5).

If automatic offset is disabled, the lower 7 bits of the offset register (Register 0x0B, Bits[5:0] plus Register 0x0C, Bit 7 for the red channel) control the absolute offset added to the channel. The offset control provides an adjustment range of ±63 LSB, with an offset of 1 LSB corresponding to an output code of 1 LSB.

If automatic offset is enabled, the 9-bit offset (consisting of 8 bits of the MSB register and 7 bits of the following registers) determines the clamp target code. A 9-bit offset consists of 1 sign bit plus 8 bits. If the register is programmed to 130d, at the end of the clamp period, the output code is equal to 130d. Incrementing the offset register setting by 1 LSB will add an offset of 1 LSB regardless of the automatic offset setting. The value written to this register is not updated until the LSB register (Register 0x0C) is also written.

0x0C Bit[7] Red channel offset LSB

The LSB of the red channel offset control is combined with the 8 bits of the MSB in the previous register to form a 9-bit offset control.

0x0D Bits[7:0] Green channel offset

8-bit green channel offset control. See Red Channel Offset (0x0B). This register is only updated when register 0x0E is written concurrently.

0x0E Bit[7] Green Channel Offset LSB

The LSB of the green channel offset control is combined with the 8 bits of the MSBs in the previous register to form a 9-bit offset control.

0x0F Bits[7:0] Blue channel offset

8-bit blue channel offset control. See 0x0B Bits[7:0]

Red channel offset. only if register 0x10 is also written.

0x10 bit[7] blue channel offset LSB

The LSB of the blue channel offset control is combined with the 8 bits of the MSB in the previous register to form a 9-bit offset control.

HSYNC control

0x11 Bits[7:0] Sync Delimiter Threshold

This register sets the threshold for the digital comparator of the sync separator. The value written to this register is multiplied by 200 ns to obtain the threshold. Therefore, if a value of 5 is written, the digital comparator threshold is 1 μs, and the sync separator rejects any pulses smaller than 1 μs. There are some variations in the 200ns multiplier value. Maximum variability across all operating conditions is ±20% (160 ns to 240 ns). Since normal Vsync and Hsync pulse widths differ by a factor of about 500 or more, 20% variability is not a problem. The power-on default is 32 DDR.

0x12 bit[7] Hsync source rewrite

This is the active Hsync overlay. Setting this to 0 allows the chip to determine the active Hsync source. Setting it to 1 uses Register 0x12, Bit 6 to determine the active Hsync source. The power-on default value is 0.

0x12 bit[6] Hsync source

This bit selects the source of Hsync for PLL and sync processing only when Register 0x12, Bit 7 is set to 1 or both syncs are active. Setting this bit to 0 specifies Hsync on the input. Setting it to 1 will select Hsync from SOG. The boot default value is 0.

0x12 Bit[5] Hsync Input Polarity Override

This bit determines whether the chip selects the Hsync input polarity or not. Setting this bit to 0 allows the chip to automatically select the polarity of the input Hsync; setting it to 1 means that Bit 4 of Register 0x12 specifies the polarity. The boot default value is 0.

0x12 Bit[4] Hsync Input Polarity

If Bit 5 of Register 0x12 is 1, the value of this bit specifies the polarity of the input Hsync. Setting this bit to 0 indicates an active low Hsync; setting this bit to 1 indicates an active high Hsync. The power-on default value is 1.

0x12 Bit[3] Hsync output polarity

This bit sets the polarity of the Hsync output. Setting this bit to 0 will set the Hsync output to active low. Setting this bit to 1 sets the Hsync output to active high. The default setting is 1 at startup.

0x13 Bits[7:0] Hsync Duration

An 8-bit register that sets the duration of the Hsync output pulse. The leading edge of the Hsync output is triggered by an internally generated phase-adjusted PLL feedback clock. The AD9983A then counts the number of pixel clocks equal to the value in this register. This triggers the trailing edge of the Hsync output, which is also phase adjusted.

VSYNC control

0x14 bit[7] Vsync source rewrite

This is the active Vsync overlay. Setting this to 0 allows the chip to determine the active Vsync source, setting it to 1 uses Register 0x14, Bit 6 to determine the active Vsync source. The power-on default value is 0.

0x14 bit[6] Vsync source

This bit selects the Vsync source for synchronization processing only when Register 0x14, Bit 7 is set to 1. Setting bit 6 to 0 specifies Vsync from the input pin; setting it to 1 selects Vsync from the sync separator. The boot default value is 0.

0x14 Bit[5] Vsync Input Polarity Override

This bit sets whether the chip selects the Vsync input polarity or if it is specified. Setting this bit to 0 allows the chip to automatically select the polarity of the input Vsync. Setting this bit to 1 indicates that Bit 4 of Register 0x14 specifies the polarity. The boot default value is 0.

0x14 Bit[4] Vsync Input Polarity

If Bit 5 of Register 0x14 is 1, the value of this bit specifies the polarity of the input Vsync. Setting this bit to 0 indicates an active low Vsync; setting this bit to 1 indicates an active high Vsync. The power-on default value is 1.

0x14 Bit[3] Vsync output polarity

This bit sets the polarity of the Vsync output. Setting this bit to 0 will set the Vsync output to active low. Setting this bit to 1 will set the Vsync output to active high. The power-on default value is 1.

0x14 bit[2] Vsync filter enabled

This bit enables the Vsync filter to allow precise placement of Vsync relative to Hsync and facilitates correct operation of the Hsyncs/Vsync count.

0x14 Bit[1] Vsync Duration Enable

This will enable the Vsync duration block, which is designed to be used with the Vsync filter. Setting the bit to 0 will keep the Vsync output duration unchanged. Setting the bit to 1 will set the Vsync output duration based on Register 0x15. The power-on duration is 0.

0x15 Bits[7:0] Vsync Duration

It is used to set the output duration of Vsync and is designed to be used with Vsync filters. This option is only valid when Register 0x14, Bit 1 is set to 1. The boot default is 10 DDR.

Glide and Clamp Control

0x16 Bits[7:0] Precast

This register allows the internally generated coast signal to be applied before the Vsync signal. This is necessary in the presence of pre-equalization pulses. The step size of this control is one Hsync cycle. For pre-broadcasting to work properly, both the Vsync filter (0x14, Bit 2) and the Sync Processing filter (Register 0x20, Bit 1) must be enabled or disabled. The power-on default value is 00.

0x17 Bits[7:0] Postprocessing

This register allows the internally generated coast signal to be applied after the Vsync signal. This is necessary in the presence of post-equalization pulses. The step size of this control is one Hsync cycle. For postprocessing to work properly, both the Vsync filter (0x14, bit 2) and the sync processing filter (0x20, bit 1) must be enabled or disabled. The power-on default value is 00.

0x18 bit[7] coast source

This bit is used to select the active coast source. Choice of coast input pin or Vsync. If Vsync is selected, an additional decision is required to use the Vsync input pin or the output of the sync splitter (Register 0x14, Bits[7:6]).

0x18 Bit[6] Coasting Polarity Override

This register is used to override the internal circuitry that determines the polarity of the coast signal entering the PLL. The default setting is 0 at startup.

0x18 Bit[5] coast input polarity

When Register 0x18, Bit 6 = 1, this register sets the input coast polarity. The default setting is 1 at startup.

0x18 Bit[4] Clamp Source Select

This bit determines the source of the clamp timing. 0 enables the clamp timing circuit controlled by clamp and clamp duration. The clamping position and duration are calculated from the leading edge of Hsync. A 1 Enable external clamp input pin. When the clamp signal is activated, the three channels are clamped. The clamp polarity is determined by the clamp polarity. The default setting is 0 at startup.

0x18 Bit[3] Red Clamp Select

This bit determines whether the red channel is fixed to ground or to the midscale. The default setting is 0 at startup.

0x18 Bit[2] Green Clamp Select

This bit determines whether the green channel is fixed to ground or to the midscale. The default setting is 0 at startup.

0x18 Bit[1] Blue Clamp Select

This bit determines whether the blue channel is fixed to ground or to midscale. The default setting is 0 at startup.

0x19 Bits[7:0] Clamp

An 8-bit register that sets the position of an internally generated clamp. When EXTCLMP = 0 (Register 0x18, Bit 4), the clamp signal is generated at the position established by the clamp register (register 0x19) and for the duration set by the clamp duration register (register 0x1A). Start the clamp count of pixel cycles (register 0x19) after the trailing edge of Hsync. The clamp position can be programmed to any value between 1 and 255. Value 0 is not supported.

The clamp should be placed during the time period when the input signal exhibits a stable black level reference, usually the back porch cycle between Hsync and the picture. When EXTCLMP=1, this register is ignored. The power-up default setting is 8.

0x1A Bits[7:0] Clamp Duration

An 8-bit register that sets the duration of an internally generated clamp. When EXTCLMP = 0 (Register 0x18, Bit 4), the clamp signal is internally generated at the position established by the clamp register (and for the duration set by the clamp persistence register). Clamp starts the clamp placement count for pixel periods after the trailing edge of Hsync (register 0x19). The clamp duration can be programmed to any value between 1 and 255. Value 0 is not supported.

For best results, the clamp duration should be set to include most of the black reference signal time after the trailing edge of the Hsync signal. Insufficient clamping time produces brightness changes at the top of the screen and slow recovery from large changes in average picture level (APL) or brightness. When EXTCLMP=1, this register is ignored. Power-up defaults to 20 DDR.

0x1B Bit[7] Clamp Polarity Override

This bit is used to override the internal circuitry that determines the polarity of the clamp signal. The default setting is 0 at startup.

0x1B Bit[6] clamp input polarity

This bit indicates the polarity of the clamp signal only when Register 0x1B, Bit 7 = 1. The default setting is 1 at startup.

0x1B Bit[5] Auto Offset Enable

This bit selects between auto-offset mode and manual-offset mode (disables auto-offset) (see the Auto-offset Operation section). The default setting is 0 at startup.

0x1B Bits[4:3] Automatic offset update frequency

These bits control the update frequency of the auto-skew circuit (if enabled). It is recommended to update every 64 Hsyncs. The boot default setting is 11.

0x1B Bits[2:0]

011 must be written for proper operation.

SOG control

0x1D Bits[7:3] SOG slicer threshold

This register allows adjustment of the SOG slicer's comparator threshold. This register is adjusted in 8mV steps, with a minimum setting of 8mV and a maximum setting of 256mV. The power-on default setting is 15 DDR, which corresponds to a threshold of 128 mV.

0x1D Bit[2] Drain sex

This bit sets the polarity of the soak signal. The default setting is 0 at startup.

0x1D Bits[1:0] SOGOUT select

These register bits control the output on the SOGOUT pin. Options include raw SOG in the slicer (which is the unprocessed SOG signal generated by the sync slicer), raw Hsync, regenerated syncs in the sync filter that may generate lost syncs due to glide or exit, or finally are filtered syncs that exclude external syncs that do not occur in the sync filter window. The default setting is 0 at startup.

Input and Power Control

0x1E Bit[7] Channel Select Override

This bit provides an override for automatic input channel selection. The default setting is 0 at startup.

0x1E Bit[6] Channel Select

If Register 0x1E, Bit 7=1, this bit selects the active input channel. This will select between channel 0 data and sync or channel 1 data and sync. The default setting is 0 at startup.

0x1E Bit[5] Programmable Bandwidth

This bit selects between low or high input bandwidth. It is useful in limiting noise on low frequency inputs. The default setting is 1 at startup. Low analog input bandwidth is about 100 MHz; high analog input bandwidth is about 200 MHz.

0x1E Bit[4] Power-Down Control Select

This bit determines whether the power-down is controlled manually or automatically by the chip. If automatic control (Register 0x1E, Bit 4) is selected, the AD9983A decision is based on the state of the Sync Detect bits (Register 0x24, Bit 2, Bit 3, Bit 6, and Bit 7). If an Hsync or sync on green input is detected on any input, the chip will power up or down. For manual control, the AD9983A allows flexible control through dedicated pins and register bits. Dedicated pins allow a hardware watchdog circuit to control power-down, while register bits allow software-controlled power-down. When using manual power-down control, the polarity of the power-down pin must be set whether it is used or not (Register 0x1E, Bit 2). If not used, it is recommended to set the polarity to active high and hardwire the pin to ground with a 10 kΩ resistor.

0x1E Bit[3] power down

This bit is used to manually put the chip into power down mode. Only used when manual power down control is selected (see bit 4 above). Both the state of this register bit and the power down pin (pin 17) are used to control manual power down. (See the Power Management section for details on shutdown.)

0x1E Bit[2] Power down pin polarity

This bit defines the polarity of the power-down pin (pin 17). Only used when manual power-down control is selected (see 0x1E Bit[4] Power-down control selection).

0x1E Bit[1] Power-down fast switching control

This bit controls a special fast switching mode. Using this bit, the AD9983A can remain active during power down and only place the output in high impedance. This option is useful when the data outputs of two chips are connected to one PCB and the user wants to switch between the two chips on the fly.

0x1E Bit[0] Immersion High Impedance Control

When in power-down mode, this bit controls whether the permeate pin is in a high-impedance state. In most cases, the immersion liquid is not placed in a high impedance state during normal operation. Sync detection is usually required by the graphics controller. The options for placing the seepage trenches in high impedance consist primarily of allowing factory test mode.

output control

0x1F Bits[7:5] Output Mode

These bits select between three options for output mode. In 4:4:4 mode, RGB is standard. In 4:2:2 mode, YCbCr is standard, allowing the number of output pins to be reduced from 24 to 16. In 4:4:4ddr output mode, the data is in RGB mode but changes on every clock edge. The power-up default setting is 100.

0x1F Bit[4] Main output enable

This bit places the main output in active or high impedance mode. The default setting is 1 at startup.

0x1F Bit[3] Auxiliary output enable

This bit places the secondary output in active or high impedance mode.

Use 4:2:2 or 4:4:4 demethylation reductase. In these modes, the data on the blue output channel is the secondary output, and the output data on the red and green channels is the primary output. Auxiliary output is always DDR YCbCr data pattern. See the Output Formatter section and Table 12. The default setting is 0 at startup.

0x1F Bits[2:1] Output driver strength

These two bits select the drive strength for all high-speed digital outputs except the VSOUT, A0, and O/E fields. Higher drive strengths result in faster rise/fall times and generally easier data capture. Lower drive strength results in slower rise/fall times and helps reduce EMI and digitally generated power supply noise. The power-up default setting is 10.

0x1F Bit[0] Output Clock Inversion

This bit allows output clock inversion. The default setting is 0 at startup.

0x20 Bits[7:6] Output Clock Select

These bits allow selection of an optional output clock such as a fixed 40mhz clock, a 2× clock, a 90° phase-shifted clock, or a normal pixel clock. The power-up default setting is 00.

0x20 Bit[5] output high impedance

This bit places all outputs (except dip) into a high impedance state. The default setting is 0 at startup.

0x20 Bit[4] SOG High Impedance

This bit allows the permeate pin to be placed in high impedance mode. The default setting is 0 at startup.

0x20 Bit[3] Field Output Polarity

This bit sets the polarity of the magnetic field output bit. The default setting is 1 at startup.

Synchronous processing

0x20 Bit[2] Phase Locked Sync Filter

This bit selects the signal used by the PLL. It can choose between raw Hsync, SOG or filtered versions. Filtering of Hsync and SOG removes almost all external transitions that would normally cause PLL interruptions. The default setting is 0 at startup.

0x20 Bit[1] Synchronous processing input source

This bit selects whether the sync processor uses raw sync or regenerated sync to perform the following functions: coast, H/V count, field detection, and Vsync duration count. Regenerated sync is recommended.

0x21 Bits[7:0]

Must be set to default

0x22 bits[7:0]

Must be set to default

0x23 Bits[7:0] Sync filter window width

This 8-bit register sets the time window (in 25 ns steps) of the regenerated Hsync leading edge and allows the sync pulse to pass through. Therefore, with the default value of 10, the window width is ±250 ns. Its purpose is to set the window width so that extraneous pulses are excluded. (see the Synchronization section). As with the sync separator threshold, the 25ns multiplier value is somewhat variable. Maximum variability over all operating conditions is ±20% (20 ns to 30 ns).

Detection status

0x24 bit[7] HSYNC0 detection bit

This bit is used to indicate when activity is detected on the HSYNC0 input pin. If Hsync remains high or low, no activity will be detected. The synchronization processing block diagram shows where this functionality is implemented. 0=HSYNC0 is not active. 1=HSYNC0 is active.

0x24 bit[6] HSYNC1 detection bit

This bit is used to indicate when activity is detected on the HSYNC1 input pin. If Hsync remains high or low, no activity will be detected. The synchronization processing block diagram shows where this functionality is implemented. 0=HSYNC1 is not active. 1=HSYNC1 is active.

0x24 bit[5] VSYNC0 detection bit

This bit is used to indicate when activity is detected on the VSYNC0 input pin. If Vsync remains high or low, no activity is detected. The synchronization processing block diagram shows where this functionality is implemented. 0=VSYNC0 is not active. 1=VSYNC0 is active.

0x24 bit[4] VSYNC1 detection bit

This bit is used to indicate when activity is detected on the VSYNC1 input pin. If Vsync remains high or low, no activity is detected. The synchronization processing block diagram shows where this functionality is implemented. 0=VSYNC1 is not active. 1=VSYNC1 is active.

0x24 bit[3] SOGIN0 detection bit

This bit is used to indicate when activity is detected on the SOGIN0 input pin. If SOG remains high or low, no activity is detected. The synchronization processing block diagram shows where this functionality is implemented. 0=SOGIN0 is not active. 1=SOGIN0 is active.

0x24 bit[2] SOGIN1 detection bit

This bit is used to indicate when activity is detected on the SOGIN1 input pin. If SOG remains high or low, no activity is detected. The synchronization processing block diagram shows where this functionality is implemented. 0=SOGIN1 is not active. 1=SOGIN1 is active.

0x24 bit[1] coast detection bit

This bit detects activity on the EXTCK/COAST pin. It indicates that one of the two signals is active, but not which signal is active. No DC signal detected.

0x24 Bit[0] Clamp Detection Bit

This bit is used to indicate when activity is detected on the external clamping pin. If the outer clamp is held high or low, no activity will be detected.

polarity state

0x25 Bit[7] HSYNC0 Polarity

Indicates the polarity of the HSYNC0 input.

0x25 Bit[6] HSYNC1 Polarity

Indicates the polarity of the HSYNC1 input.

0x25 Bit[5] VSYNC0 Polarity

Indicates the polarity of the VSYNC0 input.

0x25 Bit[4] VSYNC1 Polarity

Indicates the polarity of the VSYNC1 input.

0x25 Bit[3] Glide Polarity

Indicates the polarity of the external taxi signal.

0x25 Bit[2] Clamp Polarity

Indicates the polarity of the clamp signal.

0x25 Bit[1] Don't care pulse detection

The second output of the Hsync filter, this status bit tells if there are extraneous pulses on the incoming sync signal. Typically, external pulses are used for copy protection, so this status bit can be used for that purpose.

sync count

0x26 Bits[7:0] Hsyncs/Vsync MSB

8 MSBs of a 12-bit counter that reports the number of hsync/Vsync on the active input. This is useful for determining patterns and helps set the PLL divide ratio.

0x27 bits[7:4] hsync/vsync lsb

4 lsb of 12-bit counter reporting the number of hsync/vsync on active input.

test register

0x28 Bits[7:0] Test Register 1

0xBF must be written for proper operation.

0x29 Bits[7:0] Test Register 2

0x00 must be written for proper operation.

0x2A Bits[7:0] Test Register 3

Read-only bit for future use.

0x2B Bits[7:0] Test Register 4

Read-only bit for future use.

0x2C Bits[7:5] Auto Offset Hold

0x00 must be written for proper operation.

0x2C Bit[4] Automatic offset hold

Bits that control whether the auto-offset function runs continuously or only once and saves the result. Continuous updates are recommended as this allows the AD9983A to compensate for drift over time and temperature. If one-time updates are preferred, they should be performed on every part power-up and mode change. To perform a one-time update, the first automatic offset must be enabled (Register 0x1B, Bit 5). Next, this bit (auto-offset hold) must first be set to 1 for the auto-offset function to run and set to the final value. Then, Auto Offset Hold should be set to 0 to maintain the offset value calculated by the automatic circuit. The maximum settling time of the AD9983A auto-bias circuit is 10 updates. For example, if the update frequency is set to every 64 Hsyncs, the maximum settling time will be 640 Hsyncs (10×64 Hsyncs).

0x2C Bits[3:0]

0x0 must be written for proper operation.

0x2D Bits[7:0] Test Register 5

Read/write bits for future use. 0xE8 must be written for proper operation.

0x2E Bits[7:0] Test Register 6

Read/write bits for future use. 0xE0 must be written for proper operation.

0x34 Bit[2] SOG filter enable

This bit enables the SOG filter, which will reject inputs less than 250ns wide. This facilitates the PLL's ability to ignore extraneous (invalid) sync pulses.

0x36 bit[0] VCO gear selection

This bit allows the VCO to select a lower "gear", allowing it to run a lower pixel clock while remaining within a more linear range.

0x3C Bits[7:4] Test bits

Must be set to 0x0 for proper operation.

0x3C Bit[3] Automatic gain matching hold

Bits that control whether the automatic gain matching function runs continuously or only once and saves the result. Continuous updating is recommended as it allows the AD9983A to compensate for drift over time and temperature. If one-time updates are preferred, they should be performed on every part power-up and mode change. For a one-time update, the first automatic gain match must be enabled (register Ox3C, bit 2). Next, this bit (Auto Gain Match Hold) must first be set to 1 for the Auto Gain Match function to run and settle to the final value. Then, the automatic gain matching hold bit should be set to 0 to hold the gain value calculated by the automatic circuit. The maximum settling time of the AD9983A automatic gain matching circuit is 10 updates. For example, if the update frequency is set to every 64 Hsyncs, the maximum resolution time will be 640 Hsyncs (10 x 64 Hsyncs).

0x3C Bits[2:0] Automatic gain matching enable

These bits enable or disable the automatic gain matching function. When set to 000, the automatic gain matching function is disabled; when set to 110, the automatic gain matching function is enabled.

PCB Layout Recommendations

The AD9983A is a high-precision, high-speed analog device. In order to maximize the performance of the part, it is important to have a well laid out board. The Analog Interface Inputs section provides guidelines for designing boards using the AD9983A.

Analog interface input

It is important to use the following layout techniques on graphical input:

• Minimize trace length into graphic input. This is achieved by placing the AD9983A as close as possible to the graphics VGA interface. Long input trace lengths are undesirable as they will pick up noise from the board and other external sources.

• Place the 75Ω termination resistor (see Figure 3) as close as possible to the AD9983A chip. Any extra track length between the termination resistor and the AD9983A input will increase the magnitude of the reflections, which can damage the graphic signal.

• Use 75Ω matched impedance traces. Tracking impedances other than 75Ω also increase the chance of reflections.

• The AD9983A has a very high input bandwidth (200 MHz). While this is desirable for obtaining high-resolution PC graphics signals with fast edges, it also means that it captures any high-frequency noise present. Therefore, it is important to reduce the noise coupled to the input. Avoid running any digital traces near analog inputs.

• Due to the high bandwidth of the AD9983A, low-pass filtering of the analog input is sometimes helpful in reducing noise. (For many applications, filtering is unnecessary.) Experiments have shown that a ferrite bead in series before the 75Ω termination resistor helps filter unwanted noise. Specifically, Fair Rite #2508051217Z0 was used, but the application works best with different bead values. Alternatively, it can be beneficial to place a 100Ω to 120Ω resistor between the 75Ω termination resistor and the input coupling capacitor.

power bypass

A 0.1µF capacitor is recommended to bypass each supply pin. The exception is when two or more power pins are next to each other. For these power/ground groupings, only one bypass capacitor is required. The basic idea is to have a bypass capacitor within 0.5cm of each power pin. Also, avoid placing capacitors on the other side of the AD9983A's PC board, as this will insert resistive vias in the path.

Bypass capacitors should be located between the power plane and the power pins. Current should flow from the power plane to the capacitors and power pins. Do not make power connections between capacitors and power pins. Placing vias under the capacitor pads, all the way to the power plane, is usually the best approach.

It is especially important to maintain low noise and good stability PVD (clock generator power). Sudden changes in PVD can lead to similar changes in sampling clock phase and frequency. This can be avoided by careful attention to conditioning, filtering and bypassing. It is best to provide a separate regulated power supply for each analog circuit group (VD and PVD).

Some graphics controllers use very different power levels when active (during active picture time) and idle (during horizontal and vertical sync). This results in a measurable change in the voltage supplied to the analog power regulator, which in turn produces a change in the regulated analog supply voltage. This can be mitigated by regulating the analog supply or at least the PVD from a different, cleaner supply (eg from a 12V supply).

It is also recommended to use a single ground plane for the entire board. Experience has shown time and time again that single-surface noise performance is equal or better. Using multiple ground planes can be detrimental because each individual ground plane is smaller and can result in long ground loops.

In some cases, the use of a separate ground plane is unavoidable. For these cases, it is recommended to place at least one ground plane under the AD9983A. The location of the split should be at the receiver of the digital output. In this case, it's more important to place components wisely, as the current loop will be longer (current takes the path of least resistance). An example of a current loop is the power plane of the AD9983A to the digital output trace to the digital data receiver to the digital ground plane to the analog ground plane.

phase locked loop

Place the PLL loop filter components as close as possible to the filter pins. Do not place any digital or other high frequency traces near these parts. Use a value with a tolerance of 10% or less suggested in the data sheet.

output (data and clock)

Minimize the trace length that the digital output must drive. Longer traces have higher capacitance and require more instantaneous current drive, which creates more internal digital noise. Shorter trajectories reduce the chance of reflections.

Adding a 50Ω to 200Ω series resistor suppresses reflections, reduces EMI, and reduces current spikes inside the AD9983A. If using a series resistor, place it as close as possible to the pins of the AD9983A, but try not to add vias or extra length to the output trace to bring the resistors closer together.

If possible, limit the capacitance driven by each digital output to less than 10 pF. This is easy to do, keep the trace short, and connect the output to only one device.

Loading the output with excessive capacitance increases current transients inside the AD9983A and creates more digital noise on its power supply.

digital input

The digital inputs on the AD9983A (HSYNC0, HSYNC1, VSYNC0, VSYNC1, SOGIN0, SOGIN1, SDA, SCL, and CLAMP) are designed for 3.3V signals, but 5.0V signals are allowed. Therefore, if 5.0V logic is used, no additional components need to be added.

Any noise entering the Hsync input tracking will add jitter to the system. Therefore, try to minimize the track length and do not run any digital or other high frequency tracks near it.

reference bypass

The AD9983A has three voltage references that must be bypassed for the input PGA to function properly. REFLO and REFHI are connected to each other through 10µF capacitors. Input PGA circuits use these references to ensure maximum stability. Place them as close as possible to the AD9983A pins. Keep the ground connection as short as possible.

Dimensions