feature

Wide Operating Temperature - Temperature Range -55°C to +85°C Smart Alphanumeric Display Automotive CMOS IC Built-in RAMASCII Decoder LED Driver Circuit 128 ASCII Character Sets 16 User-Definable Characters Programmable Functions Single Character Flashing Full Screen Flashing Multiple Level Dimming and Blanking Self-Test Clear Function Read/Write Capability Fully TTL Compatible HDSP-2131 /- 2133 /-2179 Available for Night Vision Lighting Applications Solder wave XY stackable

illustrate

HDSP-2131 (yellow), HDSP-2179 (orange), HDSP-2132 (high efficiency (red) and HDSP-2133 (green) are 8-digit, 5 x 7-dot matrix, alphanumeric displays. 5.0 mm (0.2 in.) ) high-order characters are packed in standard 7.64mm (0.30") 32-pin dip. Onboard CMOS integrated circuit capable of decoding 128 ASCII characters, they are permanently stored in ROM attached, 16 programmable symbols can be stored in-board memory. Seven brightness levels available Versatility to adjust display intensity and power consumption. The HDSP-213X is designed for standard microprocessor interface technology - Nix. Display and special via a bidirectional octet data bus. These features make the HDSP-213X ideal for applications - a hermetically sealed Yes, low power ones require an alphanumeric display.

Note:

1. All dimensions are in mm (inches).

2. Unless otherwise specified, the specified tolerance is ±0.30 mm (±0.015).

3. Only available for green and yellow devices.

4. Leads are copper alloys, impregnated with solder.

Absolute Maximum Ratings

Supply Voltage, V DD to Ground[1] -0.3 to 7.0 V

Operating voltage, V DD to ground [2] 5.5V

Input voltage, any pin to ground -0.3 to V DD+0.3 V

Free Air Operating Temperature Range T A -55°C to +85°C

Storage temperature, T S -55°C to +100°C

CMOS integrated circuit junction temperature TJ (IC) +150°C

Wave Solder Temperature, 1.59 mm (0.063 in) below body ...... 250°C for 3 seconds

ESD Protection @1.5 kΩ, 100 pF…………VZ=4 kV (per pin)

notes:

1. Maximum voltage without LED lighting.

2.20 points at full brightness at all locations.

Electrical Characteristics over Operating Temperature Range 4.5

notes:

1. V DD = 5.0 volts.

2. Maximum I DD occurs at -55°C.

3. Average IDD measured at full brightness. See Table 2 in the Control Words section for IDD at low brightness. Peak IDD = 28/15 x Average IDD (#)

Optical characteristics at 25°C[4]V DD=5.0 V, full brightness

Note:

4. Refers to the initial case temperature of the device before light measurement.

AC timing characteristics over temperature V DD = 4.5 to 5.5 V unless otherwise specified.

notes:

1. Worst case value occurs at an IC junction temperature of 150°C.

2. For designers who do not need to read from the display, the read line can be tied to V DD, and the write and chip enable lines can be tied together.

3. Changing the logic level of the address line when CE = "0" may cause incorrect data to be entered into the character RAM regardless of the logic level of the WR and RD lines.

4. Only after 3 clock pulses (using internal refresh clock, 110 microseconds minimum), after the reset line

AC timing characteristics over temperature V DD = 4.5 to 5.5 V unless otherwise specified.

Electrical Instructions

The pin function reset (RST, pin 5) resets the initialization display. FLASH (FL, pin 27) FL low indicates that FLASH RAM can be accessed and is not affected by address line states A 3-A 4. Each location in the address input memory has a different address. Address Inputs (A 0-A 2) (A 0-A 4, pins 28-32) select a specific row in Character RAM, Flash RAM, or UDC (User Defined Character) RAM. A 3-A 4 are used to select the memory area to be accessed. Table 1 shows the logic levels required to access each section of memory.

Clock Select This input is used to select the internal (CLS=1) or external (CLS=0) (CLS, pin 1) clock source. Clock Input/Output Output Master Clock (CLS=1) or Slave Clock (CLS=0) (CLK, pin 2) display. WRITE (WR, pin 3) data is low on the WR input and low on the CE input. Chip Enable (CE, pin 4) This input must be at logic low in order to read or write data to the display must reach a higher value between each read and write cycle. When the RD input is low and the CE input is too low. Data Bus (D 0-D 7, The data bus is used to read or write to the display. Pins 11-14, 19-22) Ground (Power) (Pin 17) This is the analog ground for the LED driver. GND (Logic) (Pin 18) This is the digital ground for the internal logic. V DD (Power) (Pin 16) This is the positive power input.

Show internal block diagram

Figure 1 shows a schematic display of the internal block HDSP-213X/-2179. The CMOS integrated circuit includes an 8-byte character RAM, an 8-bit flash memory, a 128-character ASCII decoder, a 16-character UDCRAM, a UDC address register, a control word register, and the circuits necessary to refresh the synchronous decoding and eight 5×7 dot matrix of driving characters. The accessible portion of the primary user display is shown below:

Character Ram Figure 2 shows the logic level needed to access the HDSP-213X Character RAM. = "0" and RD = "0" or WR = "0" during normal access. However, erroneous data may be written to the character RAM if the address line is unstable when CE = "0" regardless of the logic level of the RD or WR lines. Address lines A 0-A 2 are used to select the position in the character - tram. Two types of data can be stored in each character RAM location: ASCII code or UDCRAM address. Use data bit D 7 to distinguish between ASCII characters and UDC RAM addresses. D 7=0 enables ASCII decoder and D 7=1 enables UDC memory. D 0-D 6 are used to enter ASCII data and D 0-D 3 are used to enter UDC addresses.

UDC RAM and UDC Address Registers Figure 3 shows the logic level needed to access the UDC RAM and UDC address registers. The UDC address register is eight bits wide. The next four bits (D 0-D 3) are used to select one of the 16 UDC locations. This high bit (D 4-D 7) is not used. Once the UDC address is stored in the UDC address register, the UDC RAM can be accessed. It takes eight write cycles to fully specify a 5 x 7 character. A loop is used to store the UDC RAM address address register in the UDC. Seven cycles are used in the UDC memory. Data entry row. One cycle is required to access each row. Figure 4 shows that the UDC's organizational character assumes that the symbol for storage is an "F". Use 0-A 2 to select the row to be accessed D 0-D 4 is used to transfer row point data. The last three ignore bits (D 5-D 7). The number 0 (least significant bit) corresponds to the rightmost column of a 5 x 7 matrix and D 4 (most significant bit) corresponds to the leftmost column of a 5 x 7 matrix.

Flash memory Figure 5 shows the logic level needed to access the flash memory. Flash memory has a bit-and-character RAM associated with each location. Flash input is used to select flash ram. Address lines A3-A4 are ignored. Address lines A0-A2 are used to select flash memory attributes. D 0 is used to store or delete flash attributes. D 0="1" stores the attribute and D 0="0" removes the attribute. When the attribute is enabled, a "1" in the third bit of the control word is stored in the flash RAM, and the corresponding character will flash at a frequency of about 2 Hz. The real interest rate depends on the clock frequency. For an external clock the flash can be clocked by dividing by 28672.

Control Word Register Figure 6 shows how to access the Control Word Register. This is an eight-bit register that performs five functions. They are smart-ness control, Flash RAM control, flashing, self-checking and clearing. Each function is independent of the others. However, all bits are updated during each control word write cycle. Brightness (bits 0-2) Adjusts the brightness of the display for bits 0-2 of the control word. Interpreting bits 0-2 as a three-bit binary code Code (000) corresponds to maximum brightness and code (111) corresponds to a blank display. In addition to changing the display brightness, bits 0-2 change the average value of the IDD. Day can be calculated at any brightness multiplied by the percentage brightness level I DD at 100% brightness level. These IDD values are shown in Table 2

Flash Capability (Bit 3) Bit 3 determines whether the flashing character attribute is enabled or disabled. The output of the flash memory is selected when bit 3 is "1". If the location in the flash is "1" the relevant number will be at about 2 Hz. For an external clock, the flicker rate can be calculated by driving the clock to frequency 28672. If the enable bit of the flash control word is a "0", the contents of the flash RAM are ignored. See the Reset section for using this multi-display feature system. The blink function (bit 4) uses bit 4 of the control word to synchronize all eight digits of the blinking display. when? This bit is a "1" and the display will blink when all 8 bits are close - about 2 Hz. The actual rate is dependent on the clock frequency. For an external clock, the flicker ratio can be divided by the clock frequency as 28672. This function will override the flash function at startup. See the Reset section for this function with multiple display systems.

Self-test function (bits 5, 6) Bit 6 of the control word register is used to start the self-test function. The internal result of the self-test is stored in the control word. Bit 5 is a read-only bit, where bit 5 = "1" indicates that the self-test has passed, and bit 5 = "0" indicates that the self-check has failed. Setting bit 6 to logic 1 will start the self-test function. Built-in self-check function of the IC Two internal programs practice the main part of the IC and light up all the LEDs. The first routine loops the decoder ROM in all states of ASCII and outputs it. If the checksum agrees to use the correct value, set bit 5 to "1". The second program provides visual testing of LEDs using driver circuits. This is the pattern shown by writing the completed squares and inverse squares. Each display mode for approval - about 2 seconds. The monitor cannot be accessed during the self-test function. The time it takes for this self-executing test function to be multiplied by 262144 in clock cycles. For example, assuming a clock frequency of 58 kHz, then the time function frequency for performing the self-test is equal to (262144/58000) = 4.5 seconds duration. At the end of the self-test function, the character RAM is loaded with blanks, the control word register is set to zero except bit 5, and the flash memory is cleared and the UDC address register is set to all one.

Bit 7 of the clear function (bit 7) control word will clear the character RAM and flash memory. Setting bit 7 to '1' will initiate the clear function. Three clock cycles (using the internal refresh clock) are required to complete the clear function. The display cannot be displayed while the access is clearing. When the clear weather function has been completed, bit 7 will be reset to "0". The ASCII space character code (20H) will be loaded into the character so that the display and flash will be loaded with "0"s. UDC RAM, UDC address is registered, the rest of the control word is not affected. Display Reset Figure 7 shows the logic level required to reset the display. This monitor should reset-up on power up. External reset clears character RAM, flash RAM, control word and resets internal counters. After the rising edge of the reset signal, 3 clock cycles (using the internal refresh clock) are required to complete the reset sequence. The display cannot be displayed while the access is being reset. The ASCII character space code (20H) will blank the display for loading into character RAM. The flash control word register is loaded with all "0"s. The UDCRAM and UDC address registers are not affected. All displays operating from the same clock source must be reset at the same time to synchronize the blinking and blinking functions.

Electromechanical precautions

The HDSP-213X/-2179 are 32-pin 24-inch dual-in-line component external pins that can be stacked horizontally and vertically to create arrays of any size. The HDSP-213X/-2179 is designed for continuous operation from -55°C to +85°C with a maximum of 20 dots per character. Light source - all thirty-five points brightness is not recommended. The HDSP-213X/-2179 is through die attach and 280 LED chips and CMOS integrated circuits to a ceramic substrate. The glass window is placed on a ceramic substrate to form an air-gap wire mesh on the LED. Another glass of windows forms an air gap CMOS IC on it. This wrap construction makes the display highly resistant to temperature cycling and allows for wave soldering as well as visual inspection of integrated circuits.

The input of the CMOS integrated circuit is ESD-preventive input current blocking. How - For best results standard CMOS handling precautions should be used. HDSP-213X should be stored in antistatic packaging or conductive packaging material prior to use. During the assembly process, a grounded conductive work area should be used, and assemblers should wear conductive clothing and wrist straps. Synthetic materials for lab coats should be avoided as they are prone to static buildup. input when the CMOS input is subjected to a voltage below ground (V IN < ground) or a voltage above V DD (V IN > V DD) and when high current flows into the input. To prevent damage from input current-rent locks and electrostatic discharge, unused inputs should be grounded or grounded five. Voltage should not be applied to the input until V DD has been applied to the display. Transport - input voltage should be eliminated.

Thermal factor

The HDSP-213X/-2179 has been designed to provide low thermal-24 package pins from CMOS integrated circuits. This high temperature is usually free air through the user's printed circuit board. No additional cooling is required for most applications. The maximum operating IC junction temperature is 150°C. The maximum IC junction tem-temperature can be calculated using the following equation:

I DD MAX = 370 mA, 20 o'clock at eight character positions, ambient temperature 25°C. This value comes from electrical characteristics.

The ground connection provides two ground pins to maintain the internal IC logic ground. The designer can, when necessary, route the analog LED driver ground sep- from the logic base to the appropriate ground plane is available. Regarding long interconnects between the display and the host system, designers can preserve analog voltage drops from ground affecting the display by isolating for two reasons. The logical basis should be con-connected to the same ground-tial as the logical interface circuit. Analog ground and logic ground should be connected at a common point that can withstand the current introduced by the switching LED driver. When grounded alone - using ionic, the analog ground can vary from -0.3 V to +0.3 V with respect to the logic base. Voltages below -0.3 V will result in dots on top. Voltages above +0.3V will cause dimming and dot mismatch.

Electrostatic Discharge Susceptibility These displays have an ESD sus-Class 3 perception rating DOD-STD-1686 and a Class B MIL-STD-883C standard. Soldering and Post Solder Cleaning Instructions The HDSP-213X/-2179HDSP-213X/-2179 can be hand soldered or wave soldered using SN63 solder. When hand soldering an electronic temperature controller is recommended - use a soldering iron for traction and safety grounding. For best results, the iron tip temperature should be set at 315°C (600°F). For wave soldering, rosin-based RMA fluxes can be used. The solder wave temperature should be set at 245°C ± 5°C (473°F ± 9°F), and the standing wave should be set between 1 1/2 to 3 seconds for optimal soldering. The preheat temperature should not exceed 105°C (221°F) measured on the solder side of the PC board. For soldering and post-solder cleaning, see Application Note 1027, Soldering LED Components. Contrast Enhancement When used with the appropriate con-trast enhancement filter HCMS-213X/-2179 series displays are readable in daylight environments. Refer to Application Note 1029 Light and Dark Contrast and the Sun - Optical Readability of HDSP - 235X Series Alphanumeric Military Displays - Contrast Information Options for Daylight Enhanced Environments.

Reference application

Note 1015 Contrast Enhancement - The manufacturing technology of the LEDs shows information about the con - Moderately enhanced environment. Night Vision Lighting When used with the appropriate NVG/DV filters HDSP-2131, HDSP-2179 and HDSP-2133 can be used for night vision lighting applications. The HDSP-2131 (yellow), HDSP-2179 (orange) displays are used as master alarm ring markers. The HDSP-2133 (high green) display is for general instrumentation. For NVG/DV filters and a brief discussion of night vision lighting technology, refer to Application Note 1030 LED Displays and Indicators and Night Vision Imaging System Lighting. An external dimming circuit must be used to dim these displays to night vision lighting levels meeting NVIS radiation requirements. See 1039 Dimming HDSP-213X Monitor Night Vision Lighting Levels.