General Instructions

The AOZ1024D is a synchronous, high-efficiency, simple-to-use 4A buck regulator. The AOZ1024D operates from an input voltage range of 4.5V to 16V , provides up to 4A of continuous output current, and the output voltage is adjustable down to 0.8V.

The AOZ1024D is available in a DFN 5 x 4 package and is rated for an ambient temperature range of -40°C to +85°C.

Replacement part: AOZ1034DI

feature

4.5V to 16V operating input voltage range; synchronous rectification: 100mΩ internal high-side switch and 20mΩ internal low-side switch; high efficiency: up to 95%; internal soft-start; 1.5% initial output accuracy; output voltage adjustable to 0.8V; 4A continuous output current; fixed 500kHz PWM operation; cycle-by-cycle current limit; pre-bias start-up; short circuit protection; thermal shutdown; small form factor DFN 5 x 4 package.

application

Point-of-load DC/DC conversion; PCIe graphics cards; set-top boxes; DVD drives and hard drives; LCD panels; cable modems; telecom/networking/datacom equipment.

typical application

Ordering Information

All AOS products are packaged with lead-free plating and are RoHS compliant.

For more information, visit /web/quality/rohs_compliant.jsp.

Pin configuration

Pin Description

block diagram

Absolute Maximum Ratings

Exceeding absolute maximum ratings may damage the device.

Notes: 1. The device itself is ESD sensitive and requires handling precautions. Human body model grade: 1.5kΩ in series with 100pF.

Recommended Operating Ratings

Equipment is not guaranteed to exceed maximum operating ratings.

Note: 2.Θ values were measured with a 2oz. copper mounted device on a 1-in FR-4 board in still air at T=25°C. The value in any given application depends on the user's specific board design.

Typical performance characteristics

The circuit of Figure 1. T=25°C, V=V=12V, V=3.3V, unless otherwise specified.

efficiency

Thermal Derating Curve

DFN package parts for typical line and output voltage conditions. The circuit of Figure 1. 25°C ambient temperature and natural convection (wind speed <50LFM) unless otherwise specified.

Detailed description

The AOZ1024D is a current-mode buck regulator that integrates a high-side PMOS switch and a low-side NMOS switch. It operates over an input voltage range of 4.5V to 16V and provides up to 4A of load current. The duty cycle can be adjusted from 6% to 100%, allowing a wide range of output voltages. Features include enable control, power-on reset, input undervoltage lockout, output overvoltage protection, active high power good state, fixed internal soft-start, and thermal shutdown.

AOZ1024D is available in DFN 5x4 package.

Enable and Soft Start

The AOZ1024D has an internal soft-start function that limits the inrush current and ensures that the output voltage rises smoothly to the regulated voltage. The soft-start process begins when the input voltage rises to 4.1V and the voltage on the EN pin is high. During the soft-start process, the output voltage usually gradually changes to the regulated voltage within 4ms, and the 4ms soft-start time is set internally.

The EN pin of AOZ1024D is active high. Connect the EN pin to V if the enable function is not used. Pulling EN to ground will disable the AOZ1024D. Don't leave it open. The voltage on the EN pin must be higher than 2V to enable the AOZ1024D. When the voltage on the EN pin falls below 0.6V, the AOZ1024D will be disabled. If the application circuit requires that the AOZ1024D be disabled, an open rain or open collector circuit should be used to connect to the EN pin.

steady state operation

Under steady-state conditions, the converter operates in fixed frequency and continuous conduction mode (CCM).

The AOZ1024D integrates an internal P-MOSFET as a high-side switch. The inductor current is sensed by amplifying the voltage drop from the drain to the source of the high-side power MOSFET. The output voltage is divided down by an external voltage divider at the FB pin. The difference between the FB pin voltage and the reference voltage is amplified by an internal transconductance error amplifier. At the PWM comparator input, the error voltage displayed on the COMP pin is compared to the current signal that is the sum of the inductor current signal and the slope compensation signal. If the current signal is less than the error voltage, the internal high side switch is turned on. Inductor current flows from the input through the inductor to the output. When the current signal exceeds the error voltage, the high side switch is turned off. The inductor current is freewheeling to the output through the internal low-side N-MOSFET switch. Internal adaptive FET drivers ensure that the high-side and low-side switches do not overlap.

Compared to regulators using free-spinning Schottky diodes, the AOZ1024D uses a free-spinning NMOSFET for synchronous rectification. It greatly improves the efficiency of the converter and reduces the power loss of the low-voltage side switch tube.

The AOZ1024D uses a P-channel MOSFET as the high-side switch. It saves the boot trap capacitors typically seen in circuits using NMOS switches. Allows 100% turn-on of the high-side switch for linear regulation operation. The minimum voltage drop from V to V is the load current of the MOSFET x the DC resistance + the DC resistance of the buck inductor. Its calculation formula is as follows:

where; VO MAX is the maximum output voltage, VIN is the input voltage from 4.5V to 16V, IO is the output current from 0A to 2A, and RDS(ON) is the on-resistance of the internal MOSFET, depending on the input voltage and junction temperature.

On-off level

The AOZ1024D switching frequency is fixed and set by the internal oscillator. Due to device variations, the actual switching frequency can range from 350kHz to 600kHz.

Output voltage programming

The output voltage can be set by feeding the output back to the FB pin using a resistor divider network (see Figure 1). The resistor divider network consists of R and R. Typically, a design is started by picking a fixed value of R and calculating the required R with the following formula:

Table 1 lists some standard values of R and R for the most commonly used output voltage values.

The combination of R and R should be large enough to avoid drawing too much current from the output, which would result in power loss. 12

Since the switch duty cycle can be as high as 100%, the maximum output voltage can be set as high as the input voltage minus the voltage drop across the PMO and inductor.

Protection features

The AOZ1024D has various protection functions to prevent system circuit damage under abnormal conditions.

Over Current Protection (OCP)

The sensed inductor current signal is also used for overcurrent protection. Since the AOZ1024D uses pak current mode control, the COMP pin voltage is proportional to the peak inductor current. The COMP pin voltage is limited between 0.4V and 2.5V. The inductor current peak is automatically limited for d cycles.

When the output is shorted to ground under fault conditions, the inductor current decays very slowly during the switching cycle due to V=0V. To prevent catastrophic failure, a secondary current limit is designed inside the AOZ1024D. The measured inductor current is compared to a preset voltage representing the current limit, between 5.0A and 6.0A. When the output current is at the maximum current limit, the high side switch will be closed. Once the overcurrent condition is resolved, the drive will initiate a soft start. Type O

Power-On Reset (POR)

A power-on reset circuit monitors the input voltage. When the input voltage exceeds 4.1V, the inverter starts to work. When the input voltage drops below 3.7V, the inverter will shut down.

Thermal Protection

An internal temperature sensor monitors the connector temperature. When the junction temperature exceeds 150°C, the internal control circuit and the high-side PMOS are turned off. When the junction temperature drops to 100°C, the regulator will automatically restart under the control of the soft-start circuit.

application information

The basic AOZ1024 application circuit is shown in Figure 1. Component selection is described below.

input capacitor

The input capacitor must be connected to the V pin and PGND pin of the AOZ1024D to maintain a stable input voltage and filter out pulsed input current. The voltage rating of the input capacitor must be greater than the maximum input voltage plus the ripple voltage.

The input ripple voltage can be approximated by the following equation:

Since the input current of a buck converter is discontinuous, the current stress on the input capacitor is another consideration when choosing capacitors. For a buck circuit, the rms value of the input capacitor current can be calculated by the following formula:

If we let m equal the conversion ratio:

Calculate the relationship between the input capacitor rms current and voltage slew rate as shown in Figure 2 on the next page. It can be seen that the current stress of C is the largest when V is half of V. The worst current stress on C is 0.5x I.

For reliable operation and optimum performance, the input capacitor must have a current rating higher than I under worst-case operating conditions. Ceramic capacitors are the preferred input capacitors because of their low ESR and high current ratings. Other low ESR tantalum capacitors can also be used depending on the application circuit. When choosing ceramic capacitors, X5R or X7R type dielectric ceramic capacitors should be used for better temperature and voltage characteristics. Note that capacitor manufacturers' ripple current ratings are based on a certain lifetime. Actual designs may require further derating.

sensor

The inductor is used to provide a constant current output when it is driven by a switching voltage. For a given input and output voltage, the inductor and switching frequency together determine the inductor ripple current, which is:

The peak inductor current is:

High inductance provides low inductor ripple current, but requires larger size inductors to avoid saturation. Low ripple current reduces inductor core losses. It also reduces the rms current through the inductor and switch, thereby reducing conduction losses. Typically, the peak-to-peak ripple current on the inductor is designed to be 20-30% of the output current.

When choosing an inductor, make sure it can handle peak currents without saturation even at the highest operating temperature.

The inductor accepts the highest current in the buck circuit. Conduction losses on inductors need to be checked for compliance with thermal efficiency requirements.

Coilcraft, Elytone and Murata offer surface mount sensors in different shapes and styles. Shielded inductors are small in size and have less radiated EMI noise, but their cost is higher than that of unshielded inductors. The choice depends on EMI requirements, price and size.

output capacitor

Select the output capacitor based on the DC output voltage rating, output ripple voltage specification, and ripple current rating.

The selected output capacitor mu t has a higher voltage rating than the maximum desired output voltage including ripple. Long-term reliability needs to consider e-class.

The output ripple voltage specification is another important factor in selecting an output capacitor. In a buck converter circuit, the output ripple voltage is determined by the inductor value, switching frequency, output capacitor value, and ESR. It can be calculated by the formula bel w:

where CO is the output capacitor value and ESRCO is the equivalent series resistance of the output capacitor.

When using a low ESR ceramic capacitor as the output capacitor, the impedance of the capacitor at the switching frequency dominates. The output ripple is mainly caused by the capacitor value and the inductor ripple current. The output ripple voltage calculation can be simplified as:

When the ESR impedance at the switching frequency dominates, the output ripple voltage is primarily determined by the capacitor ESR and inductor ripple current. The output ripple voltage calculation can be further simplified as:

To reduce the output ripple voltage over the entire operating temperature range, X5R or X7R dielectric ceramic or other low ESR tantalum capacitors are recommended as output capacitors.

In a buck converter, the output capacitor current is continuous. The rms current of the output capacitor is determined by the peak-to-peak ripple current of the inductor. The calculation method is as follows:

Usually, the ripple current rating of the output capacitor is a lesser concern due to the low current stress. When the buck inductor is selected very small and the inductor ripple current is large, the output capacitor will be overstressed.

loop compensation

AOZ1024D adopts peak current mode control, which is easy to use and has fast transient response. Peak current mode control eliminates the bipolar effect of the output L&C filter. This greatly simplifies the design of the compensation loop.

With peak current mode control, the buck power stage can be simplified as a one-pole-one-zero system in the frequency domain. The pole is the dominant pole and can be calculated by the following formula:

due to output capacitance and ESR. Its calculation method is as follows:

where; CO is the output filter capacitor, RL is the load resistance value, and ESRCO is the equivalent s ri-s r resistance of the output capacitor.

The compensation design actually obtains the desired gain and phase by changing the transfer function of the converter control loop. Several different types of compensation networks can be used with the AOZ1024D. In most cases, a series capacitor and resistor network connected to the COMP pin sets the pole zero and is sufficient for a stable high bandwidth control loop.

In the AOZ1024D, the FB pin and the COMP pin are the inverting input and output of the internal error amplifier. Series R and C compensation networks connected to COMP provide a pole and a zero. The rods are:

where; GEA is the error amplifier transconductance, which is 200 x 10-6 A/V, GVEA is the voltage gain of the error amplifier, which is 500v/V, and C2 is the compensation capacitor in Figure 1.

The zero given by the external compensation network, capacitor C2 and resistor R3 is located at:

In order to design the compensation circuit, the target crossover frequency f must be chosen as the closed loop. The system crossover frequency is where the control loop has unity gain. Crossover is also known as converter bandwidth. Higher bandwidth means faster load response. However, considering the stability of the system, the bandwidth should not be too high. When designing the compensation loop, the stability of the converter under all line and load conditions must be considered.

In general, it is recommended to set the bandwidth equal to or less than 1/10 of the switching frequency. The AOZ1024D operates in the frequency range from 350kHz to 600kHz. It is recommended to choose a crossover frequency less than or equal to 40kHz.

The strategy for choosing R and CC is to use R to set the crossover frequency and C to set the compensator zero. Calculate R3 with the chosen crossover frequency f:

where; fC is the desired crossover frequency. For best performance, fC is set to be around 1/10 of the switching frequency; VFB is 0.8V, GEA is the transconductance of the error amplifier, which is 200×10-6a/V, and GCS is the transconductance of the current sensing circuit, is 6.68a/V.

Compensation capacitor CC and resistor RC return to zero. This zero is placed close to the gate f, but below 1/5 of the selected crossover frequency. C can be selected by:

The previous equation can also be simplified to:

An easy-to-use application software to aid in designing and simulating compensation loops can be found on .

Thermal Management and Layout Considerations

In the AOZ1024D buck regulator circuit, high pulse current flows through two circuit loops. The first loop starts with the input capacitor, V pin, LX pin, filter inductor, output capacitor, and load, and returns to the input capacitor through ground. When the high-side switch is turned on, current flows in the first loop. The second loop starts from the inductor, to the output capacitor and load, to the low-side NMOSFET. When the low-side NMOSFET is turned on, current flows in the second loop.

In the PCB layout, minimizing the area of the two loops can reduce the noise of the circuit and improve the efficiency. It is strongly recommended to use a ground plane to connect the input capacitors, output capacitors and PGND pins of the AOZ1024D.

In the AOZ1024D buck regulator circuit, the ajor power dissipation components are the AOZ1024D and the output inductor. The total power consumption of the converter circuit can be measured as input power - output power.

The power dissipation of the inductor can be approximated by the output current of the inductor and the DCR.

The actual junction temperature can be calculated from the power dissipation in the AOZ1024D and the thermal impedance from the junction to ambient.

The maximum junction temperature of the AOZ1024D is 150°C, which limits the maximum load current capability. See the thermal derating curve for the maximum load current of AOZ1024D at different ambient temperatures.

The thermal performance of the AOZ1024D is greatly affected by the PCB layout. During the design process, the user should take extra care to ensure that the integrated circuit operates under the recommended environmental conditions.

AOZ1024D is a standard FN5*4 package. For optimum electrical and thermal performance, some layout tips are listed below. Figure 3 on the next page shows an example PCB layout for the AOZ1024D.

1. The LX pin is connected to the internal PFET and NFET drains. They are the low resistance thermal conduction paths and the noisiest switching nodes. Connect a large copper plane to the LX pin to help dissipate heat. For full load (4A) applications, the LX pads can also be connected to the bottom layer via thermal vias for enhanced thermal dissipation.

2. Do not use thermal connections for V and PGND pins. Pour the largest copper area into the PGND pin and VIN pin to help with heat dissipation.

3. The input capacitor should be placed as close as possible to the V pin and the PGND pin.

4, the preferred ground plane. If a ground plane is not used, separate PGND from AGND and connect them at only one point to avoid PGND pin noise coupling to the AGND pin.

5. Keep the current trace from the LX pin to L to C to PGND as short as possible.

6. Pour copper planes on all unused board areas and connect them to stable DC nodes such as V, GND, or V.

7. Keep sensitive signal traces away from the LX pin.

Package size, DFN 5x4

notes:

1. Dimensions and tolerances are in accordance with ASME Y14.5M-1994.

2. All dimensions are in millimeters.

3. Terminal #1 identifier location and terminal numbering conventions are in accordance with JEDEC Publication 95 SP-002.

4. Dimension b applies to metallized terminals and is measured between 0.15mm and 0.30mm from the tip of the terminal. If the other end of the terminal has an optional radius, dimension b shall not be measured within that radius.

5. Coplanarity applies to terminals and all other backside metallizations.

6. Drawings shown are for illustration only.

Tape size, DFN 5x4

This data sheet contains preliminary data; supplemental data may be published at a later date.

Alpha and Omega Semiconductors reserve the right to make changes at any time without notice.

life insurance policy

Alpha and Omega Semiconductor products are not authorized for use as critical components in life support devices or systems.

As used in this article:

1. A life support device or system means: (a) a device or system intended for surgical implantation in the body, or (b) intended to support or sustain life, and (c) when properly used in accordance with the instructions for use provided on the label , a device or system that does not function properly and can reasonably be expected to cause significant injury to the user.

2. A critical component of any part of a life-saving appliance, device or system, the failure of which can reasonably be expected to cause the failure of the life-saving appliance or system, or to affect its safety or effectiveness.