Atmel Micropower ATmega48PA/88PA/168PA is a low power CMOS 8-bit microcontroller based on AVR enhanced RISC structure. By executing powerful instructions in one clock cycle, the throughput of the ATmega48PA/88PA/168PA approaches 1MIPS/MHz. This enables system designers to optimize the device based on power consumption and processing speed.

feature

High-Performance Low-Power AtmelAVR 8-Bit Microcontroller Family:

(1), advanced RISC architecture:

–131 powerful commands

– Mostly single clock cycle execution

–32 x 8 general purpose working registers

– Fully static operation

– Up to 20 MIPS throughput at 20MHz

– On-chip 2-cycle multiplier

(2), high-persistence non-volatile memory segment:

–4K/8K/16KBytes in-system self-programming flash memory

–256/512/512 bytes EEPROM

–512/1K/1K bytes internal SRAM

– Write/Erase Cycles: 10000 Flash / 100000 EEPROM

– Data retention: 20 years at 85°C / 100 years at 25°C

– Optional boot code section with independent lock bits

(3) In-system programming through the on-chip bootloader;

(4), real read and write operations: – software security programming lock

(5), Atmel QTouch library support:

– Capacitive touch buttons, sliders and wheels

– QTouch and QMatrix acquisition

– Up to 64 sense channels

1. Peripheral functions:

– Two 8-bit timer/counters with separate prescaler and compare modes

– One 16-bit timer/counter with separate prescaler, compare mode and capture mode

– Real-time counter with independent oscillator

– Six PWM channels

– 8-channel 10-bit ADC in TQFP and QFN/MLF packages

2. Temperature measurement: – 6-channel 10-bit ADC in PDIP package

3. Temperature measurement:

– Two master/slave SPI serial interfaces

– A programmable serial USART

– Single-byte 2-wire serial interface (compatible with Philips ICs)

– Programmable watchdog timer with separate on-chip oscillator

– An on-chip analog comparator

– Interrupt and wake up when changing pins

4. Special microcontroller functions:

– Power-on reset and programmable browning detection

– Internally calibrated oscillator

– External and internal interrupt sources

– Six sleep modes: idle, ADC noise reduction, power saving, power down, standby and extended standby

5. I/O and packages:

– 23 programmable I/O lines

– 28-pin PDIP, 32-pin TQFP, 28-chip QFN/MLF and 32-chip QFN/MLF

6. Working voltage: –1.8-5.5V

7. Temperature range: -40°C to 105°C

8. Speed class:

–0-4MHz@1.8-5.5V

– 0-10MHz @ 2.7-5.5V

– 0-20 MHz at 4.5-5.5 volts

9. Power consumption at 1MHz, 1.8V, 25°C:

– Active mode: 0.2mA

– Power down mode: 0.1 μA

– Power save mode: 0.75µA (with 32kHz RTC)

illustrate

The Atmel AVR core combines a rich instruction set with 32 general-purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing access to two independent registers in a single instruction executed in one clock cycle. The resulting architecture achieves up to 10 times the throughput while being more code efficient than conventional CISC microcontrollers.

ATmega48PA/88PA/168PA has the following features: 4K/8K/16Kbytes in-system programmable read/write flash memory, 256/512/512bytes EEPROM, 512/1K/1Kbytes SRAM, 23 general-purpose I/O lines, 32 general-purpose working registers , Real Time Counter (RTC), three flexible timer/counters with compare mode and PWM, 1 serial programmable application, 1 byte-oriented 2-wire serial interface (I2C), one 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable watchdog timer with internal oscillator, an SPI serial port, and 6 software-selectable power-saving modes. Idle mode stops the CPU while allowing the SRAM, timers/counters, SPI ports and interrupt system to continue working. Power-down mode preserves register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In power saving mode, the asynchronous timer continues to run, allowing the user to maintain the timer base while the rest of the device is asleep. The ADC noise reduction mode stops the CPU and all I/O blocks except the asynchronous timer and ADC to minimize switching noise during ADC conversions. In standby mode, the crystal/resonator oscillator runs while the rest of the device sleeps. This allows very fast startup combined with low power consumption. In Extended Standby mode, the main oscillator and asynchronous timer continue to run.

Atmel provides the QTouch library for embedding capacitive touch button, slider and wheel functionality into AVR microcontrollers. Patented charge transfer signal acquisition provides robust sensing capabilities including fully denoised reporting of touch keys, and Adjacent Key Suppression (AKS) technology for unambiguous detection of critical events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.

The device is fabricated using Atmel's high-density non-volatile memory technology. On-chip ISP flash allows program memory to be reprogrammed in-system via the SPI serial interface, traditional non-volatile memory programmers, or an on-chip bootloader running on the AVR core. The launcher can use any interface to download the application into the application flash. When the application flash section is updated, the software in the boot flash section will continue to run, providing true read and write operations. The Atmel ATmega48PA/88PA/168PA is a powerful microcontroller that combines an 8-bit RISC CPU with in-system self-programmable flash memory on a single chip, providing a high degree of flexibility and cost-effectiveness for many embedded control applications Efficient solution.

ATmega48PA/88PA/168PA supports a full set of program and system development tools, including: C compiler, macro assembler, program debugger/simulator, circuit emulator and evaluation kit.

Configuration summary

The ATmega88PA and ATmega168PA support a true read-write self-programming mechanism. There is a separate bootloader section and SPM instructions can only be executed from there. In the ATmega48PA, there is no read and write support, and there is no separate bootloader section. SPM instructions can be executed from the entire Flash.

block diagram

Pin configuration

Pin Description

1.1.VCC

Digital supply voltage.

1.2. Grounding

ground.

1.3. Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2

Port B is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffer has symmetrical drive characteristics with high sink and source capacity. As an input, an externally pulled Port B pin will generate current if the pull-up resistor is activated. When a reset condition is active, the Port B pins are tri-stated even if the clock is not running.

Depending on the clock select fuse setting, PB6 can be used as input to the inverse oscillator amplifier and input to the internal clock operating circuit.

Depending on the clock select fuse setting, PB7 can be used as the output of an inverting oscillator amplifier.

If the internal calibrated RC oscillator is used as the chip clock source, then PB[7:6] are used as TOSC[2:1] inputs for asynchronous timer/counter 2 if the AS2 bit in ASSR is set.

1.4. Port C (PC[5:0])

Port C is a 7-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The PC[5:0] output buffers have symmetrical drive characteristics with high sink and source capacities. As an input, an externally pulled low Port C pin will generate current if the pull-up resistor is activated. When a reset condition is active, the Port C pins are tri-stated even if the clock is not running.

1.5.PC6/Reset

PC6 is used as an I/O pin if the RSTDISBL fuse is programmed. Note that the electrical characteristics of PC6 are different from the other pins of Port C.

If the RSTDISBL fuse is not programmed, PC6 is used as a reset input. A low level on this pin exceeding the minimum pulse length will generate a reset even if the clock is not running. Short pulses are not guaranteed to generate a reset.

The various features of the C port are described in the alternative functions of the C port section.

1.6. Port D (PD[7:0])

Port D is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffer has symmetrical drive characteristics with high sink and source capacity. As an input, an externally pulled Port D pin will generate current when the pull-up resistor is activated. When a reset condition is active, the Port D pin is tri-stated even if the clock is not running.

1.7. AVCC

AV is the supply voltage pin for A/D converter PC[3:0] and PE[3:2]. Even if the ADC is not used, it should be connected externally to V. If an ADC is used, it should be connected to V through a low pass filter. Note that PC[6:4] uses the digital supply voltage V. Cocos IslandsCocos IslandsCocos IslandsCocos Islands

1.8.AREF

AREF is the analog reference pin for the A/D converter.

1.9. ADC[7:6] (TQFP and VFQFN packages only)

In the TQFP and VFQFN packages, ADC[7:6] is used as the analog input to the A/D converter. These pins are powered by the analog supply and function as 10-bit ADC channels.

I/O multiplexing

By default, each pin is controlled by the port as a general-purpose I/O, or it can be assigned to a peripheral function.

The following table describes the peripheral signals multiplexed to the port I/O pins.

resource

A complete set of development tools, application notes and data sheets can be downloaded at /avr.

data retention

Reliability qualification results show that at 85°C, the expected data retention failure rate is well less than 1 ppm over 20 years.

About code samples

This document contains simple code samples that briefly explain how to use the various parts of the device. These code examples assume that part-specific header files are included before compilation. Note that not all C compiler vendors include bit definitions in header files, and interrupt handling in C is compiler dependent. Check with the C compiler documentation for details.

For I/O registers located in the extended I/O map, the "input", "output", "SBI", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Usually "LDS" and "STS" are combined with "SBR", "SBRC", "SBR" and "CBR".

capacitive touch sensing

1. QTouch library

The Atmel QTouch library provides an easy-to-use solution to implement a touch-sensitive interface on most Atmel AVR microcontrollers. The QTouch library includes support for the Atmel QTouch and Atmel QMatrix acquisition methods.

Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for AVR microcontrollers. This is done by using a simple set of APIs to define touch channels and sensors, and then calling the touch-sensing API to retrieve channel information and determine the state of the touch sensor.

The QTouch library is free and can be downloaded from the Atmel website at /technologies/touch/. For implementation details and other information, see the Atmel QTouch Library User Guide - also available for download from the Atmel website.

Packaging Information

32-pin 32A

32-pin 32M1-A

32-pin 32CC1

28-pin 28M1

28-pin 28P3