feature

High-resolution analog-to-digital converter; 24-bit no missing code; ±0.0015% nonlinearity; optimized for fast channel switching; 18-bit pp resolution at 500hz (21-bit valid) 16-bit pp resolution at 2khz (19-bit valid) 14-bit pp resolution at 15khz (18-bit valid) on-chip system calibration per channel; 2 fully differential analog inputs; input ranges +5 V, ±5 V, +10 V, ±10 V; overvoltage tolerance; Up to ±16.5 V without affecting adjacent channels, maximum absolute voltage up to ±50 V; three-wire serial interface; soy protein isolate 8482 ;, QSPI™, Microwire™, and DSP-compatible logic input Schmi Special Trigger; Single Supply Operation; 5V Analog Supply; 3V or 5V Digital Supply; Package: 28 lead TSSOP.

application

Programmable logic controllers/distributed control systems; multiplexing applications; process control; industrial instrumentation.

General Instructions

The AD7732 is a high precision, high throughput analog front end. True 16-bit pp resolution is achievable with a total conversion time of 500 microseconds (2 kHz channel switching), making it ideal for high-resolution multiplexing applications.

The part is configurable via a simple digital interface that allows the user to balance noise performance with data throughput up to 15.4khz.

The analog front end features two fully differential input channels with a unipolar or true bipolar input range of ±10 V, while operating from a single +5 V analog supply. The part features overrange and overrange detection capabilities and accepts analog input overvoltages of ±16.5 V without degrading adjacent channel performance.

Differential reference inputs have "no reference" detection capability. The ADC also supports per-channel system calibration options. The digital serial interface can be configured for 3-wire operation and is compatible with microcontrollers and digital signal processors. All interface inputs are Schmitt-triggered.

The part is specified for operation over the extended industrial temperature range of -40°C to +105°C.

The other parts of the AD7732 family are the AD7734 and AD7738.

The AD7734 is similar to the AD7732, but its analog front end has four single-ended input channels.

The AD7738 analog front end can be configured as four fully differential or eight single-ended input channels, features a 0.625 V to 2.5 V bipolar/unipolar input range, and accepts common-mode input voltages from 200 mV to AVDD – 300 mV. The AD7738 multiplexer output is fixed externally, allowing the user to implement programmable gain or signal conditioning prior to application to the ADC.

Typical performance characteristics

Output Noise and Resolution Specifications

The AD7732 can operate with chopping enabled or disabled, allowing the ADC to be programmed to optimize throughput rate and channel switching time or optimize offset drift performance. Listed below are noise tables for the two main operating modes used to select the output rate and settling time.

The AD7732 noise performance depends on the selected chop mode, filter word (FW) value, and selected analog input range. AD7732 noise does not vary significantly with MCLK frequency.

Chopping enabled

The first mode, where the AD7732 is configured with chopping enabled (chopping=1), provides very low noise reduction yield. Tables 4 to 6 show -3db frequency and typical performance versus channel transition time and equivalent output data rate, respectively. Typical output rms noise is shown. Table 5 shows typical effective resolutions based on rms noise. Table 6 shows typical output peak-to-peak resolution, representing values that do not experience code flicker within the 6-sigma limit. Peak-to-peak resolution is not calculated based on rms noise, but rather based on peak-to-peak noise.

These typical numbers are generated from 4096 data samples collected in continuous conversion mode with the analog input voltage set to 0V and MCLK=6.144MHz. The conversion time is selected by the channel conversion time register.

cutoff disabled

In the second mode, the AD7732 is configured with chopping disabled (chopping = 0), providing faster conversion times while maintaining high resolution. Tables 7 to 9 show -3db frequency and typical performance versus channel transition time and equivalent output data rate, respectively. Table 7 shows typical output rms noise. Table 8 shows typical effective resolutions based on rms noise. Table 9 shows typical output peak-to-peak resolution, representing values that do not experience code flicker within the 6-sigma limit. Peak-to-peak resolution is not calculated based on rms noise, but rather based on peak-to-peak noise.

These typical numbers are generated from 4096 data samples collected in continuous conversion mode with the analog input voltage set to 0V and MCLK=6.144MHz. The conversion time is selected by the channel conversion time register.

Register to visit

The AD7732 is configurable through a series of registers. Some of these configure and control general AD7732 functions, while others are specific to each channel. The register data width varies from 8 bits to 24 bits. All registers are accessed through communication registers, that is, any communication with the AD7732 must begin with a write to the communication register and specify which register will be read or written subsequently.

communication register

8-bit, write-only register, address 00h

All communications with the part must begin with a write to the communications register. The data communication register that is written determines whether the subsequent operation is a read or a write, and which register this operation will point to. The digital interface by default expects a write to the communications register after power-up, after reset, or after a subsequent read or write to the selected register is complete. If the interface sequence is lost, the part can be reset by writing at least 32 serial clock cycles with DIN high and CS low. (Note that in this case, all parts, including modulators, filters, interfaces, and all registers are reset.) Use dump bits and "24/16" bits in continuous read mode or in the mode register bank Remember to keep data low when reading 32 or more bits.

I/O port registers

8-bit, read/write register, address 01h, default value 30h + digital input value × 40h.

The bits in this register are used to configure and access the digital I/O ports on the AD7732.

Amendment register

8-bit, read-only register, address 02h, default value 04h + chip version × 10h.

test register

24-bit, read/write register, address 03h.

This register is used to test parts in the manufacturing process. The user must not change the default configuration of this register.

ADC Status Register

8-bit, read-only register, address 04h, default 00h.

In conversion mode, the register bits reflect the state of a single channel. When the conversion is complete, the corresponding channel data register is updated and the corresponding RDY bit is set to 1. When the channel data register is read, the corresponding bit is reset to 0. When no read operation occurs and the result of the next conversion is updated to the channel data register, the bit is also reset to 0. Writing to the mode register resets all bits to 0.

In calibration mode, all register bits are reset to 0 when calibration is in progress; all register bits are set to 1 when calibration is complete.

The RDY pin output is related to the contents of the ADC Status Register as defined by the RDYFN bits in the I/O Port Register.

The RDY0 bit corresponds to differential input 0, and the RDY1 bit corresponds to differential input 1.

checksum register

16-bit, read/write register, address 05h.

This register is described in the Using the AD7732/AD7734/AD7738 Checksum Register Application Note (/UploadedFiles/application_Notes/71751876 AN626_0.pdf).

ADC Zero Scale Calibration Register

24-bit, read/write register, address 06h, default 800000h.

The registers hold the ADC zero-scale calibration coefficients. The value in this register is used in conjunction with the value in the ADC full-scale calibration register and the corresponding channel zero-scale and channel full-scale calibration registers to digitally scale the conversion results for all channels. The value in this register is automatically updated after the ADC zero-scale self-calibration is performed. This register can only be written to in idle mode (see the Calibration section for details).

ADC full scale register

24-bit, read/write register, address 07h, default 800000h.

This register holds the ADC full-scale coefficients. Users are advised not to change the default configuration of this register.

channel data register

16-bit/24-bit, read-only register, address 08h, 0Ah, default width 16 bits, default value 8000h.

These registers contain the most recent conversion results for each analog input channel. 16-bit or 24-bit data width can be configured by setting 16-bit/24-bit in the mode register. When the result is updated, the associated RDY bit in the channel status register goes high. The RDY bit will return low after a data register read begins. The RDY pin can be configured to indicate when any channel has unread data, or to wait for all enabled channels to have unread data. If any channel data register reads are in progress while the new result is being updated, the data registers will not be updated. This avoids data corruption. Reading the status register can be associated with reading the data register in dump mode. Reading the status register is always associated with reading the data register in continuous read mode (see the Digital Interface Description section for details).

Channel Zero Scale Calibration Register

24-bit, read/write register, address 10h, 12h, default 800,000 hours.

These registers hold specific channel zero-scale calibration coefficients. The values in these registers are used in conjunction with the values in the corresponding channel full-scale calibration register, ADC zero-scale calibration register, and ADC full-scale register to digitally scale conversion results for a specific channel. The value in this register is automatically updated after performing a channel zero-scale system calibration.

The format of the channel zero-scale calibration register is a signed bit and a 22-bit unsigned value. This register can only be written to in idle mode (see the Calibration section for details).

Channel Full-Scale Calibration Register

24-bit, read/write register, address 18h, 1Ah, default 200000 hours.

These registers hold specific channel full-scale calibration coefficients. The values in these registers are used in conjunction with the values in the corresponding channel zero-scale calibration register, ADC zero-scale calibration register, and ADC full-scale register to digitally scale the conversion results for a specific channel. The value in this register is automatically updated after a channel full-scale system calibration is performed. This register can only be written to in idle mode (see the Calibration section for details).

channel status register

8-bit, read-only register, address 20h, 22h, default value 20h × channel number.

These registers contain individual channel status information and some general AD7732 status information. Reading the status register can be associated with reading the data register in dump mode. Reading the status register is always associated with reading the data register in continuous read mode (see the Digital Interface Description section for details).

Channel Setup Register

8-bit, read/write register, address 28h, 2Ah, default 00h.

These registers are used to configure the selected channel, configure its input voltage range, and set the corresponding channel status register.

Channel Switch Time Register

8-bit, read/write register, address 30h, 32h, default 91h.

The transition time registers enable or disable chopping and configure digital filters for specific channels. This register value affects the conversion time, frequency response, and noise performance of the ADC.

mode register

8-bit, read/write register, address 38h, 3Ah, default 00h.

The mode register configures the part and determines its operating mode. Writing to the mode register clears the ADC status register, sets the RDY pin to logic high, exits all current operations, and initiates the mode specified by the mode bits.

The AD7732 contains only one mode register. Bit 1 of the address is used to write to the mode register to specify the channel selected for the operation determined by the MD2 to MD0 bits. The mode register can only be read using address 38h.

Digital Interface Description

hardware

The AD7732 serial interface can be connected to a host device through the serial interface in several different ways. The CS pin can be used to select the AD7732 as one of several circuits connected to the host serial interface. When CS is high, the AD7732 ignores the SCLK and DIN signals and the DOUT pin enters a high impedance state. When not using the CS signal, connect the CS pin to DGND.

The RDY pin can be polled for high and low transitions, or the host device interrupt input can be driven to indicate that the AD7732 has completed the selected operation and/or that new data from the AD7732 is available. The host system can also wait a specified amount of time after a given command writes to the device before proceeding with a read. Alternatively, the AD7732 status can be polled. When the RDY pin is not used in the system, it should be left open. (Note that the RDY pin is always an active digital output, i.e. it never goes into a high impedance state.)

The reset pin can be used to reset the AD7732. When not in use, connect this pin to the DVD.

The AD7732 interface can be simplified to two lines, connecting the DIN and DOUT pins to one bidirectional data line. The second signal in this 2-wire configuration is the SCLK signal. The host system should change the data line direction by referring to the AD7732 timing specification (see the bus abandon times in Table 2). In a 2-wire serial interface configuration, the AD7732 cannot operate in continuous read mode.

All digital interface inputs are Schmitt-triggered; therefore, the AD7732 interface is more noise immune and can be easily isolated from the host system via optocouplers. Figure 13, Figure 14, and Figure 15 outline some possible host device interfaces: SPI (Figure 13) without the CS signal, DSP interface (Figure 14), and a 2-wire configuration (Figure 15).

reset

The AD7732 can be reset through the reset pin or by writing a reset sequence to the AD7732 serial interface.

The reset sequence is N×0+32×1, which can be the data sequence 00h+FFh+FFh+FFh+FFh+FFh in the byte-oriented interface. The AD7732 also has a power-on reset function with a trip point of 2V and a defined default state after power-up.

It is the responsibility of the system designer to prevent unnecessary writes to the AD7732. Unwanted writes can occur when a spurious clock is present on SCLK while the CS pin is low. It is important to note that at system power-up, if the AD7732 interface signals are floating or undefined, the part may inadvertently be configured to an unknown state. This can be easily resolved by initiating a hardware reset event or a reset sequence of 32 as the first step in system configuration.

Access AD7732 registers

All communication with the part begins with a write to the communication register, followed by a read or write of the address register.

In a simultaneous read and write interface (such as SPI), write 0 to the AD7732 when reading data.

Figure 16 shows the AD7732 interface read sequence for the ADC status register.

Convert and read data in a single pass

When writing to the mode register, the ADC status byte is cleared and the RDY pin goes high, regardless of its previous state. When a single conversion command is written to the mode register, the ADC initiates a conversion on the channel selected by the address of the mode register. After the conversion is complete, update the data register, change the mode register to idle mode, set the relevant RDY bit, and the RDY pin goes low. When the associated channel data register is read, the RDY bit is reset and the RDY pin returns high.

Figure 17 shows the digital interface signal performing a single conversion on channel 0, waiting for the RDY pin to go low, and reading the channel 0 data register.

dump mode

When the dump bit in the mode register is set to 1, the channel status register will be read immediately by a read of the channel data register, regardless of whether the status or data register has been addressed by the communication register. When reading 24-bit data in dump mode, the DIN pin should not be high; otherwise, the AD7732 will be reset.

Figure 18 shows the digital interface signals performing a single conversion on channel 0, waiting for the RDY pin to go low, and reading the channel 0 status and data registers in dump mode.

Continuous conversion mode

When writing to the mode register, the ADC status byte is cleared and the RDY pin goes high, regardless of its previous state. When a continuous conversion command is written to the mode register, the ADC starts converting on the channel selected by the address of the mode register.

After the conversion is complete, the relevant channel data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, and the AD7732 continues to convert on the next enabled channel. The part will cycle through all enabled channels until another mode is entered or reset. The period period will be the sum of the transition times of all enabled channels, set by the corresponding channel transition time registers.

When the associated channel data register is being read. The behavior of the RDY pin depends on the RDYFN bit in the I/O port register. When the RDYFN bit is 0, the RDY pin goes low when any channel has unread data. When the RDYFN bit is set to 1, the RDY pin will go low only when all enabled channels have unread data.

If the ADC conversion result has not been read before the new ADC conversion is complete, the new result will overwrite the previous one. The associated RDY bit goes low and the RDY pin goes high for at least 163 MCLK cycles (~26.5 µs), indicating when the data register is updated and previous conversion data is lost.

If the data register is read while the ADC conversion is complete, the data register will not be updated with the new result (to avoid data corruption) and the new conversion data will be lost.

Figure 19 shows the sequence of digital interface signals in continuous conversion mode with channels 0 and 1 enabled and the RDYFN bit set to 0. The RDY pin goes low and the data register is read after each conversion. Figure 20 shows a similar sequence, but with the RDYFN bit set to 1. The RDY pin goes low to read all data registers after all conversions are complete. Figure 21 shows the RDY pin when no data is being read from the AD7732.

Continuous Read (Continuous Conversion) Mode

When the Cont RD bit in the mode register is set, the first write of 48h to the communication register starts continuous read mode. As shown in Figure 22, subsequent accesses to the components sequentially read the channel status and data registers of the last completed conversion without requiring any further configuration of the communication registers.

Note that the continuous conversion bit in the mode register should be set when entering continuous read mode.

Note that the continuous read mode is a dump mode read of the channel status and data registers, independent of the dump bit value. Use the channel bits in the channel status register to check/identify that the channel data is actually shifted out.

Note that the last completed conversion result is being read. Therefore, the RDYFN bit in the I/O port register should be 0. The read result should always start before the next conversion is complete.

As long as the DIN pin is low and the CS pin is low, the AD7732 will remain in continuous read mode; therefore, a 0 is written to the AD7732 when reading in continuous read mode. To exit continuous read mode, hold the DIN pin high for at least 100 ns after the read is complete. (Write 80h to AD7732 to exit continuous read.)

Bringing the DIN pin high does not change the Cont RD bit in the mode register. Therefore, the next write of 48h starts the continuous read mode again. To stop continuous read mode completely, write to the mode register to clear the Cont RD bit.

Circuit Description

The AD7732 is a sigma-delta ADC used to measure wide dynamic range, low frequency signals in industrial process control, instrumentation, and PLC systems.

It contains thin film resistor dividers, multiplexers, input buffers, sigma-delta (or charge balance) ADCs, digital filters, clock oscillators, digital I/O ports, and serial communication interfaces.

Analog front end

The AD7732 has two fully differential analog inputs. On-chip thin-film resistor dividers allow direct connection of ±10 V, ±5 V, 0 V to +10 V, and 0 V to +5 V input signals to analog input pins.

The resistive divider input stage is followed by a multiplexer, followed by a wideband, fast settling time differential input buffer capable of driving the dynamic load of a high-speed sigma-delta modulator.

In normal circuit configuration, the bias pin is connected to a 2.5 V (reference) voltage source. This ensures that the differential signal seen by the internal input buffer is within the absolute/common-mode range, that is, AGND+200 mV to AVDD–300 mV.

The AD7732 AIN differential voltage should be within the specified nominal (up to ±10 V) input range, otherwise channel performance may be degraded (see the Extended Voltage Range for Analog Inputs section).

The AD7732 INL performance varies with AIN common-mode voltage (Figure 9). The differential analog input voltage is ±10 V and the common-mode voltage is 0 V, which means that the AIN differential voltage is concentrated around AGND, and AIN+ and AIN(–) vary within ±5 V relative to AGND. The AD7732 INL also varies with MCLK frequency (Figure 7).

AIN pin absolute voltages up to ±16.5 V will not degrade adjacent channel performance if the bias pins are in the normal configuration. AIN absolute voltages exceeding ±16.5 V cause current to flow through the internal protection diode behind the thin film resistor; adjacent channels are affected. By configuring the bias and RA to RD pins differently, as long as the internal voltage seen by the multiplexer and input buffer is between 200 mV and AVDD – 300 mV, the part will operate at higher absolute voltages at AIN work under. The absolute voltages on the AIN, BIAS, and RA to RD pins must not exceed the values specified in Absolute Maximum Ratings.

Note that the OVR bit in the channel status register is digitally generated from the conversion result and indicates that the sigma-delta modulator (nominal) is overrange. The OVR bit does not indicate that the AIN pin absolute/common mode voltage limit has been exceeded.

Figure 23 shows the AD7732 analog input internal structure.

Extended voltage range for analog inputs

The AD7732 output data code range corresponds to the nominal input voltage range. ADCs operate outside the nominal input voltage range, but performance may be degraded. The sigma-delta modulator is designed to fully cover differential input voltages of ±11.6v; outside this range, performance may degrade more rapidly. Adjacent channels are not affected by absolute analog input voltages up to ±16.5 V (Figure 8).

When the clamp in the mode register is set to 1, the channel data register will be digitally clamped to all 0s or all 1s when the analog input voltage exceeds the nominal input voltage range.

As shown in Table 16 and Table 17, when clamp = 0, the data reflects an analog input voltage outside the nominal voltage range. In this case, the sign and OVR bits in the channel status register should be considered along with the data register value to decode the actual conversion result.

Note that the OVR bit in the channel status register is digitally generated from the conversion result and indicates that the sigma-delta modulator (nominal) is overrange. The OVR bit does not indicate that the absolute voltage limit of the AIN pin has been exceeded.

chopped

With chopping enabled, the multiplexer repeatedly inverts the ADC input. Each output data result is then calculated as the average of two transformations, the first transformed to a positive and the second a negative offset term. This effectively removes any offset errors from the input buffer and sigma-delta modulator.

However, chopping is only applied after the input resistor divider stage; therefore, chopping cannot eliminate offset errors and drift caused by resistors. Figure 24 shows the channel signal chain with chopping enabled.

Multiplexer, conversion and data output timing

The specified conversion time includes one or two settling and sampling periods and the scaling time.

With chopping enabled (Figure 25), the conversion cycle begins with a settling time of 43 MCLK cycles or 44 MCLK cycles (about 7 microseconds for 6.144 MHz MCLK) to allow the circuit following the multiplexer to settle. Then, a sigma-delta modulator samples the analog signal, and a digital filter processes the digital data stream. The sampling time depends on the FW, ie on the contents of the channel switching time register. After another 42 MCLK cycles (~6.8 μs) of stabilization, the sampling time is repeated using an inverted (chopped) analog input signal. Then, over a scaling time of 163 MCLK cycles (~26.5 μs), the two results from the digital filter are averaged, scaled using the calibration register, and written to the channel data register.

With chopping disabled (Figure 26), there is only one sample time before the settling time of 43 MCLK cycles or 44 MCLK cycles, followed by 163 MCLK cycles.

The RDY pin goes high during the scaling time regardless of its previous state. The relevant RDY bit is set in the ADC status register and the channel status register, and the RDY pin goes low when the channel data register is updated and the channel conversion cycle ends. If in continuous conversion mode, the part will automatically continue the conversion cycle on the next enabled channel.

Note that the conversion time and chop mode can be configured independently for each channel. The full cycle and effective per-channel data rate depends on all enabled channel settings.

Sigma Incremental ADC

The AD7732 core consists of a charge-balanced sigma-delta modulator and a digital filter. The architecture is optimized for fast, fully pinned transitions. This allows fast inter-channel switching while maintaining inherently good linearity, high resolution and low noise.

Frequency response

The sigma-delta modulator runs at 1/2 the MCLK frequency, which is actually the sampling frequency. Therefore, the Nyquist frequency is one quarter of the MCLK frequency. The digital filter, along with the modulator, has the frequency response of a first-order low-pass filter. The -3db point is close to the frequency of 1/channel transition time. The roll-off is -20db/dec up to the Nyquist frequency. If chopping is enabled, the input signal is resampled by chopping. Therefore, the overall frequency response characteristic is close to frequency 1/channel transition time. The envelope at the top is also the ADC response –20 dB/dec.

Typical frequency response curves are shown in Figure 27 and Figure 28. Graphs are normalized to 1/channel transition time.

Voltage reference input

The AD7732 has a differential reference input, REF IN (+) and REF IN (–). The common mode range of these inputs is from AGND to AVDD. The nominal differential reference voltage for specified operation is 2.5 V. Both reference inputs have dynamic loads. Therefore, the reference input should be connected to a low impedance reference voltage source. External resistor/capacitor combinations can cause gain errors in the part.

The output noise performance listed in Table 4 through Table 9 applies to an analog input of 0 V and is not affected by noise on the reference. To obtain the same noise performance as shown in the noise table over the entire input range, the AD7732 requires a low noise reference source. Excessive reference noise in the bandwidth of interest can degrade the performance of the AD7732.

Recommended voltage references for the AD7732 include the AD780, ADR421, REF43, and REF192. Note that in a typical connection, if a positive voltage is applied to the analog input, the voltage reference must be able to sink current from the bias pin through an internal resistor. The AD780 meets this requirement. If the voltage reference used in the application cannot sink current, an external resistor (5 kΩ) should be connected in parallel to the REFIN pin.

Reference detection

The AD7732 includes on-chip circuitry to detect whether the part has a valid conversion reference. If the voltage between the REFIN(+) and REFIN(–) pins is below the NOREF trigger voltage (0.5 V typical) and the AD7732 is performing a conversion, set the NOREF bit in the channel status register.

I/O ports

The AD7732 P0 pin can be used as a general purpose digital I/O pin. The P1 pin (SYNC/P1) can be used as a general purpose digital I/O pin or to synchronize the AD7732 with other devices in the system. When the sync bit in the I/O port register is set and the sync pin is low, the AD7732 does not process any conversions. If it is put into single conversion mode, continuous conversion mode, or any calibration mode, the AD7732 will wait for the sync pin to go high before starting operation. This allows the transition to start in time from a known point, i.e. the rising edge of the synchronous pin.

The digital P0 and P1 voltages are referenced to the analog supply. When configured as an input, the pins should be tied high or low.

calibration

The AD7732 provides zero-scale self-calibration and zero-scale and full-scale system calibration functions that effectively reduce offset and gain errors to noise levels. After each conversion, the ADC conversion result is scaled using the ADC calibration register and the associated channel calibration register before writing it to the data register.

For unipolar range:

For bipolar range:

where the ADC result is in the range 0 to ffffff h.

Note that the channel zero-scale calibration register has the format of a sign bit and a 22-bit channel offset value. The user is strongly advised not to change the ADC full-scale registers.

To start any calibration, write the relevant mode bits into the AD7732 mode register. After the calibration is completed, update the content of the corresponding calibration register, set all RDY bits in the ADC status register, the RDY pin goes low, and the AD7732 returns to idle mode. The calibration duration is the same as the conversion time configured on the selected channel. A longer conversion time produces less noise and produces a more accurate calibration; therefore, use at least the default conversion time to initiate any calibration.

ADC zero-scale self-calibration

ADC zero-scale self-calibration reduces offset errors in chop-disabled mode. It also reduces offset drift errors in chopper disabled mode if repeated after a temperature change.

A zero-scale self-calibration is performed on the internally shorted ADC input. The negative analog input terminal on the selected channel is used to set the ADC zero-scale calibration common mode. Therefore, the negative terminal of the selected differential pair or AINCOM on a single-ended channel configuration should be driven to the appropriate common-mode voltage.

It is strongly recommended that the ADC zero-scale calibration registers be updated only as part of a zero-scale self-calibration.

System calibration per channel

If using per-channel system calibration, start in the following order: channel zero-scale system calibration, then channel full-scale system calibration.

System calibration is affected by the ADC zero-scale and full-scale calibration registers. Therefore, if both self-calibration and system calibration are used in the system, the ADC full-scale self-calibration should be performed first, followed by the system calibration loop.

When performing a system calibration, a fully fixed system zero-scale voltage signal or system full-scale voltage signal must be connected to the selected channel analog input.

Each channel calibration register can be read, stored or modified and written back to the AD7732. Note that the AD7732 must be in idle mode when writing to the calibration registers. Note that outside the specified calibration range, calibration can be performed, but performance may be degraded.

High Common Mode Voltage Applications

The AD7732 AIN0 can be easily configured to accept high common-mode voltages using additional thin-film resistors on AIN0 and an external op amp with ±15 V supplies.

Dimensions

ESD warning

Electrostatic discharge sensitive devices. Electrostatic charges of up to 4000 volts can easily build up on the human body and test equipment and can be discharged without detection. Although this product has proprietary ESD protection circuitry, permanent damage may occur on equipment subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.