feature

Bipolar input range; pin-to-pin compatible with ADS7844 and ADS8344; single supply: 2.7V to 5V; 8-channel single-ended or 4-channel differential input; slew rate up to 100kHz; 85dB beacon; serial interface; QSOP-20 and SSOP-20 package.

application

data acquisition; test and measurement equipment; industrial process control; personal digital assistants; battery powered systems.

illustrate

The ADS8345 is an 8-channel 16-bit sampling analog-to-digital converter with a synchronous serial interface. Typical power consumption is 8mW, 100kHz throughput and +5V supply. The reference voltage (V) can be varied between 500mV and V/2, providing a corresponding input voltage range of ±V. The unit includes a shutdown mode that reduces power consumption to less than 15 microwatts. The ADS8345 ensures an operating voltage as low as 2.7 volts.

The low power consumption, high speed, and on-board multiplexer make the ADS8345 ideal for battery-operated systems such as personal digital assistants, portable multi-channel data loggers, and measurement equipment. The serial interface also provides low-cost isolation for remote data acquisition. The ADS8345 is available in a QSOP-20 or SSOP-20 package and is guaranteed over a temperature range of -40°C to +85°C.

Absolute Maximum Ratings

Notes: (1) Stresses higher than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Prolonged exposure to absolute maximum conditions may affect device reliability.

Electrostatic Discharge Sensitivity

This integrated circuit may be damaged by electrostatic discharge. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to follow proper operation and installation procedures may result in damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits can be more susceptible to damage because very small parameter changes can cause the device to not meet its published specifications.

Typical characteristics: +5V

T=+25°C, +V=+5V, V=+2.5V, f=100kHz, f=24•f=2.4MHz, unless otherwise stated.

Typical Characteristics: +2.7V

T=+25°C, +V=+2.7V, V=+1.25V, f=100kHz, f=24•f=2.4MHz, unless otherwise stated.

theory of operation

The ADS8345 is a typical successive approximation register A/D converter. The architecture is based on capacitive redistribution, which essentially includes sample and hold functionality. The converter is fabricated using a 0.6μm CMOS process.

The basic operation of the ADS8345 is shown in Figure 1. The device requires an external reference and an external clock. It operates from a single supply of 2.7V to 5.25V. The external reference voltage can be any voltage between 500 and +V/2. The value of the reference voltage directly sets the input range of the converter. The average reference input current depends on the slew rate of the ADS8345.

The analog inputs to the converter are differential and provided through an eight-channel multiplexer. Inputs can be supplied referenced to the voltage on the COM pin (usually +V/2) or differentially by using four of the eight input channels (CH-CH7). Specific configurations can be selected via the digital interface.

analog input

The analog inputs are bipolar and fully differential. There are two general methods of driving the analog inputs of the ADS8345: single-ended or differential (see Figure 2). When the input is single-ended, the COM input is held at a fixed voltage. The CHX input swings around the same voltage, with a peak-to-peak amplitude of 2.V, determining the range over which the common voltage may vary (see Figure 3).

When the input is differential, the amplitude of the input is the difference between the CHX and COM inputs (see Figure 4). A voltage or signal is common to both inputs. The peak-to-peak amplitude of each input is approximately V of this common voltage. However, since the inputs are 180°C out of phase, the peak-to-peak amplitude of the differential voltage is 2•V. The value of V also determines the voltage range that the two inputs may share (see Figure 5).

In each case, care should be taken to ensure that the output impedances of the sources driving the CHX and COM inputs are matched. If this is not observed, the two inputs may have different settling times. This can lead to offset errors, gain errors, and linearity errors that vary with temperature and input voltage. If the impedances cannot be matched, the error can be reduced by giving the ADS8345 additional acquisition time.

The input current on the analog input depends on many factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8345 charges the internal capacitor array during sampling. After the capacitor is fully charged, there is no more input current.

Attention must be paid to the absolute analog input voltage. Outside these ranges, the linearity of the converter may be out of specification. Refer to the Electrical Characteristics table for min/max ratings.

reference input

The external reference sets the analog input range. The ADS8345 will operate from a reference voltage range of 500mV to +V/2. Remember, the analog input is different - the ence between the CHX input and the COM input, as shown in Figure 4. For example, in single-ended mode, the COM pin is a 1.25V reference for V/2, the selected input channel (CH0-CH7) will be correctly digitized (V/2–1.25V) to (V/2+1.25V) range of signals.

There are several key terms for the reference input and its wide voltage range. As the reference voltage decreases, the analog voltage weighting for each digital output code also decreases. This is often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 65536. Any offset or gain error inherent in the A/D converter increases with the size of the LSB as the reference voltage decreases. For example, if the offset for a given converter is 2LSB (with a 2.5V reference), it will typically be 10LSB (with a 0.5V reference). In each case, the actual offset of the device is the same, 152.8 microvolts.

As the size of the LSB decreases, the noise or uncertainty of the digitized output increases. When the reference voltage is 500 mV, the dimension of the LSB is 15.3 microvolts. This level is lower than the internal noise of the device. As a result, the digital output code will be unstable and will vary by several lsb around the average. The distribution of the output codes will be Gaussian, and noise can be reduced by simply averaging successive conversion results or applying a digital filter.

In the case of low reference voltages, care should be taken to provide a clean layout, including adequate bypassing, clean (low noise, low ripple) power supplies, low noise references, and low noise input signals. Due to the smaller size of the LSB, the converter is also more sensitive to nearby digital signals and electromagnetic interference.

The voltage at the V input is unbuffered and directly drives the capacitor digital-to-analog converter (CDAC) portion of the ADS8345. Typically, the input current is 13 microamps and the reference voltage is 2.5V. Depending on the conversion result, this value will vary in microamps. The reference current decreases with increasing slew rate and reference voltage. Since the current from the reference is drawn on every bit decision, clocking the converter faster during a given conversion does not reduce the overall current consumption from the reference.

digital interface

The ADS8345 has a 4-wire serial interface compatible with multiple microprocessor families (note that the digital inputs can tolerate overvoltages up to +5.5V regardless of +V). Figure 6 shows the typical operation of the ADS8345 digital interface.

Most microprocessors communicate using 8-bit transfers; as long as the timing is shown in Figure 6, the ADS8345 can perform a total of 24 clock cycles of conversion with three such transfer layers on the DCLK input.

The first 8 clock cycles are used to provide the control byte through the D pin. When the converter has enough information about the following conversions to properly set the input multiplexer, it enters acquisition (sampling) mode. After another four clock cycles, the control byte is complete and the converter enters conversion mode. At this point, enter sample and hold to enter hold mode. The next 16 clock cycles complete the actual A/D conversion.

control byte

Figure 6 shows the position and order of the control bits in the control byte. Tables 1 and 2 give the details of these bits. The first bit, the "S" bit, must always be high and indicates the start of the control byte. The ADS8345 will ignore the input on the D pin until a start bit is detected. The next three bits (A2-A0) select one or more active input channels of the input multiplexer (see Tables III and IV and Figure 4).

The SGL/DIF bit controls the multiplexer input mode: either in single-ended mode, where the selected input channel is referenced to the COM pin, or differential mode, where the two selected inputs provide differential inputs. See Table 3, Table 4 and Figure 4 for details. The last two bits (PD1-PD0) select power-down mode and clock mode, as shown in Table V. If both PD1 and PD0 are high, the device is always powered on. If both PD1 and PD0 are low, the device enters power-down mode between transitions. When a new transition is initiated, the device will resume normal operation immediately - no delay is required to power up the device and the first transition will be valid.

clock mode

The ADS8345 can be used with an external serial clock or an internal clock to perform successive approximation conversions. In both clock modes, an external clock shifts data in and out of the device. When PD1 is high and PD0 is low, internal clock mode is selected.

If the user decides to switch from one clock mode to another, additional conversion cycles are required before the ADS8345 switches to the new mode. Additional cycles are required because the PD0 and PD1 control bits need to be written to the ADS8345 before the clock mode is changed.

When the ADS8345 is first powered up, the user must set the desired clock mode. Can be set by writing PD1=1 and PD0=0 or PD1=1 and PD0 for internal clock mode = 1 to indicate external clock mode. With the desired clock mode enabled, the ADS8345 should be set to power down only between conversions (ie, PD1=PD0=0). The ADS8345 maintains the clock mode it was in before entering power down mode.

external clock mode

In external clock mode, the external clock not only shifts data in and out of the ADS8345, but also controls the A/D conversion steps. Busy will go high for one clock cycle after the last bit of the control byte is shifted in. On each of the next 16 DCLK falling edges, successive approximation bit decisions are made at D (see Figure 6). Figure 7 shows busy timing in external clock mode.

Since one clock cycle of the serial clock is consumed while busy high (when making the MSB decision), 16 additional clocks must be given to clock all 16-bit data; therefore, a conversion requires at least 25 clock cycles to fully read fetch data. Since most microprocessors communicate in 8-bit transfers, this means that additional transfers must be made to capture the LSB.

There are two ways to handle this requirement. One is that the start of the next control byte occurs at the same time the ADS8345 is clocked the LSB (see Figure 6). This method allows maximum throughput and 24 clock cycles per conversion.

Another approach, shown in Figure 8, uses 32 clock cycles per conversion; the last 7 clock cycles simply move zeros on the D line. Busy, I'm going to high impedance state, when CS goes high; BUSY will go low after the next CS falling edge.

Internal clock mode

In internal clock mode, the ADS8345 generates its own conversion clock internally. This eliminates the need for the microprocessor to generate the SAR conversion clock and allows the conversion results to be read at any clock rate from 0MHz to 2.0MHz at the convenience of the processor. BUSY goes low at the start of a conversion and then returns to HIGH when the conversion is complete. During the conversion process, BUSY will remain low for a maximum of 8 microseconds. Additionally, DCLK should be held low during conversions for best noise performance. The conversion result is stored in an internal register; data can be clocked from this register at any time after the conversion is complete.

If CS is low when busy goes low after conversion, the next falling edge of the external serial clock will be written to the MSB on line D. The remaining bits (D14-D0) will be clocked on each successive clock cycle following the most significant bit. If CS is high when busy goes low, the D line will remain tri-stated until CS goes low, as shown in Figure 9. CS does not need to be held low once a conversion has started. Note that when CS goes high in internal clock mode, it is not tri-stated busy.

At clock rates above 2.4MHz, data can be shifted in and out of the ADS8345, provided the minimum capture time t remains above 1.7 microseconds.

digital timing

Figure 7 and Tables VI and VII provide the detailed timing of the ADS8345 digital interface.

Data Format

The output data from the ADS8345 is in binary 2's complement format, as shown in Table VIII. This table represents the ideal output code for a given input voltage, excluding the effects of offset, gain error, or noise.

Power consumption

The ADS8345 has three power modes: full power (PD1-PD0=11B), automatic shutdown (PD1-PD0=00B), and shutdown (SHDN low). The effect of these modes depends on how the ADS8345 operates. For example, at full conversion rate and 24 clocks per conversion, the difference between full power mode and automatic shutdown is small; shutdown does not reduce power consumption.

When operating at full speed and 24 clocks per conversion (see Figure 6), the ADS8345 spends most of its time acquiring or converting. Assuming this mode is active, the time for automatic shutdown is short. Therefore, the difference between full power mode and automatic shutdown is negligible. If the slew rate is reduced by simply slowing down the frequency of the DCLK input, the two modes remain approximately equal. However, if the DCLK frequency remains at the maximum rate during transitions, but the number of transitions is small, the difference between the two modes is significant. In the latter case, the converter spends an increasing percentage of time in power-down mode (assuming auto power-down mode is active).

When the ADS8345 is in auto power-down mode, if DCLK is active and CS is low, the device will continue to consume some power in the digital logic. Keeping CS high minimizes power.

Operating the ADS8345 in auto-power-down mode will result in the lowest power consumption and no transition time "penalty" at power-up. The first conversion will be valid. SHDN can be used to force an immediate power down.

noise

The noise floor of the ADS8345 itself is quite low (see Figures 10 and 11). The ADS8345 was tested at 5V and 2.7V and in internal and external clock modes. The analog input pin adopts low-level DC input, and the converter undergoes 5000 conversions. The digital output of the A/D converter will vary in the output code due to the internal noise of the ADS8345. This applies to all 16-bit SAR type A/D converters. Use a histogram to plot the output codes, the distribution should be bell-shaped, with the peaks of the bell-shaped curve representing the nominal codes of the input values. The ±1σ, ±2σ and ±3σ distributions of all codes are 68.3%, 95.5% and 99.7%, respectively. Transition noise can be calculated by dividing the number of codes measured by 6, which yields a ±3σ distribution of all codes, or 99.7%. According to statistics, up to 3 codes may not be in the distribution when performing 1000 conversions. The ADS8345 has 5 output codes for a ±3σ distribution and produces <±0.83LSB transition noise at 5V operation. Remember, to achieve this low noise performance, the peak-to-peak noise of the input and reference signals must be less than 50 microvolts.

average value

The noise of the A/D converter can be compensated by averaging the digital code. By averaging the conversion results, the conversion noise will be reduced by a factor of 1/√n, where n is the average. For example, averaging 4 conversion results will reduce conversion noise by 1/2 ±0.25LSB. Average can only be used for input signals with frequencies close to DC.

For AC signals, a digital filter can be used for low-pass filtering and decimation of the output code. It works similarly to averaging: for every 2 decimations, the signal-to-noise ratio increases by 3dB.

layout

For best performance, attention should be paid to the physical layout of the ADS8345 circuit. This is especially true if the reference voltage is low and/or the slew rate is high.

The basic SAR architecture is very sensitive to faults or sudden changes in power supplies, references, ground connections, and digital inputs that occur at the outputs of the analog comparators. Therefore, in any conversion process of the n-bit synthetic aperture radar converter, there are n "windows", in which the larger external transient voltage easily affects the conversion result. Such failures can originate from switching power supplies, nearby digital logic, and high-power equipment. The degree of error of the digital output depends on the reference voltage, layout, and precise timing of external events. The error may change if the time of the external event changes relative to the DCLK input.

With this in mind, the supply to the ADS8345 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, 1µF to 10µF capacitors and 5Ω or 10Ω series resistors can be used to low pass filter noise power supplies.

Again, the reference should be bypassed with a 0.1µF capacitor. Again, series resistors and bulk capacitors can be used as the reference voltage for the low pass filter. If the reference voltage is sourced from an op amp, make sure it can drive the bypass capacitor without oscillation (a series resistor can help in this case). On average, the ADS8345 draws very little current from the reference circuit, but it does place more demands on the reference circuit for short periods of time (during transitions, on every rising edge of DCLK).

The ADS8345 architecture does not provide inherent rejection of noise or voltage variations associated with the reference input. This is especially of concern when the reference input is connected to the power supply. Any noise and ripple from the power supply will appear directly in the digital results. While high frequency noise can be filtered out as discussed in the previous paragraph, voltage variations due to line frequency (50 Hz or 60 Hz) can be difficult to remove.

The ground pin should be connected to a clean ground point. In many cases this will be the "analog" ground. Avoid making connections too close to the microcontroller or digital signal processor ground. If required, ground trace directly from the converter to the power entry point. An ideal layout would include an analog ground plane dedicated to the converter and associated analog circuitry.

Packaging diagram

DBQ (R-PDSO-G**)

Display 24 pins

Notes: A. All linear dimensions are in inches (millimeters).

B. This picture is subject to change without notice.

C. Body dimensions do not include mold flash or protrusions not exceeding 0.006 (0,15).

D. Belong to JEDEC MO-137.

Decibel (R-PDSO-G**)

28 pins shown

Note: A. All linear dimensions are in millimeters.

B. This picture is subject to change without notice.

C. The valve body size does not include flash or protrusions not exceeding 0.15.

D. Belong to JEDEC MO-150.