illustrate

HR1000A is a specially designed controller for resonant half-bridge topology. It provides two drive signal channels to output complementary signals at 50% duty cycle. An internal fixed dead time between the two complementary gate signals ensures transient and enables high frequency operation. The integrated bootstrap diode simplifies the external drive circuit of the high-side switch. It can withstand voltages up to 600 volts and is immune to high dV/dt noise. Modulating the switching frequency adjusts the topology output voltage. The programmable oscillator can set the maximum and minimum switching frequency. The IC starts with a programmed maximum switching frequency that gradually slows down until the control loop takes over to prevent excessive inrush current. The IC can be forced into a controlled burst-light-load mode operation to drain power and tighten output regulation. Protection features include latching shutdown, auto-recovery, brown protection, and -temperature protection. The improved inverter design is safe and does not create additional circuit complexity. The IC provides 1.5A/2A source/sink capable high-side and low-side gate drivers.

feature

50% Duty Cycle, Variable Frequency Resonant Half-Bridge Converter Control Operating frequency up to 600kHz Two-stage overcurrent protection: frequency shift and latched shutdown Programmable duration Remote on/off control and brown output Protection via BO Pin Latch disable input for easy protection implementation Interface with PFC controller Programmable burst mode Operating Light Load Monotonic Output Nonlinear Soft Start Voltage Rise SO-16 Package

application

LCD and PDP TVs

Desktop PCs and Servers

Telecom SMPS

AC-DC Adapter, Open Frame Switching Power Supply

video game console

Electronic Lighting Ballast

Recommended Operating Conditions (3)

Supply voltage VCC, 13V to 15.5V

Analog input and output. -0.3V to 6.5V

Operating Junction Temperature (TJ) -40°C to +125°C

Thermal resistance (4) θJAθJC

SOIC16, 80.35 degrees Celsius

notes:

1) Exceeding these ratings may damage the device.

2) The maximum allowable power dissipation is the maximum junction temperature TJ (MAX), the junction-to-ambient thermal resistance θJA, and the ambient temperature. The maximum allowable continuous power dissipation for any ambient temperature is calculated as

D(MAX)=(TJ(MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage.

3) The device is not guaranteed to operate outside its operating conditions.

4) Measured on JESD51-7 four-layer PCB.

Electrical Characteristics

TJ=25°C, VCC=13V, C HG=C LG=1nF; CT=470pF, R Fset=12kΩ, unless otherwise specified

Electrical Characteristics (continued)

TJ=25°C, VCC=13V, CHG=CLG=1nF; CT=470pF, R Fset=12kΩ, unless otherwise specified.

Typical performance characteristics

Performance waveforms were generated using the evaluation board, AC voltage = 230V, voltage output = 19V, input output = 4.7A, TA = 25°C unless otherwise noted.

Function description

Oscillator: The charge and discharge time of the capacitor determines the oscillator frequency. The voltage across this CT capacitor forms a peak-to-valley threshold triangle waveform. Figure 2 shows the detailed waveforms at steady state.

The network connected to the Fset pin charges and discharges the capacitor on the current transformer, as shown in Figure 3. The current at the source Fset pin controls the current supply 1 (I S-1) that charges the CT capacitor. Here, the current mirror ratio within the HR1000A is 1A/A. When the switching cycle begins, IS-1 charges the CT capacitor until the voltage triggers the peak threshold voltage. Then the discharge current source (I S-2) has the source current of the Fset pin turned on. Therefore, the CT capacitor uses the source current of the Fset pin. When the voltage on the CT capacitor drops to the valley threshold voltage, IS-2 is turned off and a new switching cycle is then enabled. According to the block diagram shown in Figure 3, the function of the Fset RC network is as follows: 1. Rf min from Fset pin to GND sets the maximum resistance of the external RC network When the phototransistor is blocked, so set the Fset minimum source current, set the minimum switch frequency;

2. Under normal operation, the phototransistor modulates the current through Rf max to regulate the frequency regulation of the output voltage. When the phototransistor is saturated and the current through Rf max is at its maximum value, set the frequency to the maximum

3. The series RC circuit GND between Fset determines the startup. (See the Soft-Start section for details.) Based on the previous principles, the following equations describe the minimum and maximum frequencies:

Typically, CT capacitance is between 0.1nF and 1nF, so the values of Rf min and Rf max are:

For CT capacitor selection, here is a note for low temperature high switching frequency applications: when the temperature is low, the Fset pin's sourcing current capability drops slightly due to the characteristics of the internal transistor circuit, which means that the current is not sufficient to charge and discharge the large CT capacitor. So a small CT cap is recommended for this type of application (<=330pF). Burst mode operation at light or no load limits the maximum frequency to half the resonance - the bridge switching frequency. Controlling the output voltage and limiting the power dissipation HR1000A enables compatible converters to operate in burst mode to drastically reduce the average switching frequency, thereby reducing the losses associated with the average residual magnetizing current. Operation in burst mode requires setting if the burst pin drops below 1.25V, the HR1000A turns off and reduces the HG and LG gate drive outputs, leaving only the 2V reference voltage Fset pin and SS pin to retain the previous power of the HR1000A to minimize consumption. When the voltage pin on the pulse exceeds 1.25V × 50mV, the HR1000A resumes normal operation. Based on how Burst Mode works, the burst pin voltage must be connected to the feedback loop. Figure 4 shows a typical circuit connecting the burst pin to a narrow input-voltage range application:

In addition to setting the oscillator, Rf max determines the maximum switching frequency HR1000A operates in burst mode. After confirming f max, calculate Rf max as follows:

Here, fmax corresponds to a loading point, Pburst, where the peak current flowing through the transformer is too low to produce sound. The above description is based on the input voltage range. As a resonant circuit, the input voltage also determines the switching frequency. That is, the P pulse has a large variation range over a wide input voltage. To stabilize the burst over the input range, insert the input voltage signal into the feedback loop using the circuit in Figure 5.

Figure 5: Setting Wide Bust Mode Operation

Input Voltage Range R B1 and R B2 in Figure 5 are related to a wide input voltage range. Choose two resistors based on experimental results. Please note that the total resistance of RB1 and RB2 should be much larger than RH to reduce the effect on BO pin voltage. During burst mode operation, when the load is below Pburst, the switching frequency is clamped at the maximum frequency. Then the output voltage must be higher than the set value, which will increase the current through the optocoupler. Therefore the voltage on Rf max must rise because of the phototransistor current. The pulse pin voltage then drops below 1.25 volts, triggering the gate off state. Until the output voltage falls below the set value, the current flows through the optocoupler and then decreases, causing the burst pin voltage to rise. When the voltage exceeds 1.25V+100mV, the IC restarts to generate the gate signal. The IC will continue to operate with no load or light load to reduce the average power consumption. PFC Disable Function Many applications require the PFC function to make pre-regulator circuit commons extensively before resonance. Under certain conditions, eg. No load or light load, OCP, OVP require PFC to be disabled.

Figure 6: PFC disable block diagram

HR1000A provides PFC disable. The PFC pin is low when one of the following is pulled: gate closed in burst mode (burst voltage < 1.25V); OCP (CS > 1.5V); input overvoltage (BO > 5.5V); pin high (pin > 5.5V) 1.85V); the timer pin voltage will not drop to 0.3V when it exceeds 2V; and the overheat protection is triggered. Turn off the PFC to reduce power consumption or protect the system. Figure 7 shows the HR1000A and the PFC controller (MP44010/1 is the PFC controller).

Soft-start operation for resonant half-bridge converter output power versus switching frequency. To achieve soft start, start at a high value of the switching frequency until the value is controlled by closed loop. The converter+HR1000A is easy to implement using an external RC series circuit as a soft start as shown in Figure 8.

When start-up begins, the SS voltage is 0V, so the soft-start resistor (R SS) is in parallel with Rf min: Rf ming and R SS determine the initial frequency as:

During startup, C SS is charged until its voltage reaches the reference voltage -2V, and the current through R SS drops to zero. This time is about 5×(R SS×C SS). The switching frequency changes exponentially during this period: the initial value of the C SS charge decays relatively quickly, but the rate gradually becomes slower. After this period is over, the output voltage is not still close to the setpoint, so the feedback loop will take over to start. During soft start, the input current increases gradually until the output voltage reaches the set point with a little overshoot. According to the formula as follows:

Choose an initial frequency, fstart, of at least 4 × fmin. at the desired soft-start operation and OCP speed (see next section for details). Current Sensing Figure 9 shows the current sensing block diagram

There are two levels of overcurrent protection. When the CS voltage exceeds 0.8V, the comparator triggers the control logic that outputs the advanced control signal to open the connection between SS and ground. The C SS voltage drop then causes an increase in the oscillator frequency, thus reducing the energy delivered to the output. When the CS pin voltage drops back to 0.79V, the inverter resumes normal operation thanks to the 10mV hysteresis effect. Typically, the CS pin voltage continues to rise when shorted. Secondary above - when the CS pin voltage rises to 1.5V. The IC is then locked at very low consumption (remaining consumption EC table). For two-level protection, a very large C SS slows down the discharge until the transformer resonant inductance saturates and damages the secondary diode.

There are two methods of current sensing: one uses a sense resistor in series with a low-resistance-side MOSFET; the other uses a lossless current-sensing network. The first method is simple but incurs some unnecessary power consumption. Use the following method to calculate the sense resistance equation

where I Crpk is through the resonant capacitor with a primary MOSFET at low input voltage and full load. Since the circuit requires an RC filter sense resistor and the CS pin, the RC time constant was chosen to be approximately 10/f min

In order to design a lossless current sensing network, the following two conditions are considered: 1. R1 is less than a few hundred ohms. The sensor network acts as a capacitor current divider. Use the following equations:

2. R1 is ~10kΩ. The sensing network acts on the design of the voltage divider ripple voltage. This condition conforms to the following equation:

Calculate C1 and Cr where the maximum peak resonant frequency current occurs. As a rule of thumb, the R2 and C2 time constants are about 10/f min. According to the circuit, consider the calculated value as the need to adjust according to the experimental results to achieve the design goal. OCP can limit energy from primary to secondary or short-circuit during overload. However, excessively high continuous power consumption current can damage the secondary winding and rectifier. The HR1000A provides additional protection to reduce average power consumption during OCP: when OCP is triggered, the converter enters a protection mode with hiccup-like intermittent operation. Set the maximum overload or short circuit by selecting the appropriate operating time (t OC ) for C timer and R timer. The 130µA current source turns on when the CS voltage exceeds 0.8V during the first OCP level to charge the C timer. When the voltage on the C timer reaches 2V, the C SS voltage is lower than the OCP comparator output. This forces f with equal switching frequencies to start to minimize the energy delivered. tOC is the time for the C timer voltage to rise from 0V to 2V. But the relationship between t C and C timer. The choice of C timer is based on experimental results (based on experimentation: C timer may increase operation time by 100ms). When the voltage on the C timer rises to 2V, the 130uA current source continues to charge until the voltage reaches the shutdown threshold (3.5V). This period is approximately: