General Instructions

The ADCS7476 , ADCS7477, and ADCS7478 are low-power monolithic CMOS 12-, 10-, and 8-bit analog-to-digital converters that operate at 1 ms/sec. The ADCS7476/77/78 are replacements for the analog devices AD7476/77/78. Each device is based on a successive approximation area structure with internal track and hold. The serial interface is compatible with multiple standards such as SPI 8482 ;, QSPI™, MicroWire™, and many common DSP serial interfaces.

The ADCS7476/77/78 use the supply voltage as a reference. This enables the device to operate over a full-scale input range of 0 to V. The slew rate is determined by the serial clock (SCLK) speed. These converters provide a shutdown mode that can be used to trade throughput for power consumption. The ADCS7476/77/78 operate from a single supply with a voltage range of +2.7V to +5.25V. Normal power consumption for continuous conversion from +3V or +5V power is 2 MW or 10 MW, respectively. A power-down feature enabled through the chip select (CS) pin reduces power consumption to less than 5 microwatts using a +5V supply. All three converters are packaged in a 6-wire SOT-23 package, providing a very small footprint for applications where space is a key consideration. These products are designed to operate over the automotive/extended industrial temperature range. -40°C to + 125 °C.

feature

Variable power management; packaged in 6-lead, SOT-23; power supply as reference; single-supply +2.7V to +5.25V supply operation; SPI Corporation™/QSI™/Microwire™/Compatible DSP .

Main Specifications

Resolution, no missing code 12/10/8 bits;

Conversion rate 1 MSPS;

DNL +0.5, -0.3LSB (typical);

INL ± 0.4 LSB (typ.);

Power consumption: 2 mW (typical) for 3V power supply; 10 mW (typical) for 5V power supply.

application

Car navigation; FA/ATM equipment; portable systems; medical devices; mobile communications; instrumentation and control systems.

Wiring diagram

Ordering Information

Pin Description

block diagram

Absolute Maximum Ratings

If military/aerospace specific equipment is required, please contact the National Semiconductor Sales Office/Distributor for availability and specifications.

Supply voltage VDD−0.3V to +6.5V; voltage on any analog pin to ground -0.3V to VDD+0.3V; voltage on any digital pin to ground -0.3V to 6.5V; input current on any pin (Note 3) ±10mA; ESD Sensitivity: Human Body Model 3500V; Machine Model 200V; Soldering Temperature, Infrared, 215°C for 10 seconds; Junction Temperature +150 303C; Storage Temperature −65°C to +150°C; Operating Rated Value; Operating Temperature Range TMIN=-40°F C≤TA, ≤TMAX=+125°C VDD Supply Voltage +2.7V to +5.25V; Digital Input Pin Voltage Range (Note 4) +2.7V to +5.25V.

Package thermal resistance

canonical definition

Aperture delay is the time after the falling edge of CS until the input signal is acquired or held for conversion.

Aperture jitter (aperture uncertainty) is the variation in aperture delay between samples. Aperture jitter appears as noise in the output.

Differential nonlinearity (DNL) is a measure of the maximum deviation from an ideal step size of 1 lsb.

The duty cycle is the ratio of the high time of the repeating digital waveform to the total time of one cycle. The specification here refers to SCLK.

The effective number of bits (ENOB or effective number of bits) is another way of specifying a signal to noise and distortion or SINAD. ENOB is defined as (SINAD-1.76)/6.02 and indicates that the converter is equivalent to a perfect ADC of this (ENOB) number of bits.

Full power bandwidth is a measure of the frequency at which the reconstructed output fundamental drops 3db below its low frequency value for a full scale input.

Gain error is the deviation of the last code transition (111…110) to (111…111) after adjusting the offset error from the ideal (V-1.5 LSB for ADCS7476 and ADCS7477, V-1 LSB for ADCS7478).

Integral Nonlinearity (INL) is the deviation of each individual code of the line drawn from negative full scale (/2 LSB below the first code transition) to positive full scale (/2 LSB above the last code transition) metric. The deviation of any given code from this line is measured from the center of the code value.

Intermodulation distortion is an additional spectral component due to the simultaneous application of two sinusoidal frequencies to the ADC input. It is defined as the ratio of the power in the two second-order or all four third-order intermodulation products to the sum of the powers in the two original frequencies. IMD is usually expressed in dBFS.

Missing codes are those output codes that never appear at the ADC output. The ADCS7476/77/78 are guaranteed not to have any missing codes.

The offset error is the deviation of the first code transition (000…000) to (000…001) from the ideal value (ie GND + 0.5 LSB for ADCS7476 and ADCS7477, GND + 1 LSB for ADCS7478).

Signal-to-noise ratio is the ratio of the rms value of the input signal to the rms value of the sum of all other spectral components below half the sampling frequency, measured in decibels, excluding harmonics or DC.

Signal-to-noise ratio plus distortion (S/N+D or SINAD) is the ratio of the rms value of the input signal to the rms value of all other spectral components (including harmonics, but excluding DC) below half the clock frequency , in decibels.

Spurious Free Dynamic Range (SFDR) is the difference in decibels between the rms value of the input signal and the peak spurious signal, where a spurious signal is any signal in the output spectrum that is not present at the input.

Total Harmonic Distortion (THD) is the ratio of the root mean square of the first five output harmonic levels to the output fundamental level, expressed in dBc. THD is calculated as:

where f is the rms power at the fundamental (output) frequency and f to f are the rms power at the first 5 harmonic frequencies.

Total unadjusted error is a combined specification that includes gain error, linearity error, and offset error.

Timing diagram

Typical Performance Characteristics TA=+25℃, VDD=3V, fSAMPLE=1 MSPS, fSCLK=20 MHz, unless otherwise stated, fIN=100 kHz.

application information

1.0 ADCS7476/77/78 Operation

The ADCS7476/77/78 are successive approximation analog-to-digital converters designed around charge redistribution digital-to-analog converters. The simplified scheduling of the ADCS7476/77/78 in track and hold operation is shown in Figures 4 and 5, respectively. In Figure 4, the device is in tracking mode: switch SW1 connects the sampling capacitor to the input, while SW2 balances the comparator input. The device remains in this state until CS is lowered, at which point the device moves to hold mode.

Figure 5 shows the device in hold mode: switch SW1 connects the sampling capacitor to ground, holding the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge redistribution DAC to add or subtract a fixed amount of charge from the sampling capacitor until the comparators are balanced. When the comparator is balanced, the digital word provided to the DAC is a digital representation of the analog input voltage. On the 13th rising edge of SCLK, the device moves from hold mode to track mode.

2.0 using ADCS7476/77/78

The serial interface timing diagrams of the ADCS7476/77/78 are shown in Figures 1, 2, and 3. CS is the chip select that initiates conversions and frames the serial data transfer on the ADCS7476/77/78. SCLK (serial clock) controls the conversion process and timing of serial data. SDATA is the serial data output pin where the conversion result is found as a serial data stream.

The basic operation of the ADCS7476/77/78 starts with CS going low, which initiates the conversion process and data transfer. Subsequent SCLK rising and falling edges will be labeled with reference to the CS falling edge; for example, "SCLK third falling edge" should refer to the third falling edge of SCLK after CS has fallen.

When CS falls, the SDATA pin comes out of tri-state and the converter switches from track mode to hold mode. The input signal is sampled and held on the falling edge of CS for conversion. The converter moves from hold mode to track mode on the 13th rising edge of SCLK (see Figures 1, 2, or 3).

The SDATA pin will be re-tri-stated after the 16th falling edge of SCLK or the rising edge of CS, whichever occurs first. The quiet time t must be met after the transition is complete, and then CS is lowered again to start another transition. Reading a complete sample from the ADCS7476/77/78 silently requires 16 SCLK cycles. Sample bits (including any leading or trailing zeros) are clocked on the falling edge of SCLK and are intended to be clocked by the receiver on subsequent falling edges of SCLK. The ADCS7476/77/78 will produce four leading zeros on SDATA, followed by twelve, ten or eight data bits, most importantly the first one. After the data bits, the ADCS7477 clocks out two trailing zeros and the ADCS7478 clocks out four trailing zeros. The ADCS7476 does not clock any trailing zeros; the least significant data bit is valid on the 16th falling edge of SCLK.

When the application is suspended, the first edge on SCLK after CS goes low may be a falling or rising edge. If the first SCLK edge after CS falls is a rising edge, all four leading zeros will be valid on the first four falling edges of SCLK. If the first SCLK edge after CS goes low is a falling edge, the first leading zero may not be set in time for the microprocessor or DSP to read it correctly. The remaining data bits are still clocked on the falling edge of SCLK.

3.0 ADCS7476/77/78 Transfer Function

The output format of the ADCS7476/77/78 is straight binary. Transcoding occurs at intermediate LSB values between consecutive integers. The LSB width of ADCS7476 is VDD/4096; the LSB width of ADCS7477 is VDD/1024; the LSB width of ADCS7478 is VDD/256. The ideal transfer characteristics of the ADCS7476 and ADCS7477 are shown in Figure 6, while the ideal transfer characteristics of the ADCS7478 are shown in Figure 7.

4.0 Sampling Circuit

A typical application of the ADCS7476/77/78 is shown in Figure 8. In this example, combined analog and digital power is provided by the National LP2950 low dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The power supply is bypassed by a capacitor network close to the device. The three-wire interface shown in the figure is also connected to a microprocessor or digital signal processor.

5.0 Analog Input

The equivalent circuit of the ADCS7476/77/78 input channel is shown in Figure 9. Diodes D1 and D2 provide ESD protection for the analog inputs. The analog input cannot exceed V+300 mV or GND-300 mV at any time, as these ESD diodes will start to conduct current to the substrate and affect the operation of the ADC.

The value of capacitor C1 in Figure 9 is typically 4pf, mainly due to pin capacitance. Resistor R1 represents the on-resistance of the multiplexer and track/hold switch, typically 100 ohms. Capacitor C2 is the ADCS7476/77/78 sampling capacitor, typically 26 pF.

The sampling nature of the analog input causes the input current to pulse, resulting in voltage spikes at the input. The ADCS7476/77/78 will provide the best performance when driven by a low impedance source to eliminate distortion caused by charging the sampling capacitor. In applications where dynamic performance is critical, it may be necessary to drive the input with a low output impedance amplifier. Additionally, when sampling AC signals with the ADCS7476/77/78, a bandpass or lowpass filter will reduce harmonics and noise, thereby improving THD and SNR.

6.0 Digital Inputs and Outputs

The ADCS7476/77/78 digital inputs (SCLK and CS) are not subject to the same absolute maximum ratings as the analog inputs. Instead, digital input pins are limited to +6.5V relative to GND, regardless of the supply voltage at V. This enables the ADCS7476/77/78 to interface with multiple logic levels independently of the supply voltage.

Note that even though the digital input is allowed to go up to +6.5V above GND, the digital output can only drive the V output. Additionally, digital input pins are not prone to latch-up; SCLK and CS can be asserted before V without any risk.

7.0 Operation Mode

The ADCS7476/77/78 has two possible modes of operation: normal mode and shutdown mode. When CS is pulled low, the ADCS7476/77/78 enters normal mode (and begins the conversion process). If CS is pulled high before the tenth falling edge of SCLK after CS is pulled low, the device will enter shutdown mode; if CS is held low, the device will remain in normal mode. Once in shutdown mode, the device will remain there until CS is lowered again. By changing the ratio of time spent in normal mode and shutdown mode, the system can trade off throughput and power consumption.

8.0 Normal Mode

The best throughput is obtained by keeping the ADCS7476/77/78 in normal mode all the time, so there is no power-up delay. In order for the device to remain in normal mode, CS must be held low until after the 10th falling edge of SCLK after the conversion begins (remember, the conversion is started by lowering CS).

If CS goes high after the 10th falling edge, but before the 16th, the device will remain in normal mode, but the current conversion will abort and SDATA will return to tri-state (truncated output word).

It takes 16 SCLK cycles to read all conversion words from the device. After 16 SCLK cycles, CS can idle high or low until the next conversion. If CS is at low idle, it must be turned up again before the next transition starts when CS is turned down again. After 16 SCLK cycles, SDATA returns to tri-state. At t quiet pass to lower the CS value again, which has passed.

9.0 Shutdown Mode

Shutdown mode is suitable for applications that do not sample continuously or are willing to trade throughput for power consumption. When the ADCS7476/77/78 is in shutdown mode, all analog circuits are turned off.

To enter shutdown mode, a conversion must be interrupted by returning CS high at any time between the second and tenth falling edges of SCLK, as shown in Figure 10. When CS is raised in this way, the device will enter shutdown mode; the current conversion will be aborted and SDATA will be tri-stated. If CS goes high before the second falling edge of SCLK, the device does not change modes; this is to avoid accidentally changing modes due to noise on the CS line.

10.0 Exit Shutdown Mode

To exit shutdown mode, turn CS down. Once CS is brought low, the ADCS7476/77/78 will begin to power up. Power up typically takes 1 microsecond. This microsecond power-up delay makes the first conversion result unavailable. This, however, is valid for the second conversion performed after power-up, as shown in Figure 11.

If CS is at SCLK, the device will return to shutdown mode. Done to avoid accidentally entering normal mode with noise on the CS line. To exit shutdown mode and remain in normal mode, CS must be held low until the 10th falling edge of SCLK. The ADCS7476/77/78 will power up after exactly 16 SCLK cycles.

11.0 Power-on time

The ADCS7476/77/78 typically takes 1 microsecond to power up, after the first use of VDD, or after returning to normal mode in shutdown mode. This is equivalent to any SCLK frequency specification in this document. After the first fake scam-version, ADCS7476/77/78 will perform the conversion attribute-early. Note that the tQUIET time must still be included in the first dummy transition and the second valid transition.

12.0 Boot Mode

When the V supply is first applied, the ADCS7476/77/78 can be powered up in either of two modes: normal or shutdown. Therefore, a dummy conversion should be performed after startup, as described in Section 11.0. The part can then be placed into normal mode or shutdown mode, as described in Sections 8.0 and 9.0.

13.0 Power Management

When the ADCS7476/77/78 operates continuously in nor-mal mode, the throughput can reach 1 MSPS. This user can perform fewer conversions per unit time by simply putting the ADCS7476/77/78 into shutdown mode between drives - SIENS. This approach is unfavorable throughput above 350 kSPS. The relationship between maximum power consumption and throughput is shown in Figure 12 below. Calculate power consumption - for a given throughput, keep in mind that every time you exit shutdown mode and enter normal mode, a dummy needs to be converted. Generally, the user will put the part into normal mode, perform a dummy transformation through a valid transformation, and then put the part back into off mode. When done, a fraction of the time spent in normal mode can be multiplied by the throughput (samples per second) by 2 microseconds, the time it takes to perform a dummy and a valid conversion. The power can then be consumed by multiplying the normal mode power by the time spent in normal mode. When the part is inside, the energy is dissipated and the shutdown mode is negligible.

For example, to calculate power consumption at 300 kSPS at V=5V, first calculate the fraction of time spent in normal mode: 300000 samples/sec 2 microseconds = 0.6, or 60%. Power consumption at 300 kSPS is 60% of 17.5 mW (maximum power consumption at V=5V), or 10.5 MW.

physical size