The HFA1135 is a high-speed, low-power current feedback built-in Intersil proprietary complementary amplifier bipolar UHF-1 process. This amplifier features user programmable output limits via the VH and VL pins. The HFA1135 is ideal for high-speed, low-power applications that require output constraints (such as flash A/D drives), especially those requiring fast overspeed recovery times. This limit function allows the designer to set the maximum value and protect the downstream water level from damage or input saturation. Sub-nanosecond overspeed recovery time ensures fast recovery of linear operation in overspeed conditions. Component and composite video systems also benefit from the performance of this op amp, such as gain flatness, differential gain and phase specification. The HFA1135 is a low power, high performance CLC501 and CLC502

200224134853.png" />

feature

User programmable output voltage limits fast overspeed recovery. <1ns low supply current. 6.8mA high input impedance. 2 million ohms wide -3dB bandwidth. 360 MHz very fast slew rate. 1200 V/µs gain flatness (to 50MHz). 0.07dB differential gain. 0.02% difference. 0.04 degree pin-compatible upgrade to CLC501 and CLC502 Provides lead-free plus annealing (RoHS compliant)

application

Flash A/D Drive

high resolution monitor

Professional Video Processing

Video Digitizer Board/System

multimedia system

RGB preamplifier

medical imaging

Handheld and Miniature RF Devices

battery powered communication

Absolute Maximum Ratings TA=25 oC Thermal Information Voltage between V+ and V-. 11 VDC input voltage. V Power Differential Input Voltage. 8 volt output current (Note 1). Short circuit protection 30mA continuous 60mA ≤ 50% duty cycle ESD rating. > 600V

operating conditions

temperature range. -40 to 85 degrees Celsius Thermal Resistance (Typical, Note 1) θJA (o C/W) SOIC package. 165

Maximum connection temperature (die only). 175 degrees Celsius

Maximum Junction Temperature (Plastic Packaging). 150 degrees Celsius

Maximum storage temperature range. -65 degrees Celsius to 150 degrees Celsius

Maximum lead temperature (10s for soldering). 300 degrees Celsius (SOIC - lead only)

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Installation under the above or any other conditions stated in the operating section of this specification is not implied.

Note:

1. θJA is measured in free air with components mounted on an inefficient thermal conductivity test board.

Electrical Specifications V Power = ±5V, AV = +1, RF = 510Ω (Note 3), RL = 100Ω, unless otherwise specified

Electrical Specifications V Power = ±5V, AV = +1, RF = 510Ω (Note 3), RL = 100Ω, unless otherwise specified (continued)

notes:

2. Test level: A. Product testing; B. Typical or guaranteed limits based on characteristics; C. Typical design for reference only.

3. The optimum feedback resistance of HFA1135 when V=+1 is 1.5kΩ. The production test parameters are tested with RF=510Ω because the HFA1135 and the HFA1105 amplifier share the test hardware.

4. When the output signal fluctuates below GND (e.g., 0.5V PP), undershoot dominates, resulting in a higher overshoot limit compared to V OUT = 0V to 0.5V

condition. See the Application Information section for details.

5. See typical performance curves for details.

6. If the output swings below GND (such as a bipolar signal), the swing rate is asymmetric. The positive unipolar output signal has symmetrical positive and negative slew rates comparable to the +SR specification. See the Application Information section and Impulse Response Graphs for details.

Application Information Related Application Instructions

The following application instructions apply to HFA1135:

AN9653 Use and Application of Output Limiting Amplifiers AN9752 Sync Stripper and Sync Inserter Synthesis Video AN9787 An Intuitive Way to Understand Current Feedback Amplifiers AN9420 Current Feedback Amplifier Theory and

application

AN9663 Conversion from Voltage Feedback to Current Feedback Amplifier Optimal Feedback Resistors Although the bandwidth of a current feedback amplifier is not as dependent on closed-loop gain as a voltage feedback amplifier, there can be a considerable reduction in bandwidth at higher gains. This reduction may utilize the current feedback to minimize the unique relationship of amplifier bandwidth to radio frequency. All current-feedback amplifiers require a feedback resistor, even for unity-gain applications, and RF, combined with an internal compensation capacitor, sets the dominant-pole frequency response. Therefore, the bandwidth of the amplifier is inversely proportional to RF. The HFA1135 is designed to be optimized for 250ΩRF at a gain of +2. Decreasing RF reduces stability, causing excessive peaking and overshoot (note: capacitive feedback will cause problem frequencies due to reduced feedback impedance). The higher the gain, the more stable the amplifier is, so in the bandwidth stability tradeoff, RF can be reduced. The following table lists the recommended RF values, and the expected bandwidth for various closed-loop gains

Non-inverting input source impedance For optimum operation, the DC source impedance from the non-inverting input should be ≥ 50Ω. Especially important is the inverting gain configuration - the inverting input is usually directly grounded. Pulse undershoot and asymmetric slew rate The HFA1135 uses a quasi-complementary output stage to achieve high output current supply current while minimizing quiescent current. In this approach, a composite device replaces the traditional PNP pull-down transistor. This composite device switches modes after crossing 0V, resulting in additional distortion of the wobble signal below ground, and the undershoot on the negative adds a portion of the output waveform (see Figures 9, 13 and 17). For small bipolar signals, this undershoot does not exist, or for large positive signals. Another artifact device is an asymmetric slew rate output signal with a negative voltage component. When the output signal crosses 0V (see Figures 9, 13 and 17), the overall negative slew rate is slowed down. Positive-only signals have symmetrical slew rates, as shown in the large-signal positive impulse response plots (see Figures 7, 11, and 15). PC Board Layout The frequency response of this amplifier is largely dependent on the care taken when designing the PC board. Using low inductive components like chip resistors and chip capacitors is highly recommended, while a solid ground is a must! Care should be taken to disconnect the power supply. Large value (10µF) tantalum parallel with small value tantalum (0.1µF) chip capacitors work well in most cases. It is recommended that the input and output of the device. Capacitance directly at the output must be minimized or isolated, as described in the next section.

Care must also be taken to reduce the capacitor to ground (-IN) at the inverting input of the amplifier, as shown below the capacitor causes gain peaking, pulse overshoot, and is large enough to be unstable. To reduce capacitance designers should remove traces under the ground plane connected to -IN, and keep the connection to -IN as short as possible. An example of a good high frequency layout is the evaluation board shown in Figure 2. Driving capacitive loads Capacitive loads, such as A/D inputs, or terminating transmission lines reduce the amplifier's phase leading to margin oscillations in the frequency response peaks. In most cases, the oscillation can pass through the capacitor. Figure 1 details the selection of this resistor. The points on the curves represent the RS and CL optimal bandwidth, stability, and settling time, but experimental fine-tuning is recommended. Selecting a point above or to the right of the curve will produce an overdamped response, while points below or to the left of the curve show areas of insufficient damping performance. RS and CL form a low-pass network at the output, thus limiting the system bandwidth well below the amplifier bandwidth of 660 MHz (AV=+1). When CL increases and decreases RS as shown in the curve), the maximum bandwidth is obtained without sacrificing stability. Still, the bandwidth decreases with increasing load capacitance. For example, at V=+1, RS=50Ω, CL=20pF, the total bandwidth is 170MHz, but at AV=+1, RS=10Ω, CL=330pF.

The performance of the HFA1135 can be determined using the HFA11XX Evaluation Board (part number HFA11XXEVAL). Please contact your local sales office for information. When evaluating this amplifier at a gain of +2, the two 510Ω gain setting resistors on the evaluation board should be changed to 250Ω. The layout and schematic diagram of the circuit board are shown in Figure 2. NOTE: SOIC versions are available in DIP boards by using SOIC dip adapters such as Aries Electronics part number 08-350000-10.

General operating limits

The HFA1135 has a user-programmable output clip to limit the output voltage excursion. The limit action is amplified by applying a voltage to the VH and VL terminals (pins 8 and 5). VH sets the output upper limit, while VL sets the lower limit level. If the amplifier attempts to drive the output above VH or below VL, the clamp circuit limits the output voltage to VH or VL, respectively (± limit accuracy). The low input bias current of this limit pin allows driving from simple resistive divider circuits or active components such as amplifiers or digital-to-analog converters. Limit Circuit Figure 3 shows a simplified schematic stage and high limit (VH) circuit of the HFA1135 input. As with all current feedback amplifiers, there is a unity gain buffer (Q X1-Q X2) between the positive and negative inputs. This buffer force - input tracks + input and sets the following slew current: I SLEW = (V - IN - V OUT )/RF + V -IN /RG

This current passes through

Q X3-Q X4, where it is converted to a voltage and fed to the output through another unity gain buffer. If no restrictions are used, the high impedance node may swing within the limits specified by Q P4 and Q N4. Note that when the output reaches a quiescent value, the inflow current is reduced to only a small current (-I bias) required to maintain the output final voltage. Tracing the path from VH to Z illustrates the effect of the limit on the voltage on the high impedance node. VH drops 2V BE (Q N6 and Q P6) sets the base voltage on Q P5. Question 5 When the high impedance node reaches a voltage equal to the base voltage of Q P5 + 2V BE (qp5) and question 5). Therefore, Q P5 limits node Z when Z reaches VH. R1 provides a pull-up network to ensure the limit input floats. A similar description applies to a VL-controlled symmetrical low-limit circuit. When the output is limited, the negative input continues to source a slewing current (I-limit) in an attempt to force the output to a quiescent voltage defined by the input. Question 5 must sink this current when limiting, because the -IN current is always mirrored on the high impedance node. This limit current is calculated as: I LIMIT = (V -IN - V OUT LIMITED )/RF + V -IN /RG For example, a unity gain circuit, V IN = 2V, VH = 1V, there will be I limit = (2V-1V )/1.5kΩ+2V/∞=667µA (RG=∞ for unity gain applications). Note that ICC increases I LIMIT when output is limited.

ultimate accuracy

The limiting output voltage will not be exactly equal to the voltage applied on VH or VL. Offset errors, mainly caused by VBE mismatches, require a limit accuracy parameter to be found in the device specification. Limit accuracy is the effect of limit conditions. Referring back to number 3, it can be seen that one component of the ultimate accuracy is the voltage mismatch between the Q X6 transistor and the Q X5 transistor. If the transistors always run at the same current level there will be no V-be mismatch and no contribution inaccuracies. The QX6 transistors are biased to constant current, but equal to the I limit through QX5 as previously described. Increase by my limit increases, resulting in limited output voltage increases well. Limit is a function of overdrive ((AV x V IN - V limit)/V limit), so limit accuracy is reduced as overdrive is increased. For example, the accuracy decreases when the overdrive is from 100% to 200% (AV=+2, VH=500mV, RF=250Ω). The fact that voltage has an effect on the linearity of the amplifier must also be taken into account. The "Linear "Near Limit Voltage" curves, Figures 34 and 35, illustrate the effect of several limit levels on linearity. The limit range differs from some competitor devices in that both VH and VL can use a range that spans 0V. While VH Must be greater than VL, both can be positive or negative, within the limits indicated in the range specification. For example the HFA1135 can be limited to ECL output levels by setting VH=-0.8V and VL=-1.8V. VH and VL can be Connect to the same voltage (eg GND), but the result will not be the DC output voltage of the AC input signal. The 150mV-200mV output will still have the AC signal.

Resuming from overdrive as long as the overspeed condition remains. When the input voltage falls below overdrive (V limit/AV), the amplifier returns to linear operation. A delay, called the overdrive recovery time, is required for this linear recovery. Overdrive recovery time is defined as the difference between the amplifier's propagation delay limit and the amplifier's normal propagation delay overdrive. Figure 36 details the overdrive recovery time for various limit and overdrive gears. The benefits of limiting output The "unlimited impulse response" and "impulse" graphs "limited response" (Figures 4 and 5) highlight the advantages of output limiting. In addition to the obvious benefit of limiting the output swing to a defined range, limiting the output excursion Also saturates the output transistor, preventing unwanted saturation artifacts from distorting the output signal. The output limit also takes advantage of the HFA1135's superfast overspeed recovery time, reducing the recovery time from 2.3ns to 0.3ns, based on the amplifier's normal propagation delay of 1.2 ns.

Typical Performance Curves V Supply = ±5V, TA = 25 oC, RF = Value from Optimum Feedback Resistor Table, RL = 100Ω, unless otherwise specified

Typical performance curve V power supply = ±5V, TA = 25 oC, RF = value

Typical Performance Curves V Supply = ±5V, TA = 25 oC, RF = Value from Optimum Feedback Resistor Table, RL = 100Ω, unless otherwise specified (continued)

Typical Performance Curves V Supply = ±5V, TA = 25 oC, RF = Value from Optimum Feedback Resistor Table, RL = 100Ω, unless otherwise specified (continued)