feature

High integration: 32-channel DAC in 1212 mm² LFBGA; guaranteed monotonicity; DSP/microcontroller compatible serial interface; channel update rate 1.1 MHz; output impedance 0.5; selectable output voltage 0 V to 5 V or - 2.5 V to +2.5 V asynchronous reset device; temperature range -40 C to +85 C.

application

Optical networking; level setting; instrumentation; automatic test equipment; industrial control systems; data acquisition; low-cost I/O.

General Instructions

The AD5532HS is a 32-channel voltage output 14-bit DAC with a high-speed serial interface. Selected DAC registers are written over the 3-wire interface. The serial interface operates at clock frequencies up to 30 MHz and is compatible with digital signal processor and microcontroller interface standards. The output voltage range is 0 V to 5 V or -2.5 V to +2.5 V, determined by the offset voltage at OFFS_ on the pin. It is limited to the range of V+2 V to V–2 V due to the headroom of the output amplifier.

The device operates at AV = 5 V ± 5%, DV = 2.7 V to 5.25 V, V = -4.75 V to -12 V and V = +4.75 V to +12 V and requires the reference voltage to stabilize at 2.5 V.

Product Highlights

1. 32 14-bit DACs in one package to ensure monotonicity.

2. The AD5532HS is packaged in a 74-ball LFBGA with a body size of 12 mm x 12 mm.

AC Characteristics (VDD=+4.75 V to +12 V, VSS=-4.75 V to -12 V; AVCC=4.75 V to 5.25 V; DVCC=2.7 V to 5.25 V; AGND=DGND=DAC_GND=0 V; REF_IN= 2.5 V; all outputs are unloaded. All specifications TMIN to TMAX unless otherwise noted.)

notes

1. See terminology;

2. Guaranteed by design and characteristics, without production testing;

3. Type B: Industrial temperature range -40°C to +85°C;

4. Start timing from the end of the write sequence. Specifications are subject to change without notice.

Timing Characteristics (VDD=+4.75 V to +12 V, VSS=-4.75 V to -12 V; AVCC=4.75 V to 5.25 V; DVCC=2.7 V to 5.25 V; AGND=dgd=DAC_GND=0 V; all specifications TMIN to TMAX unless otherwise noted.)

notes

1. See the timing diagram in Figure 1.

2. Guaranteed by design and features, no production testing.

3. The specified value of all input signals is t=t=5ns (10% to 90% of DV) and starts timing from the voltage level of (V+V)/2. Specifications are subject to change without notice.

the term

Integral Nonlinearity (INL)

A measure of the maximum deviation of a straight line through the endpoints of the DAC transfer function. It is expressed as a percentage of full scale.

Differential Nonlinearity (DNL)

The difference between the measured change and the ideal 1lsb change between any two adjacent codes. The specified DNL maximum is ±1 LSB, ensuring monotonicity.

offset error

With all 0s loaded into the DAC, measure the error present in the output of the device. It includes the offset of the DAC and output amplifier. Expressed in mV.

full scale error

Measurement of output error when all 1s are loaded into the DAC. Ideally, if off-IN=0, the output should be 2 REF-IN. It is expressed as a percentage of full scale.

DC Power Supply Rejection Ratio (PSRR)

A method of measuring changes in analog output as supply voltages (V and V) change. Expressed in decibels. V and V variation is ±5%.

DC crosstalk

A dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output changes of all other DACs. Expressed in microvolts.

Output temperature coefficient

A method of measuring the change in analog output with temperature. Expressed in ppm/°C.

Output voltage settling time

The time from the last data bit entering the DAC until the output settles to within ±0.5LSB of its final value.

Digital-to-analog fault pulse

The fault area injected into the analog output when the code in the DAC register changes state. It is specified to convert in major carry (011.11 to 100.00 or 100.00 to 011.11) Yes.

digital crosstalk

When a full-scale code change (all 1s to all 0s, and vice versa) is written to the other DAC, a glitch pulse is transmitted to the output of one DAC in mid-scale. It is expressed in nV secs.

Analog crosstalk

Transfer to one DAC resulting from a full-scale change in the output (V) of the other. The fault area is expressed in nV secs.

digital feedthrough

Measurement of the pulses injected from the digital control input into the analog output when the part is not written, i.e. when the synchronization is high. It is specified in nV secs and is measured on a digital input pin with a worst-case change, e.g. from 0 to 1 and vice versa.

Output Noise Spectral Density

A method of measuring internally generated random noise. Random noise is characterized by its spectral density (voltage per root Hertz). It is measured by loading all DACs to midscale and measuring the noise at the output. The unit of measurement is nV/√Hz.

Typical Performance Characteristics - AD5532HS

Function description

The AD5532HS contains 32 DACs in one package. The 14-bit digital word is loaded into one of 32 DAC registers via the serial interface. It is then converted (with gain and offset) to an analog output voltage (V0–V31).

To update the output voltage of the DAC, the required DAC is addressed through the serial port. The selected DAC converts the code after loading the 5-bit DAC address and 14-bit DAC data. At power up, all DACs are loaded with zeros.

Digital-to-analog conversion part

The structure of each DAC channel consists of a resistor string DAC and an output buffer amplifier. The voltage at the REF_IN pin provides the reference voltage for the cor response DAC. Since the input encoding of the DAC is straight binary, the ideal DAC output voltage is given by:

where D = the decimal equivalent of the binary code loaded into the DAC register, 0–16383.

Output buffer stage gain and offset

The function of the output buffer stage is to convert the DAC output from 0 V to 2.5 V with a wider range. This is done by tripling the output of the DAC and offsetting the voltage by the voltage in the pin on off.

VDAC is the output of the DAC.

VOFFS_-IN is the voltage at OFFS_ in the pin.

Table 1 shows the relationship between the output voltage range and the user-supplied bias voltage.

VOUT is limited only by the headroom of the output amplifier.

VOUT must be within the maximum ratings.

Reset function

The reset function on the AD5532HS can be used to reset all nodes on the device to a power-on reset state. All dacs are loaded with 0 and all registers are cleared. The reset function is achieved by driving the reset pin low.

serial interface

The serial interface is controlled by three pins as follows:

SYNC: This pin is the frame synchronization pin of the serial interface.

SCLK: This pin is the serial clock input. It operates at a clock frequency of up to 30 MHz.

DIN: This pin is the serial data input. Data must be valid on the falling edge of SCLK.

To update a single DAC channel, a 19-bit data word is written to the AD5532HS. See Table 2.

A4–A0 bits

Used to address any of the 32 channels (A4=MSB of address, A0=LSB).

DB13–DB0 bits

They are used to write 14-bit words to the addressed DAC registers.

Figure 1 shows the timing diagram for a serial write to the AD5532HS. The serial interface can work with both continuous and non-continuous serial clocks. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift register. Any other edges while synchronizing are ignored until the correct number of bits is shifted in or out. Once 19 bits are shifted in or out, SCLK will be ignored. For another serial transfer, the counter must be reset by a synchronous falling edge. The user must allow a time interval of 280 ns (min) between two consecutive writes (see timing specifications).

Microprocessor interface AD5532HS-to-ADSP-21xx interface

The ADSP-21xx family of DSPs is easy to interface with the AD5532HS without additional logic.

After motion is enabled, data transfer is initiated by writing a word to the Tx register. During the write sequence, data is clocked to the AD5532HS on each rising edge of the DSP serial clock and on the falling edge of SCLK. The easiest way to provide the 19-bit data words required by the AD5532HS is to send two 10-bit data words from the ADSP-21xx. Make sure the data is positioned correctly in the TX register so that the first 19 bits sent contain valid data. The settings of the motion control registers are as follows:

TFSW=1, alternate frames;

INVTFS=1, valid low frame signal;

DTYPE=00, right-aligned data;

ISCLK=1, internal serial clock;

TFSR=1, every word frame;

ITFS=1, internal frame signal;

SLEN=1001, 10-bit data word.

Figure 3 shows the connection diagram.

AD5532HS-to-MC68HC11 interface

The Serial Peripheral Interface (SPI) on the MC68HC11 is configured in master mode (MSTR=1), clock polarity bit (CPOL)=0 and clock phase bit (CPHA)=1. SPI is configured by writing to the SPI Control Register (SPCR) - see the 68HC11 User Manual. The SCK of the 68HC11 drives the SCLK of the AD5532HS, while the MOSI output drives the serial data line (DIN) of the AD5532HS. The sync signal comes from the port line (PC7). When data is sent to the AD5532HS, the sync line is taken low (PC7). Data displayed on the MOSI output is valid on the falling edge of SCK. The 68HC11 transfers only 8 bits of data during each serial transfer operation; therefore, three consecutive write operations are required to transfer 19 bits of data. The data MSB is transferred first. Be sure to left-justify the data in the SPDR register so that the first 19 bits of the transfer contain valid data. PC7 must be pulled low to start the transfer. It is pulled high and pulled low again before any further write cycles occur. See Figure 4.

AD5532HS-to-PIC16C6x/7x interface

The PIC16C6x/7x Synchronous Serial Port (SSP) is configured as an SPI master with the clock polarity bit set to 0. This is done by writing to the Synchronous Serial Port Control Register (SSPCON). Please refer to the User's PIC16/17 Microcontroller User's Manual. In this example, I/O port RA1 is used for pulse synchronization and enables the serial port of the AD5532HS. The microcontroller transfers only 8 bits of data during each serial transfer operation; therefore, three consecutive write operations are required to transfer 19 bits of data. The data MSB is transferred first. Be sure to left-justify the data in the SPDR register so that the first 19 bits of the transfer contain valid data. RA1 must be pulled low to start the transfer. It is pulled high and pulled low again before any further write cycles occur. Figure 5.

AD5532HS-to-8051 interface

The AD5532HS requires a clock that is synchronized with the serial data. Therefore, the 8051 serial interface must operate in mode 0. In this mode, serial data is exited from 8051 to RxD and a shift clock is output on TxD. The sync signal comes from the port line (P1.1). Figure 6 shows how the 8051 is connected to the AD5532HS. Since the AD5532HS shifts out data on the rising edge of the shift clock and latches the data on the falling edge, the shift clock must be inverted. Also note that the AD5532HS needs its data with the MSB first. Because the 8051 outputs the LSB first, the transmit routine must take this into account.

Application circuit

AD5532HS in Optical Network Control Loop

The AD5532HS can be used in optical networking applications that require a large number of DACs to perform control and measurement functions. In the circuit shown in Figure 7, the 0 V–5 V output of the AD5532H is amplified to 0 V–180 V and then used to control the driver to position the MEMS mirror in the optical switch. The exact position of each mirror is measured with sensors. The sensor readings are modulated using four dual 4-channel matrix switches (ADG739) and fed back to an 8-channel 14-bit ADC (AD7856).

The control loop is driven by the ADSP-21065L, which is a 32-bit SHARC digital signal processor with an SPI-compatible motion interface. It writes data to the DAC, controls the multiplexer, and reads data from the ADC via the 3-wire serial interface.

Alternatively, the AD5532HS can be driven by the ADMC401 motor controller, as shown in the control loop in Figure 8. The DAC outputs are fed into eight AD8534 quad-transconductance amplifiers to generate currents for the voice coil actuators that determine the position of the rearview mirror. The exact position of each mirror is measured and the readings are mixed into the ADMC401's on-chip 8-channel ADC.

AD5532HS in a typical ATE system

The AD5532HS is ideal for use in automated test equipment. Several DACs are required to control pin drivers, comparators, active loads and signal timing. Traditionally, a sample and hold device is used in this application.

The AD5532HS has the following advantages: no refresh, no droop, elimination of pedestal errors, and no additional filtering to eliminate glitches. Achieve higher levels of integration in smaller areas (see Figure 9).

Power decoupling

In any circuit where accuracy is important, careful consideration of power and ground return layout helps ensure rated performance. The printed circuit board on which the AD5532HS is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5532HS is in a system where multiple devices require an AGND to DGND connection, the connection should be made at only one point. The star ground point should be as close as possible to the device. For power supplies with multiple pins (V, V, AV), it is recommended to connect these pins together. The AD5532HS should have adequate supply bypassing of 10µF in parallel with 0.1µF on each supply, each as close to the package as possible, ideally close to the device. The 10µF capacitors are of the tantalum bead type. The 0.1µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like common ceramic types that provide a high frequency, low impedance path to ground to handle transient currents from internal logic switches.

The power supply lines to the AD5532HS should use as large traces as possible to provide a low impedance path and reduce the effect of faults on the power supply lines. Fast switching signals such as clocks should use a digital ground shield to avoid radiating noise to other parts of the board and must not run near the reference input. A ground wire routed between the D and SCLK lines will help reduce crosstalk between them (not needed on multi-layer boards as there will be a separate ground plane, but separating the lines will help). Noise on REF_IN must be minimized. In avoiding the intersection of digital and analog signals. The traces on opposite sides of the board should be at right angles to each other. This reduces feedthrough effects through the board. Microstrip technology is by far the best, but not always possible with double sided. In this technique, the component side of the board is dedicated to the ground plane, while the signal lines are placed on the solder side.

As with all thin packages, during assembly, care must be taken to avoid buckling of the package and to avoid point loads on the surface of the package.

Dimensions

Dimensions are in inches and (mm).