feature

Single channel, 1024 position resolution 20 kΩ nominal resistance; calibrated 1% nominal resistance tolerance (resistance performance mode); varistor mode tempco: 35 ppm/°C; voltage divider tempco: 5ppm/°C; single supply operation : 9 V to 33 V dual supply operation: ? 9 V to ? 6.5 V SPI compatible serial interface wiper setting readback.

application

Mechanical potentiometer replacement; instrumentation: gain and offset adjustment; programmable voltage-to-current conversion; programmable filters, delays, and time constants; programmable power supplies; low-resolution DAC replacement; sensor calibration.

General Instructions

The AD5293 is a single-channel 1024-bit digital potentiometer with less than 1% end-to-end resistance error. The AD5293 features the same electronic adjustment as a mechanical potentiometer with higher resolution, solid-state reliability, and superior low temperature coefficient performance. The device is capable of high voltage operation and supports dual-supply operation from ±10.5 V to ±15 V and single-supply operation from 21 V to 30 V.

1. In this data sheet, the terms digital potentiometer and RDAC are used interchangeably.

The AD5293 offers an industry-leading low resistance tolerance error guaranteed to ±1% with a nominal temperature coefficient of 35 ppm/°C. The low resistance tolerance feature simplifies open loop applications as well as precision calibration and tolerance matching applications.

The AD5293 is a compact 14-lead TSSOP package. The part is guaranteed to operate over an extended industrial temperature range (from -40°C to +105°C).

Interface Timing Specification

VDD=VSS=±15 V, VLOGIC=2.7 V to 5.5 V, and 8722 ; 40°C

1. All input signals are specified with tR=tF=1ns/V (10% to 90% of VDD) and start timing from the voltage level of (VIL+VIH)/2.

2. Maximum SCLK frequency = 50 MHz.

3. Refer to t12 and t13 for RDAC register command operation. 4 RPULL_UP=2.2 kΩ to VLOGIC with a capacitive load of 168 pF. 5 Typical supply voltage conversion rate of 2 ms/V.

Timing diagram

Absolute Maximum Ratings

TA = 25°C unless otherwise noted.

1. The maximum terminal current is handled by the maximum current of the switch, the maximum power dissipation of the package, and the maximum-maximum voltage applied across any two of the A, B, and W terminals for a given resistance.

2. d = pulse duty cycle.

Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions described in the operating section of this specification or any other conditions above is not implied. Long-term exposure to absolute maximum rating conditions may affect device reliability.

Thermal resistance

θJA is specified for worst-case, devices soldered in circuit boards intended for surface mount packages.

1. JEDEC 2s2p test board, still air (airflow from 0 m/sec to 1 m/sec).

Typical performance characteristics

test circuit

Figures 26 to 31 define the test conditions used in the specification section.

theory of operation

The AD5293 digital potentiometer is designed as a true variable resistor for the analog signal, the analog signal is held at VSS

serial data interface

The AD5293 includes a serial interface (SYNC, SCLK, DIN, and SDO) that is compatible with the SPI standard and most DSPs. The device allows data to be written to each register via SPI.

Shift Register

The AD5293 shift register is 16 bits wide (see Figure 2). A 16-bit data word consists of two unused bits set to 0, followed by four control bits and 10 RDAC data bits. Data is loaded MSB first (bit DB15). Four control bits determine the function of the software command (see Table 8). Figure 3 shows a timing diagram for a typical write sequence.

Pull the sync line low at the beginning of the write sequence. The sync pin must be held low until a complete data word is loaded from the DIN pin. When SYNC returns high, the serial data word is decoded according to the instructions in Table 8. The command bit (Cx) controls the operation of the digital potentiometer. The data bits (Dx) are the values loaded into the decode register. The AD5293 has an internal counter that counts multiples of 16 bits (per frame) for proper operation. For example, the AD5293 can handle 32-bit words, but not 31-bit or 33-bit words correctly. The AD5293 does not require a continuous SCLK, and when synchronization is high, all interface pins should operate close to the power rails to minimize power consumption in the digital input buffers.

RDAC register

The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with all 0s, the wiper is connected to terminal B of the variable resistor. The RDAC register is a standard logic register; there is no limit to the number of changes allowed. The RDY pin can be used to monitor the completion of a write or read to the RDAC register. The AD5293 is preset to midscale at power-up.

write protection

At power-up, the serial data input register write command to the RDAC register is disabled. The RDAC write-protect bit C1 of the control register (see Table 9 and Table 10) is set to 0 by default. This disables any changes to the contents of the RDAC register regardless of software commands, except that the RDAC register can be refreshed to midscale using a software reset command (Command 3, see Table 8) or through hardware using the reset pin. To enable programming of the variable resistor wiper position (program the RDAC register), the write-protect bit C1 of the control register must first be programmed. This is accomplished by loading the serial data input register with command 4.

Basic operation

The basic mode of setting the variable resistor wiper position (programming the RDAC register) is accomplished by loading the serial data input register with Command 1 (see Table 8) and the desired wiper position data. The RDY pin can be used to monitor the completion of this RDAC register write command. Command 2 can be used to read the contents of the RDAC register (see Table 8). After issuing the readback command, the RDY pin can be monitored to indicate when data can be read on SDO in the next SPI operation. Instead of monitoring the RDY pin (see Table 3), minimal latency can be achieved when executing a write or read command. Table 7 provides an example listing of serial data input (DIN) word sequences, serial data output appearing on the SDO pin in hexadecimal format for reading and writing to the RDAC.

shutdown mode

The AD5293 can be put into shutdown mode by executing a software shutdown command (see Command 6 in Table 8) followed by setting the LSB to 1. This feature puts the RDAC in a special state where terminal a is open and wiper W is connected to terminal B. Entering shutdown mode, the contents of the RDAC register remain unchanged. However, in shutdown mode, all commands listed in Table 8 are supported.

reset

A low-to-high transition of the hardware reset pin will load the RDAC register with midscale. The AD5293 can also be reset by software by executing Command 3 (see Table 8). Restore control registers with default settings (see Table 10).

Resistor Performance Mode

This mode activates a new, patented 1% end-to-end resistance tolerance, ensuring a resistance tolerance of ±1% on each code, i.e. code = half scale, RWB = 10 kΩ ± 100Ω. See Table 2 to verify which codes achieve ±1% of the resistance tolerance. The resistor performance mode is activated by programming bit C2 of the control register (see Table 9 and Table 10). Typical settling times are shown in Figure 23.

Daisy Chain Operation

The serial data output pin (SDO) serves two purposes. It can read the contents of the wiper settings using Command 2 (see Table 8), and can also be used to daisy-chain multiple devices.

The remaining instructions are valid for daisy-chaining of multiple devices in simultaneous operation. Daisy chaining minimizes the number of port pins required to control the IC.

The SDO pin contains an open-drain N-channel FET that requires a pull-up resistor if this feature is used. As shown in Figure 32, the SDO pins of one package must be connected to the DIN pins of the next package. Users may need to increase the clock period because pull-up resistors and capacitive loads at the SDO/DIN interface may require additional time delays between subsequent devices.

When two AD5293 devices are daisy-chained, 32 bits of data are required. The first 16 bits go into U2, and the last 16 bits go into U1. The sync pins should be held low until all 32 bits are in their respective serial registers. Then pull the sync pin high to complete the operation.

RDAC Architecture

For the best cost performance, Analog Devices patented the RDAC segment structure for all digital potentiometers. In particular, the AD5293 employs a three-stage segmentation method, as shown in Figure 33. The AD5293 wiper switch adopts a transmission gate CMOS topology, and the gate voltage is derived from VDD.

Variable Resistor Programming

Rheostat operation - 1% resistance tolerance

When there are only two terminals, the AD5293 operates in rheostat mode - NAL acts as a variable resistor. Unused terminals can be left floating or can be tied to the W terminal as shown in Figure 34.

The nominal resistance between Terminal A and Terminal B (RAB) is 20 kΩ, with 1024 tap points, accessible through the wiper terminals. The 10 bits of data in the RDAC latch are decoded to select one of 1024 possible wiper settings. The AD5293 includes an internal ±1% resistor tolerance calibration feature that can be enabled or disabled (enabled by default) through programming bit C2 of the control register (see Table 9 and Table 10).

The digitally programmed output resistances between the W and A terminals RWA and W and B terminals RWB are calibrated to give a maximum ±1% absolute resistance error over the entire supply and temperature range. Therefore, the general formula for determining the digitally programmed output resistance between the W and B terminals is:

where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register; RAB is the end-to-end resistance.

Similar to a mechanical potentiometer, the resistance of the RDAC between the W and A terminals also produces a digitally controlled complementary resistance, RWA. RWA is also calibrated to give a maximum 1% absolute resistance error. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equation for this operation is:

where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register; RAB is the end-to-end resistance.

Under zero-scale conditions, there is a finite total wiper resistance of 120Ω. Regardless of the setting for part operation, care should be taken to limit the current between the A and B terminals, between the W and A terminals, and between the W and B terminals to a maximum continuous current of ±3 mA or as specified in Table 4 pulse current. Failure to do so may result in degradation or damage to the internal switch contacts.

Program the Potentiometer Divider

Voltage output operation

A digital potentiometer easily generates a voltage divider proportional to the input voltage from a to B at the wiper-to-B terminal and the wiper-to-a terminal, as shown in Figure 35. Unlike the polarity of VDD to GND (which must be positive), the voltages between A to B, W to A, and W to B can be of any polarity.

If you ignore the effect of wiper resistance for simplicity, and connect the A terminal to 30 V and the B terminal to ground, an output voltage from 0 V to 30 V - 1 LSB will result from wiper W to terminal B. The LSB of each voltage is equal to the voltage applied across the A and B terminals divided by the 1024 positions of the potentiometer divider. For any effective input voltage applied to Terminal A and Terminal B, the general equation that defines the VW output voltage with respect to ground is:

To optimize the wiper position update rate in voltage divider mode, it is recommended to disable the internal ±1% resistor tolerance calibration feature via programming bit C2 of the control register (see Table 9 and Table 10).

Operation of the digital potentiometer in voltage divider mode results in more accurate overtemperature operation. Unlike in rheostat mode, the output voltage depends mainly on the ratio of the internal resistances RWA and RWB, not the absolute value. Therefore, the temperature drift is reduced to 5ppm/°C.

External capacitor

A 1µF capacitor to ground must be connected to the external cap pins during AD5293 power-up and throughout operation (see Figure 36). The voltage rating of this capacitor must be ≥7 V.

Terminal voltage operating range

The positive VDD and negative VSS supplies of the AD5293 define the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals that appear on the A, B, and W terminals in excess of VDD or VSS are clamped by internal forward-biased diodes (see Figure 37).

The ground pin of the AD5293 is primarily used as a digital ground reference. To minimize digital ground bounce, the AD5293 ground pin should be connected remotely to common ground. The digital input control signals to the AD5293 must be referenced to the device ground pin (GND) to meet the logic levels defined in the Specifications section.

Power up sequence

Because diodes limit the voltage compliance at the A, B, and W terminals (see Figure 37), VDD and VSS must be powered before any voltage is applied to the A, B, and W terminals. Otherwise, the diode is forward biased, allowing VDD and VSS to power up inadvertently. The ideal power-up sequence is GND, VSS, VLOGIC, VDD, digital inputs, then VA, VB, and VW. The order in which VA, VB, VW and digital inputs are activated is not important as long as they are shown in Figure 36. The hardware settings for the cover pins are VDD, VSS and VLOGIC.

Regardless of the power-up sequence and ramp rate of the power supplies, the power-up preset activates after VLOGIC is powered up, restoring midscale to the RDAC register.

application information

High Voltage DAC

The AD5293 can be configured as a high voltage DAC with output voltages up to 33V. The circuit is shown in Figure 38. The output is:

where is a decimal code between 0 and 1023.

Programmable Voltage Source with Boost Output

For applications that require high current regulation, such as laser diodes or tunable lasers, a boost power supply can be considered (see Figure 39).

In this circuit, the op amp's inverting input forces VOUT to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the power supply through the N-channel FET (U3). The N-channel FET power handling must be sufficient to dissipate (VIN-VOUT) × IL power. The circuit can be powered from a 33V supply with a maximum current of 100mA.

High-precision digital-to-analog converter

The AD5293 can be configured as a high precision DAC by optimizing the resolution of the device within a specific reduced voltage range. This is accomplished by placing external resistors on either side of the RDAC, as shown in Figure 40. The improved ±1% resistor tolerance specification greatly reduces errors associated with discrete resistor matching.

Variable Gain Instrumentation Amplifier

As shown in Figure 41, the AD8221, together with the AD5293 and ADG1207, make an excellent instrumentation amplifier for data acquisition systems. The data acquisition system has the characteristics of low distortion and low noise, and can condition the signal before various analog-to-digital converters.

The gain can be calculated using Equation 6 as follows:

Audio volume control

The AD5293's excellent THD performance and high voltage performance make it ideal for digital volume control. The AD5293 is used as an audio attenuator; it can be connected directly to a gain amplifier. A large step change in volume level at any time can cause a sudden interruption of the audio signal, resulting in audible zipper noise. To prevent this, a zero-crossing window detector can be inserted on the sync line to delay device updates until the audio signal crosses the window. Because the input signal can operate at any DC level, not an absolute 0V level, a zero crossing in this case means that the signal is AC coupled, and the DC offset level is the zero reference point for the signal.

Figure 42 shows the configuration for reducing zipper noise, and Figure 43 shows the results of using this configuration.

The input is AC coupled by C1 and attenuated before the input to a window comparator formed by U2, U3, and U4B. U6 is used to establish the signal as zero reference. The upper limit of the comparator is set above its offset, so in this example the output pulses high whenever the input is between 2.502v and 2.497v (or 0.005v window). This output is used with the chip select signal so that the AD5293 updates when the signal crosses the window. To avoid constant updates of the device, the chip select signal should be programmed with two pulses, not one.

In Figure 43, the lower trace shows that the volume level changes from quarter to full scale as the signal changes around the zero-crossing window.

Dimensions