feature

Highly integrated: 16-channel DAC in 12 mm 12 mm LFBGA; 14-bit resolution via increment/decrement mode; guaranteed monotonicity; low power, SPITM, QSPITM, MICROWIRETM and DSP-compatible three-wire serial interface; output impedance 0.5 ; Output voltage range: 2.5V (AD5516-1); 5V (AD5516-2); 10V (AD5516-3); Asynchronous reset device (via reset pin); Asynchronous power down device (via PD pin); Daisy chain mode; temperature range: –40 C to +85 C.

application

Level settings; instrumentation; automatic test equipment; optical networks; industrial control systems; data acquisition; low-cost I/O.

General Instructions

The AD5516 is a 16-channel 12-bit voltage output DAC. This selected DAC register is written over the 3-wire serial interface. DAC selection is done through address bits A3–A0. 14-bit resolution can be achieved with incremental trim/decrement mode (mode 2). The serial interface operates at clock frequencies up to 20 MHz and is compatible with standard SPI, Microwire and DSP interface standards. The output voltage-age range is fixed at ±2.5 V (AD5516-1), ±5 V (AD5516-2), and ±10 V (AD5516-3). Access to each channel is provided through RFB0 to the RFB15 pin.

The device needs a stable 3V reference voltage when AVCC=5V±5%, DVCC=2.7V to 5.25V, the voltage standard value is -4.75V to -12V, and the voltage standard value is +4.75V to +12V.

Product Highlights

1. 16 12-bit DACs in one package to ensure monotonicity.

2. Provide 74 lead LFBGA package, the body size is 12mm 12mm.

Serial Interface Timing Diagram

the term

Integral Nonlinearity (INL)

This is a measure of the maximum deviation of a straight line through the endpoints of the DAC transfer function. It is expressed in LSB.

Differential Nonlinearity (DNL)

Differential Nonlinearity (DNL) is the difference between the measured variation of any two adjacent codes and the ideal 1lsb variation. A specified DNL of –1 LSB maximum ensures monotonicity.

Bipolar Zero Error

Bipolar zero error is the deviation of the DAC output from the ideal midscale of 0 V. Measured with 10…00 loaded into the DAC. It is expressed in LSB.

Positive full-scale error

This is the error in the output voltage of the DAC when all 1s are loaded into the DAC. Ideally, when all 1s are loaded into the DAC registers, the DAC output voltages should be 2.5v–1lsb (AD5516-1), 5v–1lsb (AD5516-2), and 10v–1lsb (AD5516-3). It is expressed in LSB.

Negative full-scale error

This is the error in the output voltage of the DAC when all 0s are loaded into the DAC. Ideally, the DAC output voltages with all 0s loaded into the DAC registers should be -2.5 V (AD5516-1), -5 V (AD5516-2), and -10 V (AD5516-3). It is expressed in LSB.

Output temperature coefficient

This is a way to measure the change in analog output with temperature. It is expressed in ppm/°C of FSR.

DC power rejection ratio

The DC Power Supply Rejection Ratio (PSRR) is a measure of the change in the analog output as the supply voltage (V and V) changes. It is expressed in dBs. V and V variation is ±5%.

DC crosstalk

This is the DC change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and the output of the other DAC. Expressed in mV.

Output stabilization time

This is the time from the last data bit entering the DAC until the output settles to within ±0.5 LSB of its final value (see TPC 7).

Digital-to-analog fault pulse

This is the faulty region injected into the analog output when the code in the DAC register changes state. LSB (011…11 to 100…00 or 100…00 to 011…11) when numeric code is changed to major-carry transition.

digital crosstalk

This is a glitch pulse going to the mid-scale output of one DAC, while a full-scale code change (all 1s to all 0s and vice versa) is being written to the other DAC. It is expressed in nV-secs.

Analog crosstalk

This is one DAC due to a full-scale change in the output (V) of the other DAC due to the faulty region of the transfer to the output (V). The fault area is expressed in nV secs.

digital feedthrough

This is a measure of the pulses injected from the digital control input into the analog output when the part is not written, i.e. when the synchronization is high. It is specified in nV secs and is measured on a digital input pin with a worst-case change, e.g. from 0 to 1 and vice versa.

Output Noise Spectral Density

This is random noise generated inside the measurement. Random noise is characterized by its spectral density (voltage per gigahertz). The unit of measurement is nV/(Hz).

AD5516 – Typical Performance Characteristics

Function description

The AD5516 consists of 16 12-bit DACs in one package. A single reference input pin (REF_-IN) is used to provide a 3 V reference for all 16 DACs. To update the output voltage of the DAC, the desired DAC is addressed through a 3-wire serial interface. After the serial write is complete, the selected DAC converts the code to an output voltage. The output amplifier converts the DAC output range to the appropriate voltage range (±2.5 V, ±5 V or ±10 V at output pins V0 to V15).

The AD5516 uses a self-calibrating architecture to achieve 12-bit performance. The calibration routine servos select the appropriate voltage levels on the internal 14-bit resolution DAC. Noise during calibration (busy-low cycles) can cause the selection voltage to be within the ±0.25 LSB band around the normal selection voltage. See TPC 10.

For optimum performance, the noise on REFIN must be minimized. The specified decoupling of the AD780 makes it an ideal reference for driving the AD5516. On power-up, all DACs power up to the reset value (see the reset section).

Digital-to-analog conversion part

The structure of each DAC channel consists of a resistor string DAC and an output buffer amplifier. The voltage at the REF_IN pin provides the reference voltage for the corresponding DAC. The input to the DAC is encoded as offset binary; this results in an ideal DAC output voltage as follows:

Where: D= the decimal equivalent of the binary code loaded into the DAC register, i.e. 0–4096; N=DAC resolution=12.

Table 1 illustrates the ideal analog output versus DAC code.

operating mode

The AD5516 has two modes of operation.

Mode 1 (Mode bit = 00): The user programs the 12-bit data word to one of 16 channels via the serial interface. This word is loaded into the addressed DAC register and then converted to an analog output voltage. During conversions, the busy output is low and all SCLK pulses are ignored. At the end of the conversion, BUSY goes high, indicating that the update of the addressed DAC is complete. It is recommended not to pulse SCLK when busy. Mode 1 transitions take 25µs typical.

Mode 2 (Mode bits = 01 or 10): Mode 2 operation allows the user to increment or decrement the DAC output in 0.25 LSB steps, resulting in a 14-bit monotonic DAC. The amount by which the DAC output is incremented or decremented is determined by Mode 2 bits DB6–DB0, eg, for 0.25 LSB increment/decrement DB6…DB0=0000001, and for 2.5 LSB increment/decrement DB6…DB0=0001010. The mode bits determine whether the DAC data is incremented (01) or decremented (10). The maximum amount the user is allowed to increase or decrease the DAC output is 127 steps of 0.25lsb, which is DB6...DB0=1111111. Mode 2 updates take about 1 microsecond. The Mode 2 function allows for increased resolution, but the overall increment/decrement accuracy varies with increment/decrement steps, as shown in TPC 14. Mode 2 is useful in applications that require higher resolution, for example, in servo applications that require fine-tuning to 14-bit resolution.

The user must allow 200 ns (min) between two consecutive Mode 2 writes in standalone mode and 400 ns (min) between two consecutive Mode 2 writes in daisy-chain mode.

Mode 1 and Mode 2 data formats are shown in Figures 4 and 5.

When the mode bit = 11, the device is in no operation mode. This can be useful in daisy chain applications where the user does not want to change the DAC's settings. Simply write 11 to the mode bits and the following address and data bits will be ignored.

serial interface

The AD5516 has a 3-wire interface that is compatible with SPI/QSPI/MICROWIRE and DSP interface standards. Data is written to the device in 18-bit words. This 18-bit word consists of two mode bits, four address bits, and 12 data bits, as shown in Figure 4.

The serial interface can work with continuous clocks and burst clocks. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift register. Any other edges while synchronizing are ignored until the correct number of bits is shifted in or out. For another serial transfer, the counter must be reset by a synchronous falling edge.

Level A3–A0

Four address bits (A3=MSB address, A0=LSB). They are used to process one of the 16 DACs.

DB11–DB0

They are used to write 12-bit words to the addressed DAC registers. Figure 1 and Figure 2 show the timing diagrams for a write cycle to the AD5516.

Sync function

In standalone mode and daisy-chain mode, SYNC is an edge-triggered input used as a frame sync signal and chip enable. Data can only be transferred to the device when sync is low. To start serial data transfer, SYNC should be set low and observe the minimum setup time t from the falling edge of SYNC to the falling edge of SCLK.

Standalone mode (DCEN=0)

After sync goes low, serial data will be transferred into the device input shift register on the falling edge of SCLK for 18 clock pulses. After the falling edge of the 18th SCLK pulse, data is automatically transferred from the input shift register to the addressing DAC.

Synchronization High and low must be done again for further serial data transfer. Synchronization is possible on the 18th SCLK pulse, observe the minimum SCLK falling edge synchronization rising edge time, t. If on the 18th falling edge of SCLK, the data transfer will be aborted and the addressed DAC will not be updated. See the timing diagram in Figure 1.

Daisy Chain Mode (DCEN=1)

In daisy-chain mode, the internal strobe on SCLK is disabled. When sync is low, SCLK is continuously applied to the input shift register. If more than 18 clock pulses are applied, the data fluctuates out of the shift register and appears on the D line. This data is clocked on the rising edge of SCLK and is valid on the falling edge. By connecting this wire to the D input on the next device in the chain, a multi-device interface is constructed. Each device in the system requires 18 clock pulses. Therefore, the total number of clock cycles must equal 18N, where N is the total number of devices in the chain. See the timing diagram in Figure 2.

Sync should be set high when the serial transfer to all devices is complete. This prevents any further data from being recorded into the input shift register. It is possible to use a burst clock that contains the exact number of clock cycles, with high synchronization after a period of time. After the rising edge of synchronization, data is automatically transferred from each device's input shift register to the addressing DAC.

Reset function

The reset function on the AD5516 can be used to reset all nodes on the device to a power-on reset state. This is achieved by applying a minimum 20 ns low pass pulse to the reset pin on the device.

BUSY output

During conversions, the busy output is low and all SCLK pulses are ignored. At the end of the conversion, BUSY goes high, indicating that the update of the addressed DAC is complete. It is recommended not to pulse SCLK when busy.

Microprocessor interface

The AD5516 is controlled through a versatile 3-wire serial interface that is compatible with many microprocessors and DSPs.

AD5516 to ADSP-2106x SHARC DSP Interface

The ADSP-2106x SHARC DSPs are easy to interface with the AD5516 without additional logic.

The AD5516 expects t (sync falling edge to SCLK falling edge setup time) to be 15 ns min. Refer to the ADSP-2106x User Manual for information on the clock and frame sync frequencies of the motion registers and the contents of the TDIV and RDIV registers.

After motion is enabled, data transfer is initiated by writing a word to the TX register. During the write sequence, data is clocked into the AD5516 on every rising edge of the DSP's serial clock and on the falling edge of its SCLK. The settings of the motion transfer control registers are as follows:

DTYPE=00, right-aligned data;

ICLK=1, internal serial clock;

TFSR=1, frame each word;

INTF=1, internal frame synchronization;

LTFS=1, active low frame sync signal;

LAFS=0, early frame synchronization;

SENDN=0, the data is transmitted MSB first;

SLEN=10011, 18-bit data word (SLEN=serial word).

Figure 6 shows the connection diagram.

AD5516 to MC68HC11

The Serial Peripheral Interface (SPI) on the MC68HC11 is configured in master mode (MSTR=1), clock polarity bit (CPOL)=0 and clock phase bit (CPHA)=1. SPI is configured by writing to the SPI Control Register (SPCR) - see the 68HC11 User Manual. The SCK of the 68HC11 drives the SCLK in the AD5516, and the MOSI output drives the serial data line (D) of the AD5516. The sync signal comes from the port on the line (PC7). When data is sent to the AD5516, the sync line is taken low (PC7). Data displayed on the MOSI output is valid on the falling edge of SCK. Serial data for the 68HC11 is transmitted in 8-bit bytes, with only 8 falling clock edges during the transmission cycle. The data MSB is transferred first. In order to transfer 18 data bits, the data in the SPDR register must be left aligned. PC7 must be pulled low to start a transfer and pulled high or low again before any further read/write cycles. The connection diagram is shown in Figure 7.

AD5516 to PIC16C6x/7x

The PIC16C6x/7x Synchronous Serial Port (SSP) is configured as an SPI master with Clock Polarity Bit (CKP) = 0. This is done by writing to the Synchronous Serial Port Control Register (SSPCON). Please refer to the User's PIC16/17 Microcontroller User's Manual. In this example, I/O port RA1 is used to provide the synchronization signal and enable the serial port of the AD5516. This microcontroller transfers only 8 bits of data in each serial transfer operation; therefore, three consecutive write operations are required. Figure 8 shows the connection diagram.

AD5516 to 8051

The serial interface between the AD5516 and the 80C51/80L51 microcontroller is shown in Figure 9. The AD5516 requires a clock that is synchronized with the serial data. Therefore, the 8051 serial interface must operate in mode 0. The microcontroller's TxD drives the AD5516's SCLK, while the RxD drives the serial data lines. P3.3 is a bit programmable pin on the serial port used to drive synchronization. The 80C51/80L51 provides the LSB first, while the AD5516 requires the MSB of the 18-bit word first. Care should be taken to ensure that the transfer routine takes this into account.

When data is transferred to the DAC, P3.3 is taken low. The data on RxD is valid on the falling edge of TxD, so the clock must be inverted to the AD5516 clock data into the input shift register on the rising edge of the serial clock. The 80C51/80L51 transmits its data in 8-bit bytes with only 8 falling clock edges during the transmission cycle. Since the DAC requires an 18-bit word, P3.3 must remain low after the first 8 bits have been transmitted and high after the entire 18 bits have been transmitted. When the device is in daisy chain mode, DOUT can be tied to RxD for data verification.

application circuit

The AD5516 is suitable for many applications such as level setting, optics, industrial systems and automated test applications. The Mode 2 function increases resolution in horizontal settings and servo applications where fine-tuning is required. The figure below shows the AD5516 used in some potential applications.

AD5516 in a typical ATE system

The AD5516 is ideal for level setting functions in automatic test equipment. Many DACs are required to control pin drivers, comparators, active loads, parametric measurement units and signal timing. Figure 10 shows the AD5516 in such a system.

Application of AD5516 in Optical Network Control Loop

The AD5516 can be used in optical network control applications that require a large number of DACs to perform control and measurement functions. In the example shown below, the output of the AD5516 is fed into an amplifier and used to control the driver to determine the position of the MEMS mirror in the optical switch. The exact position of each mirror is measured and the readings are multiplexed into an 8-channel 14-bit ADC (AD7865). The DAC's increment and decrement modes are useful in this application as it allows the user 14-bit resolution. The control loop is driven by the ADSP-2106x of 32-bit SHARC DSPs.

Power decoupling

In any circuit where accuracy is important, careful consideration of power and ground return layout helps ensure rated performance. The printed circuit board on which the AD5516 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5516 is in a system where multiple devices require an AGND to DGND connection, this connection should only be made at one point. The star ground point should be as close as possible to the device. For power supplies with multiple pins (AV1, AV2), it is recommended to tie these pins together. The AD5516 should have ample supply bypassing of 10µF in parallel with 0.1µF on each supply, each as close to the package as possible, ideally close to the device. The 10µF capacitors are of the tantalum bead type. The 0.1µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like common ceramic types that provide a high frequency, low impedance path to ground to handle transient currents from internal logic switches.

The power lines to the AD5516 should use as large traces as possible to provide a low impedance path and reduce the effect of faults on the power lines. Fast switching signals such as clocks should use a digital ground shield to avoid radiating noise to other parts of the board and must not run near the reference input. A ground wire routed between the D and SCLK lines will help reduce crosstalk between them (not needed on multi-layer boards as there will be a separate ground plane, but separating the lines will help). Noise during oil changes must be minimized.

Avoid crossover of digital and analog signals. The traces on opposite sides of the board should be at right angles to each other. This reduces feedthrough effects through the board. Micro-stripe technology is by far the best, but dual panels are not always possible. In this technique, the component side of the board is dedicated to the ground plane, while the signal lines are placed on the solder side. As with all thin packages, during assembly, care must be taken to avoid buckling of the package and to avoid point loads on the surface of the package.

Dimensions

Dimensions are in mm and (inches)