feature

128 positions; 10 kΩ, 50 kΩ, 100 kΩ; 20 V to 30 V single supply operation ±10 V to ±15 V dual supply operation; 3-wire SPI® compatible serial interface THD 0.006% typical programmable preset; off Electrical: Less than 1 microamp; iCMOS™ process technology.

application

High Voltage DAC; Programmable Power Supply; Programmable Gain and Offset Adjustment; Programmable Filter, Delay; Actuator Control; Audio Volume Control; Mechanical Potentiometer Replacement.

General Instructions

The AD7376 is one of the few high-voltage, high-performance digital potentiometers on the market. The device can be used as a programmable resistor or resistor divider. The AD7376 features the same electronic adjustment capabilities as mechanical potentiometers, variable resistors, and trimmers with enhanced resolution, solid-state reliability, and programmability. With digital control rather than manual control, the AD736 provides layout flexibility and allows closed-loop dynamic controllability.

The AD7376 features sleep mode programmability at shutdown, which can be used to program presets before device activation, providing an alternative to expensive EEPROM solutions.

The AD7376 is available in 14-line TSSOP and 16-line wide body SOIC packages and is available in 10 kΩ, 50 kΩ, and 100 kΩ. All parts are guaranteed to operate over the extended industrial temperature range of -40°C to +85°C.

Typical performance characteristics

theory of operation

Variable Resistor Programming

Rheostat operation

The part operates in varistor mode when only two terminals are used as variable resistors. Unused terminals can be left floating or tied to W terminals as shown in Figure 24.

The nominal resistance RAB between terminals A and B is 10 kΩ, 50 kΩ and 100 kΩ, with a tolerance of ±30%, and has 128 taps accessible through the wiper terminals. Decode the 7-bit data in the RDAC latch to select one of 128 possible settings. Figure 25 shows a simplified RDAC structure.

The general formula for determining the digitally programmed output resistance between the W and B terminals is:

where: D is the decimal equivalent of the binary code loaded in the 7-bit RDAC register from 0 to 127. RAB is end-to-end resistance. RW is the wiper resistance generated by the on-resistance of the internal switch.

The AD7376 wiper switch uses a transmission gate CMOS topology with the gate voltage derived from VDD. The on-resistance RW of each switch is a function of VDD and temperature (see Figure 13). In contrast to the temperature coefficient of the RAB, the temperature coefficient of the wiper resistance is significantly higher because the wiper resistance doubles every 100°. Therefore, the user must consider the contribution of RW to the desired resistance. On the other hand, the on-resistance of each switch is insensitive to the wiper potential, remaining relatively flat at 120Ω, which is typical at 15 V VDD and 25°C.

Assuming a 10 kΩ part is used, the first connection to the wiper starts at the B terminal of programming code 0x00 with SWB closed. Therefore, the minimum resistance between terminals W and B is typically 120Ω. The second connection is the first tap point, corresponding to 198Ω (RWB=1/128×RAB+RW=78Ω+120Ω), for programming code 0x01, and so on.

For each additional LSB data value, the wiper moves up the resistor ladder until the last tap point reaches 10042Ω (RAB – 1 LSB+RW). Regardless of which setting the part is operating in, care should be taken to limit the current conducted between the A and B, W and A, and W and B terminals to a maximum of 5mA DC and a maximum of 20mA of pulsed current. Failure to do so may result in degradation or damage to the internal switch contacts. Similar to a mechanical potentiometer, the resistance of the RDAC between the W and A terminals also produces a digitally controlled complementary resistance RWA.

When using these terminals, the B terminal can be opened. The resistance value that sets the RWA starts at the maximum value of the resistance and decreases as the value of the data loaded into the latch increases. The general equation for this operation is:

Program the Potentiometer Divider

Voltage output operation

A digital potentiometer easily creates a voltage divider proportional to the input voltage at terminal a to terminal B at wiper W to terminal B and wiper W to terminal a. Unlike the polarity of VDD to ground (which must be positive), the voltages between terminal a to terminal B, wiper W to terminal a, and wiper W to terminal B can be polar.

If the effect of wiper resistance is ignored for approximation, connecting terminal A to 30 V and terminal B to ground produces an output voltage of 0 V to 1 LSB of less than 30 V from wiper W to terminal B. The voltage at each LSB is equal to the voltage applied to terminals A and B divided by the 128 positions of the potentiometer divider. For any effective input voltage applied across terminals A and B, the general equation that defines the output voltage of VW relative to ground is:

A more precise calculation includes the effect of the wiper resistance V,

Operation of the digital potentiometer in voltage divider mode results in more accurate overtemperature operation. Unlike the varistor mode, the output voltage in the voltage divider mode is mainly determined by the ratio of the internal resistors RWA and RWB, not the absolute value. Therefore, the temperature drift is reduced to 5ppm/°C.

Three-wire serial bus digital interface

The AD7376 contains a 3-wire digital interface (CS, CLK, and SDI). The 7-bit serial word MSB must be loaded first. The format of the word is shown in Figure 2. The positive edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work fine. When CS is low, the clock loads data into the serial register on each positive clock edge.

The data setup and hold times in Table 3 determine the effective timing requirements. The AD7376 uses a 7-bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic high. The extra MSB bits are ignored.

The AD7376 starts up randomly. However, by manipulating RS or SHDN with additional I/O, a mid-scale preset or any desired preset can be achieved.

When the reset (RS) pin is asserted, the wipers are reset to the midscale value. Midscale reset can be achieved dynamically or during power-up if additional I/O is used.

When the SHDN pin is asserted, the AD7376 turns on SWA, leaving terminal A floating and shorting wiper W to terminal B. In shutdown mode, the AD7376 consumes negligible power, and once the SHDN pin is released, the AD7376 will restore the previous setting. On the other hand, the AD7376 can be programmed with any setting during shutdown. This unique feature allows the AD7376 to be programmed to preset at any desired level, thanks to an additional programmable I/O assertion shutdown during power-up.

Table 7 shows the logical truth table for all operations.

Daisy Chain Operation

Figure 27 shows the details of the serial data output pin (SDO). SDO shifts out the SDI content from the previous frame; thus, it can be used to daisy-chain multiple devices. The SDO pin contains an open-drain N-channel MOSFET and requires a pull-up resistor if the SDO function is used.

The user needs to bind the SDO pin of one package to the SDI pin of the next package. For example, in Figure 28, if two AD7376s were daisy-chained, a total of 14 bits of data would be required per operation. The first set of 7 bits goes into U2; the second set of 7 bits goes into U1. CS should be held low until all 14 bits have entered their respective serial registers. Then pull CS high to complete the operation.

When daisy-chaining multiple devices, the user may need to increase the clock period because the pull-up resistors and capacitive loading at the SDO to SDI interface may cause time delays for subsequent devices.

ESD protection

All digital inputs are protected with series input resistors and ESD structures, as shown in Figure 29. These structures apply to the digital input pins CS, CLK, SDI, RS, and SHDN.

All analog terminals are also protected by ESD protection diodes, as shown in Figure 30.

Terminal voltage operating range

The AD7376 VDD and VSS supplies define the boundary conditions for proper 3-terminal digital potentiometer operation. Applied signals appearing on terminals A, B, and W that are more positive than VDD or more negative than VSS are clamped by internal forward-biased diodes (see Figure 30).

Power-Up and Power-Down Sequence

Since ESD protection diodes limit voltage compliance at terminals A, B, and W (see Figure 30), it is important to power up VDD/VSS before applying voltage to terminals A, B, and W. Otherwise, the diodes will be forward biased, causing VDD/VSS to power up unexpectedly and affecting the system. Again, VDD/VSS should shut down last. The ideal power-up sequence is as follows: GND, VDD, VSS, digital input, and VA/VB/VW. The order in which VA, VB, VW, and the digital inputs are powered does not matter, as long as they are powered after VDD/VSS.

Layout and Supply Bias

It is good practice to design a layout with a compact, minimum lead length. Wires to the input should be as direct as possible, with a minimum wire length. The ground path should have low resistance and low inductance.

Also, it is a good practice to bypass the power supply with a good quality capacitor. A low ESR (equivalent series resistance) 1µF to 10µF tantalum or electrolytic capacitor should be used at the power supply to minimize transients and filter out low frequency ripple. Figure 31 shows the basic power supply bypass configuration for the AD7376.

The ground pin of the AD7376 is the digital ground reference. To minimize digital ground bounce, the AD7376 digital ground terminal should be connected remotely to the analog ground (see Figure 31).

application information

High Voltage DAC

The AD7376 can be configured as a high voltage DAC up to 30V. The circuit is shown in Figure 32. The output is:

where D is a decimal code between 0 and 127.

Programmable Power

For a boost regulator like the ADP1611, the AD7376 can be used as a variable resistor at the FB pin of the regulator to provide a programmable power supply (see Figure 33). The output is:

Note that the VDD of the AD7376 comes from the output. Initially, L1 acts as a short circuit and VDD is a diode drop below +5v. The output slowly settles to its final value.

AD7376 shutdown sleep mode programming can be used to program the desired preset level at power-up.

Audio volume control

The AD7376 has good THD performance and high voltage performance and can be used for digital volume control. If the AD7376 is used directly as an audio attenuator or gain amplifier, a large step change in volume level at any time can cause abrupt interruptions in the audio signal, resulting in audible zipper noise. To prevent this, a zero-crossing window detector can be plugged into the CS line to delay device updates until the audio signal crosses the window. Since the input signal can operate at any DC level rather than an absolute zero volt level, in this case a zero crossing means that the signal is AC coupled, and the DC offset level is the signal zero reference point.

The configuration for reducing zipper noise and the results of using this configuration are shown in Figure 35 and Figure 34, respectively. The input is AC coupled by C1 and attenuated before the input to a window comparator formed by U2, U3, and U4B. U6 is used to establish the signal zero reference. The upper limit of the comparator is set above its offset, so in this example the output pulses high whenever the input is between 2.502 V and 2.497 V (or 0.005 V window). This output is used with the chip select signal so that the AD7376 updates when the signal crosses the window. To avoid constant device updates, the chip select signal should be programmed with two pulses instead of the one shown in Figure 2.

In Figure 34, the lower trace shows that the volume level changes from quarter to full scale as the signal changes around the zero-crossing window.

The AD7376 shutdown sleep mode programming feature can be used to mute the device at power-up by holding SHDN low and programming zero scale.

Dimensions