feature

Specified VDD from 2.7 V to 5.25 V; flexible power/throughput management; shutdown mode: 1 μA max; one or two single-ended inputs; serial interface: SPI@/QSPI 8482 ; Compatible 8-lead narrow SOIC and MSOP packages for automotive applications.

application

Battery-powered systems (personal digital assistants, medical devices, mobile communications); instrumentation and control systems; high-speed modems.

General Instructions

The AD7887 is a high speed, low power, 12-bit analog-to-digital converter (ADC) that can be powered from a single 2.7V to 5.25V supply. The AD7887 has a throughput rate of 125 kSPS. The input track and hold acquires the signal within 500ns and has a single-ended sampling scheme. The output encoding of the AD7887 is straight binary, and this section is capable of converting full power signals up to 2.5MHz.

The AD7887 can be configured for dual-channel or single-channel operation through on-chip control registers. The default single-channel mode allows the AD7887 to operate as a read-only ADC. In single-channel operation, there is one analog input (AIN0), and the AIN1/VREF pin assumes its VREF function. This VREF pin allows the user to access the part's internal 2.5 V reference, or the VREF pin can be driven from an external reference to provide the part with a reference. This external reference voltage can range from 2.5 V to VDD. The analog input range on AIN0 is 0 to VREF.

In dual-channel operation, the AIN1/VREF pin assumes its AIN1 function, providing a second analog input channel. In this case, the reference voltage for the part is provided through the VDD pin. Therefore, the input voltage range on the AIN0 and AIN1 inputs is 0 to VDD.

The CMOS structure ensures low power consumption of typically 2 megawatts in normal operation and 3 microwatts in power-down mode. The part is available in 8-lead, 0.15-inch wide and narrow body SOIC and 8-lead MSOP packages.

Product Highlights

1. The smallest 12-bit dual/single-channel ADC; 8-lead MSOP package.

2. Lowest power consumption 12-bit dual/single-channel ADC.

3. Flexible power management options, including automatic power down after conversion.

4. Read-only ADC function.

5. The analog input range is from 0V to VREF.

6. Universal serial input/output port (compatible with SPI/QSPI/MICROWIRE/DSP).

Typical performance characteristics

the term

Integral nonlinearity

This is the maximum deviation of a straight line through the endpoints of the ADC transfer function. The end point of the transfer function is zero scale, one-and-a-half LSB on the first code transition, and full scale, one-half LSB on the last code transition.

Differential nonlinearity

This is the difference between the measured value and the ideal 1 LSB change between any two adjacent codes in the ADC.

offset error

This is the deviation of the first code transition (00.000) to (00.001) ideally, AGND + 0.5lsb.

offset error matching

This is the offset error difference between any two channels.

gain error

This is the deviation of the last code transition (111...110) to (111...111) after adjusting the offset error from the ideal value (ie VREF−1.5 LSB).

Gain Error Matching

This is the difference in gain error between any two channels.

Track/Hold Acquisition Time

At the end of the conversion, the track/hold amplifier returns to track mode. The track/hold capture time is the time it takes for the output of the track/hold amplifier to reach its final value (within ±1/2 LSB) after the end of the conversion.

signal to noise ratio

This is the ratio of signal to (noise + distortion) measured at the ADC output. The signal is the rms amplitude of the interesting Damenthal. Noise is the sum of all non-fundamental signals up to half the sampling frequency (fS/2), excluding DC. The ratio depends on the number of quantization levels in the digitization process: the more levels, the less quantization noise. The theoretical signal-to-noise ratio for an ideal N-bit sine wave converter is given by: Signal to (Noise + Distortion) = (6.02 N + 1.76) dB, so for a 12-bit converter this is 74 dB.

total harmonic distortion

Total Harmonic Distortion (THD) is the ratio of the root mean square sum of harmonics to the fundamental. For the AD7887, it is defined as:

where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and v6 are the rms amplitudes of the second to sixth harmonics.

Peak harmonics or spurious noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to fS/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, the largest harmonic may be the noise peak.

Intermodulation Distortion

When the input consists of two sine waves of frequencies fa and fb, any active device with nonlinearity produces distortion products at the sum and difference frequencies of mfa±nfb, where m, n = 0, 1, 2, 3, and many more. Intermodulation distortion terms refer to terms where neither m nor n equals 0. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

The AD7887 was tested using the CCIF standard using two input frequencies near the top of the input bandwidth. In this case, the second-order term is usually at a distance from the original sine wave in frequency, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second- and third-order terms are specified separately. Intermodulation distortion is calculated according to the THD specification, where it is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental sum expressed in decibels.

Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a full-scale 25 kHz sine wave signal to a non-selected input channel and determining how much the signal is attenuated in the selected channel. The numbers given are the worst case of the two channels of the AD7887.

Power Supply Rejection (PSR)

Changes in the power supply affect full-scale conversion, but do not affect the linearity of the converter. PSR is the maximum change in the full-scale transition point due to a change in supply voltage from nominal. See Figure 7.

PSRR is the ratio of the power output by the ADC at frequency f to the power of the full-scale sine wave applied to the ADC at frequency fS: PSRR(dB) = 10 log(Pf/Pfs).

where Pf is the power at frequency f in the ADC output and Pfs is the power at frequency fS in the ADC full-scale input.

control register

The control register on the AD7887 is an 8-bit write-only register. Data is loaded from the DIN pin of the AD7887 on the rising edge of SCLK. Data is transmitted on the data line while the conversion result is read from the part. Each data transfer requires 16 serial clocks. Information provided only on the first eight rising clock edges after the CS falling edge is loaded into the control register. MSB represents the first bit in the data stream. The contents of the control registers are all 0s at power-up.

theory of operation

circuit information

The AD7887 is a fast, low power, 12-bit, single supply, single/dual ADC. The part can operate from a 3 volt (2.7 to 3.6 volt) power supply or a 5 volt (4.75 to 5.25 volt) power supply. When operating from a 5V or 3V supply, the AD7887 can achieve a throughput of 125 kSPS with a 2 MHz clock.

The AD7887 provides the user with an on-chip track/hold analog-to-digital converter reference and a serial interface packaged in an 8-wire package. The serial clock input accesses the data from the section and provides the clock source for the successive approximation ADC. The part can be configured for single-channel or dual-channel operation. When configured as a single channel section, the analog input range is 0 to VREF (where VREF for external applications can be between 1.2V and VDD). The range is determined by the internal connections from 0 to VDD when the AD7887 is configured as two input channels.

If single-channel operation is required, the AD7887 can be operated in read-only mode by permanently connecting the DIN line to GND. For applications where the user wishes to change the operating mode or wish to operate the AD7887 as a dual ADC, the DIN line can be used to clock data into the part's control register.

Inverter operation

The AD787 is a successive approximation ADC built around a charge redistribution DAC. Figures 8 and 9 show schematic diagrams of a simplified ADC. Figure 8 shows the ADC during the acquisition phase. SW2 is closed and SW1 is in position A, the comparator remains in equilibrium and the sampling capacitor takes the signal on A in.

When the ADC starts converting (see Figure 9), SW2 opens and SW1 moves to position B, causing the comparator to become unbalanced. Control logic and a charge redistribution DAC are used to add and subtract a fixed amount of charge from the sampling capacitor to bring the comparator back to equilibrium. The conversion is complete when the comparator is rebalanced. The control logic generates the ADC output codes. Figure 10 shows the ADC transfer function.

ADC transfer function

The output encoding of the AD7887 is straight binary. The designed transcoding occurs on consecutive integer LSB values (ie 1 LSB, 2 LSB, etc.). The LSB size is VREF/4096. The ideal transfer characteristics of the AD7887 are shown in Figure 10.

Typical Wiring Diagram

Figure 11 shows a typical connection diagram for the AD7887. The ground pin is connected to the analog ground plane of the system. The part is in dual-channel mode, so VREF is internally connected to a well-decoupled VDD pin to provide an analog input range of 0 V to VDD. The conversion result is output as a 16-bit word with four leading zeros followed by the MSB of the 12-bit result. For applications involving power consumption, automatic power down at the end of conversion should be used to improve power supply performance. See the Operating Modes section.

analog input

Figure 12 shows the equivalent circuit of the AD7887 analog input structure. Two diodes D1 and D2 provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 200 mV. Exceeding this value will cause the diode to be forward biased and begin to conduct to the substrate. These diodes can draw up to 20mA without irreversible damage. However, it is worth noting that (1 mA) being conducted onto the substrate due to overvoltage on the unselected channel may result in inaccurate switching on the selected channel. Capacitor C1 in Figure 12 is typically around 4pf, mainly due to pin capacitance. Resistor R1 is a lumped element consisting of the on-resistance of the multiplexer and switch. This resistance is usually about 100Ω. Capacitor C2 is the ADC sampling capacitor and typically has a capacitance of 20pf.

Note that the analog input capacitance seen in track mode is typically 38 pF and in hold mode it is typically 4 pF.

For AC applications, it is recommended to use an RC low-pass filter on the associated analog input pin to remove high frequency components from the analog input signal. In applications where harmonic distortion and signal-to-noise ratio are important, the analog input should be driven by a low impedance source. A large source impedance will significantly affect the AC performance of the ADC. This may require the use of an input buffer amplifier. The choice of op amp is a function of the specific application.

When no amplifier is driving the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. THD increases as source impedance increases and performance decreases. Figure 13 shows a plot of total harmonic distortion versus analog input signal frequency for different source impedances.

on-chip reference

The AD7887 has an on-chip voltage reference of 2.5 volts. This reference can be enabled or disabled by clearing or setting the REF bit in the control register, respectively. If an on-chip reference is to be used outside the system, it must be buffered before it can be applied elsewhere. If an external reference is applied to a device, the internal reference will be automatically overdriven. However, when applying an external reference, it is recommended to disable the internal reference by setting the reference bit in the control register for best performance from the device. When the internal reference is disabled, SW1 is on as shown in Figure 14, and the input impedance seen at the AIN1/VREF pin is the input impedance of the reference buffer and is in the gigaohm range. When the internal reference is enabled, the input impedance seen at the pin is typically 10 kΩ. When the AD7887 operates in dual-channel mode, the reference signal is taken from the internal VDD, not from the on-chip 2.5V reference signal.

Power out options

The AD787 provides flexible power management to allow the user to achieve the best power performance for a given throughput rate. Power management options are selected by programming the power management bits in the control register (ie PM1 and PM0). Table 6 summarizes the available options. When the power management bits are programmed to any of the automatic power-down modes, the part enters power-down mode on the 16th rising SCLK edge following the falling edge of CS. The first falling edge of SCLK after the falling edge of CS powers up the part again. When the AD7887 is in mode 1, that is, PM1=PM0=0, the part enters the shutdown state on the rising edge of CS and powers up from the shutdown state on the falling edge of CS. If CS rises during a transition in this mode, the part immediately goes off.

Power-on time

The AD787 has a power-up time of approximately 1µs when in standby or powered from an external reference block. When VDD is first connected, the AD7887 is powered up in Mode 1, ie PM1=PM0=0. In this mode, the part turns off on the rising edge of CS. Power-up after shutdown takes about 5µs. The AD787 wake-up time is very short in AutoStand mode, so it is possible for Hu Xi to wake up and perform a valid conversion in the same read/write operation.

Power and Throughput

By operating the AD7887 in auto-shutdown mode, auto-standby mode, or Mode 1, the average power consumption of the AD7887 is reduced at lower throughput rates. Figure 15 shows that when the throughput rate decreases, the device remains powered off for longer and the average power consumption decreases accordingly over time.

For example, if the AD7887 is operating in continuous sampling mode with a throughput of 10 kSPS, SCLK of 2 MHz (VDD=5 V), PM1=1, PM0=0, i.e. the device is in auto-shutdown mode, and the on-chip reference is used, the functional The power consumption is calculated as follows: The power consumption during normal operation is 3.5 mW (VDD = 5 volts). If the power-up time is 5 μs, and the rest of the conversion plus acquisition time is 15.5 sic, or about 7.75 μs (see Figure 18), the AD787 can be said to consume 3.5 milliwatts for 12.75 μs per conversion cycle. If the throughput rate is 10 kSPS, the cycle time is 100 μs, and the average power consumption per cycle is (12.75/100) × (3.5 mW) = 446.25 μW. If VDD=3 V, SCLK=2 MHz, and auto-shutdown mode using the on-chip reference, the power consumption in normal operation is 2.1 mW. The AD7887 can now be said to dissipate 2.1 MW for 12.75 μs per conversion cycle. With a throughput of 10 kSPS, the average power consumption per cycle is (12.75/100) × (2.1 mW) = 267.75 μW. Figure 15 shows the power to throughput ratio for automatic shutdown of 5 V and 3 V supplies.

operating mode

The AD787 features several modes of operation designed to provide flexible power management options. These options can be selected to optimize the power/throughput ratio for different application requirements. The operating mode is controlled by the PM1 and PM0 bits of the control register, as shown in Table 6 above. For read-only operation of the AD7887, the default mode of all 0s in the control register can be set by holding the data lines low.

Mode 1 (PM1=0, PM0=0)

This mode allows the user to control the power down of the part via the CS pin. Whenever CS is low, the AD7887 is fully powered up; whenever CS is high, the AD7887 is fully powered down. When CS goes from high to low, all on-chip circuits start to power up. For AD787 internal circuit, the electric circuit needs about 5μs power supply. Therefore, no conversions (or sample-and-hold acquisitions) should be initiated during these 5µs.

Figure 16 shows a general diagram of the operation of the AD7887 in this mode. The input signal completes on the second rising edge of SCLK following the falling edge of CS. The user should ensure that 5µs elapses between the falling edge of CS and the second rising edge of SCLK. In microcontroller applications, this is easily accomplished by driving the CS input from one of the port lines and ensuring that serial data reads (from the microcontroller serial port) do not initiate 5µs. In DSP applications, CS is usually derived from the serial frame sync line, and it is usually not possible to separate the CS falling edge from the second SCLK rising edge by 5µs without affecting the speed of the rest of the serial clock. Therefore, the user must write to the control register to exit this mode, and (by writing PM1=0 and PM0=1) put the part into mode 2, normal mode. When the part is powered up to obtain the conversion result, a second conversion needs to be initiated. A second transition of the write operation that occurs at the same time can return the part to Mode 1, and the part goes into power-down mode when CS returns high.

Mode 2 (PM1=0, PM0=1)

In this mode of operation, the AD7887 remains fully powered up regardless of the state of the CS line. It's designed to get the fastest throughput performance, as users don't have to worry about the aforementioned 5µs power-on time. Figure 17 shows a schematic of the operation of the AD7887 in this mode.

During the first eight clock cycles of a data transfer, the data presented to the AD7887 on the data line is loaded into the control register. To continue operating in this mode, the user must ensure that PM1 is loaded with 0 and PM0 is loaded with 1 on each data transfer.

The falling edge of CS initiates the sequence and samples the input signal on the second rising edge of the SCLK input. It takes 16 serial clock cycles to complete the conversion and access the conversion result. Once the data transfer is complete (i.e. once CS returns high), another conversion can be started immediately by turning CS low again.

Mode 3 (PM1=1, PM0=0)

In this mode, the AD7887 automatically enters a full shutdown mode at the end of each conversion. It is similar to Mode 1 except that the state of CS has no effect on the power down state of the AD7887.

Figure 18 shows a schematic of the operation of the AD7887 in this mode. On the first falling SCLK edge after CS goes low, all on-chip circuits begin to power up. For AD787 internal circuit, the electric circuit needs about 5μs power supply. Therefore, no conversions (or sample-and-hold acquisitions) should be initiated during these 5µs. The input signal is sampled on the second rising edge of SCLK following the falling edge of CS. The user should ensure that 5µs elapses between the first falling edge of SCLK and the second rising edge of SCLK following the CS falling edge, as shown in Figure 18. In a microcontroller application (or use a slow serial clock), by driving the CS input of one of the port lines, and ensuring that serial data reads (from the microcontroller's serial port) do not initiate 5µs, this is easy to achieve. However, for higher speed serial clocks, the 5µs delay from power-up to the first rising edge of SCLK will not be possible. Therefore, the user must write to the control register to exit this mode and put the section into mode 2 (by writing PM1=0 and PM0=1). When the part is powered up to obtain the conversion result, a second conversion needs to be initiated, as shown in Figure 19. A write operation in conjunction with the second conversion can return the part to Mode 3, and when the conversion sequence ends, the part enters a power-down mode.

Mode 4 (PM1=1, PM0=1)

In this mode, the AD7887 automatically enters standby (or sleep) mode at the end of each conversion. In this standby mode, all on-chip circuits are powered down except for the on-chip reference. This mode is similar to Mode 3, but in this case the power-up time is much shorter because the on-chip reference is always powered on.

Figure 20 shows a schematic of the operation of the AD7887 in this mode. On the first falling SCLK edge after CS falls, the AD7887 comes out of standby. In this mode, the AD7887 wake-up time is very short, so it is possible to wake up the part and perform a valid conversion in the same read/write operation. The input signal is sampled on the second rising edge of SCLK, immediately following the falling edge of CS. At the end of the conversion (last rising edge of SCLK), the part automatically enters standby mode.

serial interface

Figure 21 shows a detailed timing diagram for the serial interface to the AD7887. The serial clock provides the conversion clock and controls the transfer of information to and from the AD7887 during conversions. CS initiates the data transfer and conversion process. For some modes, the falling edge of CS wakes up the part. In all cases the serial clock is passed to the AD7887 and put into the chip trace/hold into trace mode. The input signal is on the rising edge of CS ond after the falling edge of the SCLK input. Therefore, the first 1.5 clock cycles after the drop point when the incoming signal is acquired. This time is denoted as acquisition time (tACQ). The mode acquisition time that wakes up the part on the falling edge of CS must allow a wake-up time of 5µs and the track/hold on the chip goes from track mode to the second rising edge of SCLK and also initiates the conversion on this edge. The conversion process requires an additional 14 half SCLK cycles to complete. A rising edge restores the bus to three states. If CS is low, a conversion can be initiated. In dual-channel operation, the input channel sampled is the channel selected during the last write to the control register. Therefore, in dual channel operation, the user must have the channel address of the next conversion while the current conversion is in progress.

Writing to the control register occurs on the first eight rising edges of SCLK during a data transfer. When a data transfer occurs, the control register is always written. However, the AD7887 can be operated in read-only mode by binding the data to the low-order bits, thereby loading the control register with all 0s each time. When operating the AD7887 in read/write mode, the user must always be careful to set the correct information on the data lines when reading data from the part.

16 serial clock cycles are required to perform con version processing and access data from the AD7887. In applications where the first serial clock edge following CS going low is a falling edge, this edge knocks off the first leading zero. Therefore, the first rising clock edge on the SCLK clock provides the first leading zero. In applications where the first serial clock edge after CS goes low is a rising edge, the first leading zero may not be set in time for the processor to read it correctly. However, subsequent bits are clocked on the falling edge of SCLK so that they are presented to the processor on the next rising edge. Therefore, the second leading zero is clocked on the falling edge after the first rising edge. The last bit in the data transfer was valid on the rising edge of 16, clocked on the previous falling edge.

Microprocessor interface

The serial interface on the AD7887 allows the part to be directly connected to many different microprocessors. This section describes how to interface the AD7887 with some of the more common microcontroller and DSP serial interface protocols.

AD7887 to TMS320C5x

The serial interface on the TMS320C5x uses continuous serial clock and frame synchronization signals to synchronize data transfer operations with peripherals such as the AD7887. The CS input allows the serial clock on the TMS320C5x and AD7887 to be just glue logic required. The serial port of the TMS320C5x is set up to run in burst mode using the internal CLKX (Tx serial clock) and FSX (transmit frame sync). The Serial Port Control Register (SPC) must have the following settings: FO=0, FSM=1, MCM=1, TXM=1. The connection diagram is shown in Figure 22.

AD7887 ADSP-21xx

The DSPs of the ADSP-21xx family are easily connected to the AD7887 through an inverter between the serial clock of the ADSP-21xx and the AD7887. This is the only glue logic needed. The settings of the motion control registers are as follows:

The connection diagram is shown in Figure 23. The ADSP-21xx connects the motion's TFS and RFS together, with TFS set as output and RFS set as input. The DSP operates in alternate frame mode and sets the motion control registers as described in Table 7. The frame sync signal generated on the TFS is connected to the CS, and as with all signal processing applications, equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling rate of the ADC, and in some cases, equidistant sampling cannot be achieved.

The timer register is loaded with a value that will provide an interrupt at the desired sampling interval. When an interrupt is received, a value is sent with TFS/DT (ADC control word). TFS is used to control RFS to read data. The frequency of the serial clock is set in the SCLKDIV register. When an instruction to transmit with TFS is given (ie AX0=TX0), check the status of SCLK. Before the transfer begins, the DSP waits for SCLK to go high, low, and high again. If the timer and SCLK values are chosen such that the instruction to be sent occurs on or near the rising edge of SCLK, the data can be sent, or it can wait until the next clock edge.

This situation results in non-equidistant sampling since the transfer instruction occurs on the edge of SCLK. If the number of sclks between interrupts is an integer N, equidistant sampling is implemented by the DSP.

AD7887 to DSP56xxx

The connection diagram in Figure 24 shows how the AD7887 connects to the SSI (Synchronous Serial Interface) of the Motorola DSP56xxx family of DSPs. SSI operates in synchronous mode (SYN bit in CRB = 1), internally generated 1-bit clock cycle frame synchronization of Tx and Rx (FSL1 bit = 1 and FSL0 bit = 0 in CRB). Set the word length to 16 by setting bits WL1=1 and WL0=0 in the CRA. An inverter is also required between the SCLK pins of the DSP56xxx and the SCLK pins of the AD7887, as shown in Figure 24.

AD7887 to MC68HC11

The Serial Peripheral Interface (SPI) on the MC68HC11 is configured for master mode (MSTR=1) when the clock polarity bit (CPOL)=1 and the clock phase bit (CPHA)=1. SPI is configured by writing to the SPI Control Register (SPCR) - see Freescale Semiconductor, Inc.'s M68HC11 Reference Manual for more information. Serial transfers occur as two 8-bit operations. The connection diagram is shown in Figure 25.

AD7887 to 8051

A serial interface can be implemented using the data port on the 8051. This allows full duplex serial transmission. The technique consists of bit tapping an input/output port (eg, P1.0) to generate a serial clock, and using two other input/output ports (eg, P1.1 and P1.2) to shift data in and out, See Figure 26.

AD7887 to PIC16C6x/PIC16C7x

The PIC16C6x Synchronous Serial Port (SSP) is configured as an SPI master with the clock polarity bit set to 1. This is done by writing to the Synchronous Serial Port Control Register (SSPCON). Please refer to the PIC16/PIC17 Microcontroller User's Manual. Figure 27 shows the hardware connections required to interface with the PIC16C6x/PIC16C7x. In this example, the input/output port RA1 is used to pulse CS. The microcontroller transfers only 8 bits of data per serial transfer operation. Therefore, two consecutive read/write operations are required.

Application Tips

Grounding and Arrangement

As shown in Figure 7, the AD7887 is very immune to noise on the power supply. However, care should still be taken when it comes to grounding and layout.

The design of the printed circuit board housing the AD7887 should keep the analog and digital sections separate and confined to certain areas of the board. This facilitates the use of easily separated ground planes. The minimum etch technique is usually best for the ground plane because it produces the best shielding. The digital and analog ground planes should only be connected in one location, as close as possible to the ground pin of the AD7887. If the AD7887 is in a system where multiple devices require an AGND to DGND connection, the connection should still be made at only one point, the star ground, as close as possible to the AD7887. Avoid running digital lines under the device as this will couple noise onto the die. The analog ground plane should be allowed to operate under the AD7887 to avoid noise coupling. The power lines to the AD7887 should use as large traces as possible to provide a low impedance path and reduce the effect of faults on the power lines. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to the rest of the board, and clock signals must not run near the analog inputs. Avoid crossover of digital and analog signals. The traces on opposite sides of the board should be at right angles to each other. This reduces feedthrough effects through the board. Microstrip technology is by far the best approach, but double-sided panels are not always possible. In this technique, the component side of the board is dedicated to the ground plane and the signals are placed on the solder side.

Good decoupling is also important. All analog supplies should be separated from 10µF tantalum and in parallel with 0.1µF capacitors to AGND. To get the best results from these decoupling components, they must be placed as close to the device as possible, ideally right against the device.

Dimensions

1. Z = RoHS compliant parts, # indicates lead-free products, which can be top or bottom marks.

2, W = meet the requirements of automotive applications.

3. The linear error here refers to the integral linear error.

automotive products

The AD7887W model can be used in control manufacturing to support the quality and reliability requirements of automotive applications. Note that the specifications for this model may differ from the commercial model; therefore, designers should carefully review the Specifications section of this data sheet. Only the automotive grade products shown are available for automotive applications. For specific product ordering information, please contact your local Analog Devices account representative for a specific vehicle reliability report for this model.