The HI5860 is a 12-bit, 125 +MSPS (each second), high-speed, low-power, D/A converter implemented using advanced CMOS technology. Operating from a single +3V to +5V supply, the converter delivers 20mA full-scale output current and includes edge-triggered CMOS input data latches. Good frequency domain performance is obtained with low fault energy using a segmented current source architecture. This device is a complement to the CommLink HI5x60 and HI5x28 family of high-speed converters, including 8, 10, 12, and 14-bit devices.

feature

throughput. 125+ ms

low power. 175mW at 5V, 32mW at 3V (100MSPS)

Integral linearity error (typical). LSB ±0.5

Adjustable full-scale output current. 2mA to 20mA

Internal 1.2V Bandgap Reference Voltage

Single supply from +5V to +3V

Power down mode

CMOS compatible input

Excellent spurious free dynamic range (76dBc, fS=50MSPS, fOUT=2.51MHz)

Excellent multi-tone intermodulation distortion

application

Base Station (Cellular, WLL)

Medical/Testing Instruments

wireless communication system

direct digital frequency synthesis

signal reconstruction

high resolution imaging system

Arbitrary Waveform Generator

Absolute Maximum Ratings Thermal Information

Digital supply voltage DVDD to DCOM. +5.5V

Analog supply voltage AVDD to ACOM. +5.5V

Ground, ACOM to DCOM. -0.3V to +0.3V

Digital input voltage (D11-D0, CLK, sleep). DVD+0.3V

Reference input voltage range. Average voltage +0.3V

Analog output current (IOUT). 24 mA

operating conditions

temperature range. -40oC to 85oC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC package. 75

TSSOP package. 100

Maximum junction temperature 150 degrees Celsius

Maximum storage temperature range -65 degrees Celsius to 150 degrees Celsius

Maximum lead temperature (soldering 10s) 300 degrees Celsius (SOIC - lead only)

CAUTION: Stresses exceeding those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Installation under the above or any other conditions stated in the operating section of this specification is not implied.

Note:

1. θJA is measured in free air with components mounted on the evaluation PC board

Electrical Specifications AVDD=DVDD=+5V (unless otherwise stated), VREF=internal 1.2V, IOUTFS=20mA, TA=25oC for all typical values

Electrical Specifications AVDD=DVDD=+5V (unless otherwise stated), VREF=internal 1.2V, IOUTFS=20mA, TA=25oC for all typical values (continued)

Electrical Specifications AVDD=DVDD=+5V (unless otherwise stated), VREF=internal 1.2V, IOUTFS=20mA, TA=25oC for all typical values (continued)

notes:

2. Gain error is measured as the error in the ratio of the full-scale output current to the current through RSET (typically 625µA). Ideally the ratio should be 32.

3. Parameters guaranteed by design or characterization, not production tested.

4. Spectral measurement with differential transformer coupled output and no external filtering.

5. Measured with a clock of 50MSPS and an output frequency of 10MHz.

6. Measured with a clock of 100MSPS and an output frequency of 40MHz.

7. Measured with a clock of 125MSPS and an output frequency of 10MHz.

8. See Normative Definitions.

9. It is recommended to reduce the output current to 12mA or less to maintain optimum performance when operating below 3V. DVD and AVDD don't have to be equal.

canonical definition

Differential Linearity Error, DNL, is the step output deviation from code to code. The ideal step size should be 1 LSB. DNL specifications less than or equal to 1 LSB guarantee monotonicity. Measure the full-scale gain drift by setting the data input to all logic highs (all 1s) and measure the output voltage from TMIN to TMAX over temperature through a known resistance. It is defined as the maximum deviation. From values measured at room temperature to measurements at TMIN or TMAX. Units are parts per million FSR (full scale range) per oC. Full-scale gain error, which is the ideal ratio of 32 errors between the output current and the full-scale adjustment current (via RSET). The integrated linearity error, INL, is the worst measured deviation from the best-fit straight line data at the instance point along the transmission curve. Internal reference voltage drift, defined as the maximum deviation of the room temperature measurement to the value measured at TMIN or TMAX. The unit is ppm/oC. By setting the data inputs to all logic lows (all 0s) and through a known resistance as the temperature goes from TMIN to Lynx.

It is defined as the maximum deviation from the value. Either TMIN or TMAX is measured at room temperature. Units are ppm (full scale range) of FSR per degree Celsius. Offset error, by setting the data input to logic low (all 0s) and passing a known resistance. The offset error is defined as a maximum value. Deviation of output current from 0 mA value. The output settling time is the time it takes for the output to stabilize within the specified measurement error range from the start of the output transition. This measurement is done by switching the quarter scale. Due to the parallel connection, the termination impedance is 25Ω for the output and 50Ω for the input of the resistive oscilloscope on a 50Ω load. This also helps to address the specified error band without overdriving the scope. The output voltage conforms to the range, which is the voltage limit imposed on the output. The output impedance should be chosen such that the voltage does not violate the compliance range. Power supply rejection, using a single power supply to measure the supply. The nominal +5V variation of the power supply is ±10%, and the variation of the DAC full-scale output is noted.

The reference input is multiplied by the bandwidth, defined as the 3dB bandwidth of the voltage reference input. It was measured using a sine waveform as an external reference with the digital input set to 1 and the frequency increased until the amplitude of the output waveform was -3dB of the original value of 0.707. Single point fault zone, whether switching transients occur at the output during code transitions. It is measured as the area under the overshoot portion of the curve expressed as a volt-time specification. This is converted with a single code across the main current source. The spurious-free dynamic range, SFDR, is the frequency window specified by the harmonically or dissonantly correlated stimulus of the difference in amplitude from the fundamental signal to the maximum signal. Total Harmonic Distortion, THD, is the RMS ratio of the fundamental output signal to the first five harmonic components.

Detailed description

HI5860 is a 12-bit current output CMOS digital to analog converter converter. Its maximum update rate is 125+MSPS and CAN. The recommended range is +3V to +5V for powering from a single or dual supply in . With clock run rates may be higher than 125MSPS; contact factory for more information. Power consumption is less than 180mW and 125ms/sec when using +5V power supply. The architecture is based on a current source configuration by reducing the amount of current through the primary switch. On an architectural source or binary-weighted resistor ladder that contains all binary-weighted currents, the converter may have a large amount of current diverted at some worst-case transition points (such as mesoscale and quarter-scale transitions. Greatly By reducing the amount of current switching for some "main" conversions, the overall failure of the converter is greatly reduced, improving resolution time, transient problems, and accuracy. The digital inputs and terminal HI5860 digital inputs are guaranteed to reach CMOS levels. Threshold, supply voltage is 3V. The buffer is about half the supply voltage. This internal register is updated on the rising edge of the clock. To minimize reflections, terminate the implementation appropriately. If the line input driving the clock and digital is a long 50Ω line, then a 50Ω line Termination resistors should be connected as close as possible to the converter input to the digital ground plane (if separate grounds are used). These termination resistors may not be needed as long as the digital waveform source is within a few inches of the DAC. Separate digital and analog grounds should be used for the ground plane. All digital functions of the equipment and their corresponding components shall be located on the digital ground and terminate in the digital ground plane. For analog components and analog ground.

Noise reduction

To minimize power supply noise, 0.1µF capacitors should be placed as close as possible to the converter's power supply pins, AVDD and DVD. Also, layout designs using separate digital and analog ground capacitors should be terminated to digital ground DVD and analog ground for AVDD. Additional filtering is recommended using on-board power supplies. The internal voltage reference of the voltage reference device has a nominal value of +1.2V with a drift coefficient over the full temperature range of the converter. It is recommended that a 0.1µF capacitor should be placed as close as possible to the REFIO pin, connected to analog ground. Return pin (16) Select reference. Internal reference can be selected if pin 16 is tied low (ground). If an external reference is required, pin 16 should be tied high (analog supply voltage) and the external reference voltage REFIO, pin 17. The full-scale output current of the converter is the voltage reference used and the setter. IOUT should be in the range of 2mA to 20mA, although operation below 2mA is possible, but performance is degraded. If using the internal reference, VFSADJ will be equal to approximately 1.2V (pin 18). If an xref is used, VFSADJ will be equal to the xref. Calculate IOUT (full scale) as: IOUT (full scale) = (VFSADJ/RSET) X 32. If an internal reference voltage (1.2V) and a 1.91kΩ RSET resistor are used, the input encoding of the output current will look like the following

output

IOUTA and IOUTB are complementary current outputs. The sum of these two currents is always equal to the full-scale output current minus 1 LSB. If single-ended use is required, a load resistor can be used to convert the output current to voltage. Grounding or equivalent termination is recommended for unused outputs. The voltage developed at the output must not violate the output voltage compliance range of -0.3V to 1.25V.RLOAD (impedance should be selected to load each current output) so that the desired output voltage is matched with the output full scale current. If the line impedance is known to drive, the output load resistor should be chosen to match this impedance. The output voltage equation is: VOUT = output X load. These outputs can be used in differential to single-ended arrangements for better harmonic rejection. The SFDR measurements in this datasheet use a 1:1 transformer on the DAC output (see Figure 1). When the center tap is grounded, the output swing 22 at pin 21 is biased at zero volts. Loaded as shown in Figure 1 will be at full scale if the DAC's output current is set to 20mA.

VOUT=2xIOUT x REQ, where REQ is ~12.5O. Allowing the center tap to float will result in the same transformer output, however, the output pin of the DAC will have positive DC offset. Because the DAC output voltage compliance range is 0.3V to +1.25V, the center tap may need to be left floating or a DC offset that increases the amount of signal swing is available. The 500 load of the transformer output represents the input impedance of the spectrum analyzer.