feature

AD5304 : 4 buffered 8-bit DACs in 10-lead MSOP and 10-lead LFCSP; Type A, W: ±1 LSB INL, Type B: ±0.625 LSB INL; AD5314 : 4 buffered 10-bit DACs, 10-lead MSOP and 10-lead LFCSP; A, W versions: ±4 LSB INL, B version: ±2.5 LSB INL; AD5324: 4 buffered 12-bit DACs, 10-lead MSOP and 10-lead LFCSP; A, W versions: ±6 LSB input, Type B: ±10LSB input Low power operation: 500 μA@3V, 600 μA@5V 2.5V～5.5V power supply; monotonicity guaranteed for all codes by design, power as low as 80mA@3V, 200mA @5V Double Buffered Input Logic Output Range: 0 V to VREF Power-on Reset to 0 V; Simultaneous Update Output (LDAC Function) Low Power, SPI, QSPI™-, MicroWire™-, and DSP-compatible 3-wire Serial interface chip, rail-to-rail output buffer amplifier temperature range -40°C to +105°C, suitable for automotive applications.

application

Portable battery powered instruments; digital gain and offset adjustment' programmable voltage and current sources; programmable attenuators; industrial process control.

General Instructions

The AD5304/AD5314/AD5324 are four 8-bit, 10-bit and 12-bit buffered voltage output DACs in 10-wire MSOP and 10-wire LFCSP packages that operate from a single 2.5V to 5.5V and consume 500µA at 3V . Its on-chip output amplifier allows rail-to-rail output swing at a slew rate of 0.7 V/µs. Uses a 3-wire serial interface; it operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI, Microwire and DSP interface standards.

The references for the four DACs originate from one reference pin. Using the software LDAC function, the outputs of all DACs can be updated simultaneously. These parts include a power-on reset circuit and ensure that the DAC outputs up to 0v of power and remains there until a valid write is made to the device. These parts include a power-down feature that reduces the device's current consumption to 200mA @ 5V (80mA @ 3V).

The low power consumption of these parts during normal operation makes them ideal for portable battery-operated devices. Power consumption is 3mw at 5v, 1.5mw at 3v, and drops to 1µW in power-down mode.

Typical performance characteristics

the term

Relative Accuracy or Integral Nonlinearity (INL)

For a DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation in the LSB of a straight line through the endpoints of the DAC transfer function. Typical INL and code diagrams are shown in Figure 5, Figure 6, and Figure 7.

Differential nonlinearity

Differential Nonlinearity (DNL) is the difference between the measured variation of any two adjacent codes and the ideal 1lsb variation. The specified differential nonlinearity of ±1 LSB sheet guarantees monotonicity. This DAC is guaranteed to be mono by design. Typical DNL and code diagrams are shown in Figure 8, Figure 9, and Figure 10.

offset error

This is a measure of the offset error of the DAC and output amplifier. It is expressed as a percentage of full scale.

gain error

This is a measure of the span error of the DAC. It is the deviation of the slope of the actual DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range.

offset error drift

This is a measure of offset error as a function of temperature. Expressed in (ppm of full scale)/°C.

Gain Error Drift

This is a measure of gain error as a function of temperature. Expressed in (ppm of full scale)/°C.

power supply rejection ratio

This shows how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to the change in VDD for the full-scale output of the DAC. It is measured in decibels. VREF remains at 2v and VDD varies by ±10%.

DC crosstalk

This is the DC change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and the output of the other DAC. It is expressed in microvolts.

reference feedthrough

This is the ratio of the signal amplitude at the DAC output to the reference input when the DAC output is not being updated. It is expressed in decibels.

Major Code Transition Failure Energy

The primary code transition fault energy is the pulse energy injected into the analog output when the code in the DAC register changes state. It is usually designated as a fault region in nV-s and transitions in major carry (011...11 to 100...00 or 100...00 to 011...11) yes.

digital feedthrough

Digital feedthrough is a measurement of the pulses injected into the DAC's analog output from the device's digital input pins when the DAC output is not being written (sync held high). It is specified in nV-s and is measured on a digital input pin with a worst-case change (eg, from 0 to 1 or from 0 to 1).

digital crosstalk

This is a glitch pulse that is midscale transferred to the output of one DAC in response to a full-scale code change in the input register of the other DAC (all 0s to all 1s and vice versa). It is represented by nV-s.

DAC-to-DAC crosstalk

This is a fault pulse transferred to the output of one digital to analog converter due to a change in the digital code of one digital to analog converter followed by a change in the output of another digital to analog converter. This includes digital and analog crosstalk. Measured by loading one DAC with a full-scale code change (all 0s to all 1s and vice versa) with the LDAC bit set low and monitoring the output of the other DAC. The fault energy is expressed in nV-s.

Double the bandwidth

Amplifiers within a DAC have limited bandwidth. Multiplying bandwidth is one measure. A sine wave on the reference appears in the output (loading the full-scale code to the DAC). The octave bandwidth is the frequency at which the output amplitude drops 3db below the input.

Total Harmonic Distortion (THD)

This is the difference between an ideal sine wave and a decaying sine wave using a DAC. The sine wave is used as a reference for the DAC, and THD is a measure of the harmonics of the DAC's output. It is measured in decibels.

theory of operation

Function description

The AD5304/AD5314/AD5324 are four-resistor string DACs fabricated on a CMOS process with 8-, 10-, and 12-bit resolutions, respectively. Each contains four output buffer amplifiers and is written over a 3-wire serial interface. They operate from a single supply of 2.5v to 5.5v, and the output buffer amplifier provides rail-to-rail output swing at a slew rate of 0.7v/µs. The four DACs share a reference input pin. These devices feature a programmable power-down mode in which all DACs can be completely shut down with high-impedance outputs.

digital to analog

The structure of a DAC channel consists of a resistor string DAC and an output buffer amplifier. The voltage at the REFIN pin provides the reference voltage for the DAC. Figure 30 shows a block diagram of the DAC architecture. Since the input encoding of the DAC is straight binary, the ideal output voltage is given by:

Where: D=Load into DAC register: 0–255 (8 bits) for AD5304; 0–1023 (10 bits) for AD5314; 0–4095 (12 bits) for AD5324; N=DAC resolution.

resistor string

The resistor string section is shown in Figure 31. It's just a string of resistors, each with a value of R. The digital code loaded into the DAC register determines which node on the string the voltage is tapped into the output amplifier. The voltage is cut off by closing a switch to connect the string to the amplifier. Because it is a string of resistors, monotonicity is guaranteed.

DAC reference input

Four DACs have a reference input pin. Quoted input is not buffered. The user can have a reference voltage as low as 0.25 volts or as high as VDD, as there are no limitations due to the head space or foot space requirements of any reference amplifier. It is recommended to use a buffered reference (for example, REF192) in an external circuit. The input impedance is typically 45 kΩ.

output amplifier

The output buffer amplifier is capable of generating rail-to-rail voltages at its output with an output range of 0v to VDD when the reference voltage is VDD. It is capable of driving 2 kΩ loads to GND or VDD in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier are shown in Figure 15.

The slew rate is 0.7v/µs, and the half-scale settling time is ±0.5lsb (eight bits) of 6µs.

power-on reset

The AD5304/AD5314/AD5324 have a power-on-reset function to power up in a defined state. The power-on state uses normal operation and the output voltage is set to 0 V.

Both the input register and the DAC register are filled with zeros and remain zero until a valid write sequence is made to the device. This is especially useful for applications where it is important to know the state of the DAC output when the device is powered up.

serial interface

The AD5304/AD5314/AD5324 are controlled by a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards.

input shift register

The input shift register is 16 bits wide. Data is loaded into the device as a 16-bit word under the control of the serial clock input SCLK. The timing diagram for this operation is shown in Figure 2. A 16-bit word consists of 4 control bits and 8, 10, or 12 bits of DAC data, depending on the device type. Data is loaded MSB first (bit 15), the first two bits determine whether the data is for DACA, DAC B, DAC C, or DAC D. Bit 13 and Bit 12 control the operating mode of the DAC. Bit 13 is PD and determines whether the part is in normal mode or power down mode. Bit 12 is LDAC and controls when the DAC registers and outputs are updated.

address and control bits

PD 0: All four DACs go into power down mode and consume only 200mA @ 5V. The DAC output goes into a high impedance state.

1: Normal operation.

LDAC 0: All four DAC registers, therefore, all DAC outputs are updated simultaneously when the write sequence is complete.

1: Only the address input registers are updated. The contents of the DAC register have not changed.

The AD5324 uses all 12 bits of DAC data; the AD5314 uses 10 bits, ignoring the 2 LSB bits. The AD5304 uses 8 bits, ignoring the last 4 bits. The data format is straight binary, with all 0s corresponding to 0 V output and all 1s corresponding to full-scale output (VREF-1 LSB).

The sync input is a level-triggered input used as a frame sync signal and chip enable. Data can be transferred to the device only when sync is low. To initiate serial data transfer, set SYNC low to be synchronized to the minimum falling edge of SCLK to set time t4. When sync goes low, serial data is transferred into the device input shift register on the falling edge of SCLK for 16 clock pulses. Any data and clock pulses after the 16 falling edges of SCLK are ignored because the SCLK and DIN input buffers are powered down. No more serial data transfers will take place until high-low synchronization occurs again. After the falling edge of 16 SCLK pulses, high synchronization can be performed, observing the time t7 from the minimum SCLK falling edge to the synchronization rising edge. After the serial data transfer is complete, the data is automatically transferred from the input shift register to the selected digital-to-analog converter. If a high sync occurs before the 16 falling edge of SCLK, the data transfer is aborted and the DAC input registers are not updated. When data is transferred to the three DAC input registers, all DAC registers and all DAC outputs are updated simultaneously by setting LDAC low when writing to the remaining DAC input registers.

Low power serial interface

To further reduce the power consumption of the device, the interface is only fully powered up when the device is being written to (i.e., on the falling edge of synchronization). Once the 16-bit control word is written to the part, the SCLK and DIN input buffers are powered down. They only power up again when the sync drops.

Double buffered interface

The AD5304/AD5314/AD5324 DACs have a double-buffered interface consisting of two sets of register input registers and the DAC registers. The input register is directly connected to the input shift register and transfers the digital code to the associated input register upon completion of a valid write sequence. The DAC register contains the digital code used by the resistor string.

Access to the DAC register is controlled by the LDAC bits. When the LDAC bit is set high, the DAC register is latched, so the input register can change state without affecting the contents of the DAC register. However, when the LDAC bit is set low, all DAC registers are updated after completing the write sequence.

This is useful if the user needs to update all DAC outputs simultaneously. The user can write to the three input registers individually, then by setting the LDAC bit low when writing to the remaining DAC input registers, all outputs are updated simultaneously.

These sections contain an additional feature that the DAC register will not be updated unless the input register of the DAC register has been updated since the last time LDAC was low. Normally, when LDAC is low, the DAC register is filled with the contents of the input register. In the case of the AD5304/AD5314/AD5324, this section updates the DAC registers only if the input registers have been changed since the last time the DAC registers were updated, eliminating unwanted digital crosstalk.

Power down mode

The AD5304/AD5314/AD5324 have low power consumption, consuming only 1.5MW from a 3V supply and 3MW from a 3V, 5V supply. When the DAC is not in use, power consumption can be further reduced by placing it in power down mode (selected by 0 on Bit 13 (PD) of the control word).

When the PD bit is set to 1, all DACs operate normally and the typical power consumption is 600µA at 5 V (500µA at 3 V). However, in power down mode, the supply current drops to 200 mA at 5 V (80 mA at 3 V) when all DACs are powered down. Not only does the supply current drop, but the output stage switches from inside the amplifier's output, leaving it open. The advantage of this is that when the part is in power down mode, the output is in three states and provides a defined input condition for anything connected to the output of the DAC amplifier. The output stage is shown in Figure 35.

When the power-down mode is activated, the bias generator, output amplifier, resistor string and all other associated linear circuits are turned off. However, when power is removed, the contents of the registers are not affected. When VDD=3V, the output power drop time is usually 2.5μs, VDD=5V, 5μs. This is the time from the fall of 16 SCLK pulses until the output voltage deviates from its power-down voltage. Figure 22 shows a graph.

Microprocessor interface

AD5304/AD5314/AD5324 to ADSP-21xx

Figure 36 shows the serial interface between the AD5304/AD5314/AD5324 and the ADSP-21xx family. The ADSP-21xx is set to operate in motion transmission alternate frame mode. The ADSP-21xx Motion Edition is programmed through motion control registers and must be configured as follows: internal clock operation, active low frame, and 16-bit word length. After enabling motion, a transfer is initiated by writing a word to the Tx register. Data is clocked to the AD5304/AD5314/AD5324 on each rising edge of the DSP serial clock and on the falling edge of the digital-to-analog converter SCLK.

AD5304/AD5314/AD5324 to 68HC11/68L11 Interface

Figure 37 shows the serial interface between the AD5304/AD5314/AD5324 and the 68HC11/68L11 microcontroller. The SCK of the 68HC11/68L11 drives the SCLK of the AD5304/AD5314/AD5324, while the MOSI output drives the serial data line (DIN) of the DAC. The sync signal comes from the port line (PC7). The setup conditions for proper operation of this interface are as follows: The 68HC11/68L11 is configured with its CPOL bit set to 0 and the CPHA bit set to 1. When data is transferred to the DAC, the sync line is taken low (PC7). When the 68HC11/68L11 is configured as above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data for the 68HC11/68L11 is transferred in 8-bit bytes with only 8 falling clock edges during the transfer cycle. The data MSB is transferred first. To load data into the AD5304/AD5314/AD5324, after the first 8 bits have been transferred, PC7 is held low, a second serial write is performed to the DAC, and at the end of the process, PC7 is taken high.

AD5304/AD5314/AD5324 to 80C51/80L51 Interface

Figure 38 shows the serial interface between the AD5304/AD5314/AD5324 and the 80C51/80L51 microcontroller. The interface setup is as follows: the TxD of the 80C51/80L51 drives the SCLK of the AD5304/AD5314/AD5324, while the RxD drives the data lines of the serial part. The sync signal again comes from the bit programmable pins on the port. In this case, use port line P3.3. When data is to be sent to the AD5304/AD5314/AD5324, P3.3 is taken low. The 80C51/80L51 transmits data in only 8-bit bytes; therefore there are only 8 falling clock edges in the transmit cycle. To load data into the DAC, P3.3 is held low after the first 8 bits have been sent and a second write cycle is initiated to send the second byte of data. P3.3 rises after this cycle is completed. The 80C51/80L51 outputs serial data in a format with LSB first. The AD5304/AD5314/AD5324 require its data to be received with the MSB as the first bit. The 80C51/80L51 transmit routines take this into account.

AD5304/AD5314/AD5324 to Microwire Interface

Figure 39 shows the interface between the AD5304/AD5314/AD5324 and any Microwire compatible device. Serial data is shifted on the falling edge of the serial clock SK and enters the AD5304/AD5314/AD5324 on the rising edge of SK, which corresponds to the falling edge of the DAC's SCLK.

application information

Typical Application Circuit

The AD5304/AD5314/AD5324 are available over a wide reference voltage range, where the device provides full one-quadrant multiplication capability over a reference range of 0V to VDD.

More typically, these devices use a fixed, accurate voltage reference. References for 5V operation are the AD780 and REF192 (2.5V reference). For 2.5V operation, a suitable external reference is the AD589, a 1.23V bandgap reference. Figure 40 shows a typical setup for the AD5304/AD5314/AD5324 when using external references.

If a 0 V to VDD output range is required, the easiest solution is to connect the reference input to VDD. Since this supply is imprecise and potentially noisy, the AD5304/AD5314/AD5324 can be powered from a reference voltage; for example, use a 5 V reference such as the REF195. The REF195 can output a regulated supply voltage for the AD5304/AD5314/AD5324. The current required from the RIF195 is 600µA of supply current, about 112µA to the reference input seat. There is no load on the DAC output. When the DAC output is loaded, the REF195 also needs to supply current to the load. The total current required (with a 10 kΩ load per output) is: 712 μA + 4 (5 V/10 kΩ) = 2.70 mA.

The load regulation of the REF195 is typically 2ppm/mA, resulting in a 2.7ma current error of 5.4ppm (27µV). This corresponds to 0.0014 LSB errors for 8 bits and 0.022 LSB errors for 12 bits.

Bipolar Operation Using the AD5304/AD5314/AD5324

The AD5304/AD5314/AD5324 are designed for single-supply operation, but a bipolar output range can also be achieved using the circuit in Figure 41. The output voltage range of this circuit is ±5 V. Using the AD820 or OP295 as the output amplifier enables rail-to-rail operation at the output of the amplifier.

The output voltage of any input code can be calculated as follows:

where: D is the decimal equivalent of the code loaded into the DAC; N is the DAC resolution.

REFIN is the reference voltage input:

Optically isolated interfaces for process control applications

The AD5304/AD5314/AD5324 have a versatile 3-wire serial interface, making them ideal for generating precise voltages in process control and industrial applications. The AD5304/AD5314/AD5324 may need to be isolated from the controller due to noise, safety requirements, or distance. This can easily be achieved by using opto-isolators, providing isolation in excess of 3 kV. The actual attainable data rate is limited by the optocoupler type selected. The serial loading structure of the AD5304/AD5314/AD5324 makes them ideal for optoisolated applications. Figure 42 shows the opto-isolated interface of the AD5304, where DIN, SCLK, and SYNC are driven by optocouplers. The power supply to the components also needs to be isolated. This is done by using a transformer. On the DAC side of the transformer, a 5v regulator provides the 5v supply required by the AD5304.

Decode Multiple AD5304/AD5314/AD5324S

The sync pins on the AD5304/AD5314/AD5324 can be used to decode multiple DACs in an application. In this application, all DACs in the system receive the same serial clock and serial data, but SYNC can only be active to one of these devices at any time, allowing access to four channels in a 16-channel system. The 74HC139 acts as a 2 to 4 wire decoder to address any DAC in the system. To prevent timing errors, the enable input must be inactive when the encoded address input changes state. Figure 43 shows a diagram of a typical setup for decoding multiple AD5304 devices in a system.

AD5304/AD5314/AD5324 as digitally programmable window detectors

A digitally programmable upper/lower limit detector using the two DACs in the AD5304/AD5314/AD5324 is shown in Figure 44. The upper and lower limits of the test are loaded into DAC A and DAC B, which in turn set the limits on the CMP04. If the signal at the VIN input is not within the programmed window, the LED indicates a fault condition. Similarly, D a C and DAC D can be used for window detection of the second VIN signal.

Power Bypass and Ground

In any circuit where accuracy is important, careful consideration of power and ground return layout helps ensure rated performance. The printed circuit board on which the AD5304/AD5314/AD5324 is mounted is designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5304/AD5314/AD5324 are in a system where multiple devices require an AGND to DGND connection, make the connection at only one point. The star ground point is as close as possible to the device. The AD5304/AD5314/AD5324 have ample supply bypass of 10µF in parallel with 0.1µF on the power supply located as close to the package as possible, ideally facing the device. The 10µF capacitors are of the tantalum bead type. 0.1µF capacitors have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic type that provides a high frequency, low impedance path to ground to handle transient currents generated by internal logic switches.

Use the largest possible traces for the power lines of the AD5304/AD5314/AD5324 to provide a low impedance path and reduce the effect of faults on the power lines. Fast switching signals such as clocks are shielded by digital ground to avoid radiating noise to the rest of the board and never run near the reference input. Avoid crossover of digital and analog signals. The traces on opposite sides of the board are at right angles to each other. This reduces feedthrough effects through the board. Microstrip technology is by far the best, but double sided is not always possible. In this technique, the component side of the board is dedicated to the ground plane, while the signal lines are placed on the solder side.

Dimensions