feature

AD7656 /AD7657/AD7658 Compatible Pin and Software, Reduces Decoupling Requirements 6 Independent ADCs; True Bipolar Analog Input Pin/Software Selectable Ranges: ±0 V, ±5 V Fast Throughput: 250 kSPS iCMOS Processing technology; low power; 140mw, 250ksps, 5v, wideband high noise performance; 88 dB SNR at 10 kHz input frequency on-chip reference and reference buffers; high-speed parallel, serial and daisy-chain interface modes high-speed serial interface; SPI/QSPI Standard 8482 ;/MicroWire™ DSP Compatible Standby Mode: 315 Si W max 64 lead LQFP.

application

Power line monitoring systems; instrumentation and control systems; multi-axis positioning systems.

General Instructions

The AD7656-1/AD7657-1/AD7658-1 are simplified pinout and software compatible versions of the AD7656/AD7657/AD7658. The AD7656-1/AD7657-1/AD7658-1 devices contain six 16-/14/12-bit, fast, low-power successive approximation ADCs designed on a one-package ICMOS® process (industrial CMOS). iCMOS is a process that combines high voltage silicon with submicron CMOS and complementary bipolar technology. It made it possible to develop a range of high-performance analog integrated circuits capable of operating at 33 volts, which was not possible with the previous generation of high-voltage devices. Unlike analog integrated circuits using traditional CMOS processes, iCMOS components can accept bipolar input signals while delivering higher performance, which greatly reduces power consumption and package size.

The AD7656-1/AD7657-1/AD7658-1 have throughputs up to 250 kSPS. These parts contain low noise, broadband track and hold amplifiers that can handle input frequencies up to 4.5 MHz.

The conversion process and data acquisition are controlled by the CONVST signal and the internal oscillator. Three CONVST pins (CONVST A, CONVST B, and CONVST C) allow independent, simultaneous sampling of three ADC pairs. The AD7656-1/AD7657-1/AD7658-1 feature high-speed parallel and serial interfaces that allow the device to interface with a microprocessor or DSP. When the serial interface is selected, each part has a daisy-chain capability that allows multiple ADCs to be connected to a single serial interface. The AD7656-1/AD7657-1/AD7658-1 can accommodate true bipolar input signals within ±4×VREF and ±2×VREF. Each AD7656-1/AD7657-1/AD7658-1 also includes an on-chip 2.5 V reference.

Product Highlights

1. Six 16/14/12-bit 250 kSPS ADCs.

2. Six true bipolar, high impedance analog inputs.

3. High-speed parallel and serial interfaces.

4. Reduced decoupling requirements and bill of materials cost compared to AD7656/AD7657/AD7658 devices.

Typical performance characteristics

the term

Integral Nonlinearity (INL)

The end point of the maximum deviation ADC transfer function for a straight line through. The endpoint transfer function is zero-scale at 1/2 LSB below the first code transition and full-scale at half-LSB above the last code transition.

Differential Nonlinearity (DNL)

The difference between the measured value and the ideal 1 LSB between any two adjacent codes in the ADC changes.

Bipolar Zero Scale Error

Deviation of mid-scale transitions (all 1s to all 0s) from the ideal VIN voltage (i.e. AGND-1 LSB).

Bipolar zero-scale error matching

The difference in bipolar null error between any two input channels.

Positive full-scale error

Deviation of last code transition (011…110 to 011…111) from ideal (+4×VREF−1 LSB, +2×VREF−1 LSB) after adjusting for bipolar zero-scale error.

Positive full-scale error matching

Positive full-scale error difference between any two input channels.

Negative full-scale error

The deviation of the first code transition (10…000 to 10…001) from the ideal (-4×VREF+1 LSB, -2×VREF+1 LSB) after adjusting for bipolar zero-scale error.

Negative full-scale error matching

The difference in negative full-scale error between any two input channels.

Track and hold acquisition time

At the end of the conversion, the track-and-hold amplifier returns to track mode. Track-and-hold capture time is the time it takes for the output of the track-and-hold amplifier to reach its final value (within ±1lsb) after a conversion has ended. See the Track and Hold section for details.

Signal to Noise Ratio (SINAD)

The ratio of signal to (noise + distortion) measured at the output of the analog-to-digital converter. The signal is the rms amplitude of the fundamental wave. Noise is the sum of all non-fundamental signals up to half the sampling frequency (fSAMPLE/2, excluding dc).

The ratio depends on the number of quantization levels in the digitization process: the more levels, the less quantization noise. The theoretical SINAD ratio of an ideal N-bit converter with a sine wave input is given by: SINAD = (6.02 N + 1.76) dB, so the SINAD of the 16-bit converter is 98 dB, the 14-bit converter is 86.04 dB, and the 12 The bit translator is 74 dB.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the harmonics to the fundamental. For the AD7656-1/AD7657-1/AD7658-1, it is defined as:

where: V1 is the rms amplitude of the fundamental; V2, V3, V4, V5 and V6 are the rms amplitudes of the second to sixth harmonics.

Peak harmonics or spurious noise

The ratio of the rms value of the next largest component in the ADC output spectrum (less than or equal to fSAMPLE/2, excluding dc) to the rms value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonic is buried in the noise floor, it is determined by the noise peak.

Intermodulation Distortion

When the input consists of two sine waves of frequencies fa and fb, any active device with nonlinearity produces distortion products at the sum and difference frequencies of mfa±nfb, where m, n = 0, 1, 2, 3 . Intermodulation distortion terms refer to terms where neither m nor n equals 0. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

The AD7656-1/AD765 71/1/AD768-1 were tested using the CCIF standard using two input frequencies near the maximum input bandwidth. In this case, the second-order term is usually at a distance from the original sine wave in frequency, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second- and third-order terms are specified separately. Intermodulation distortion is calculated according to the THD specification, where is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental sum, expressed in decibels.

Isolation between channels

Channel-to-channel isolation is a method of measuring the level of crosstalk between any two channels. It is measured by applying a full-scale 100 kHz sine wave signal to all unselected input channels, and using the 30 kHz signal to determine how much the signal is attenuated in the selected channel.

Power Supply Rejection (PSR)

Changes in the power supply affect full-scale conversion, but do not affect the linearity of the converter. Power supply rejection is the maximum change in the full-scale transition point due to a change in supply voltage from nominal. See the Typical Performance Characteristics section.

in:

Pf is equal to the power at frequency f in the ADC output.

PfS is equal to the power coupled to the VDD and VSS supplies at frequency fSAMPLE.

% Feasibility study report

The %FSR is calculated using the entire theoretical span of the ADC.

Principle of Operation

Converter Details

The AD7656-1/AD7657-1/AD7658-1 are pin and software compatible with the AD7656/AD7657/AD7658 devices with a reduced decoupling version. In addition, the AD7656-1/AD7657-1/AD7658-1 are high-speed, low-power converters that can simultaneously sample six on-chip ADCs. The analog inputs on the AD7656-1/AD7657-1/AD7658-1 can accept true bipolar input signals. The RANGE pin or RNGx bits are used to select ±4×VREF or ±2×VREF as the input range for the next conversion.

Each AD7656-1/AD7657-1/AD7658-1 contains six synthetic aperture radar ADCs, six track-and-hold amplifiers, a 2.5V reference slice, reference buffers, and high-speed parallel and serial interfaces. These parts allow all six ADCs to be sampled simultaneously when the three CONVST pins (CONVST A, CONVST B, and CONVST C) are connected together. Alternatively, the six ADCs can be split into three pairs. Each pair of ADCs has an associated CONVST signal that initiates simultaneous sampling on each pair, four ADCs, or all six ADCs. CONVST A is used to initiate simultaneous sampling on V1 and V2, CONVST B is used to initiate simultaneous sampling on V3 and V4, and CONVST C is used to initiate simultaneous sampling on V5 and V6.

A conversion is initiated by pulsing the CONVST input on the AD7656-1/AD7657-1/AD7658-1. On the rising edge of CONVST, the track-and-hold amplifier of the selected ADC pair is placed into hold mode and a conversion begins. After the rising edge of CONVST, the busy signal goes high, indicating that a conversion is in progress. The conversion clock for the AD7656-1/AD7657-1/AD7658-1 is internally generated and the conversion time for each part is 3 microseconds. Any further CONVST rising edges on CONVST A, CONVST B, or CONVST C are ignored as long as it is busy. The busy signal returns low to indicate the end of the conversion. On a busy falling edge, the track-and-hold amplifier returns to track mode. Data can be read from the output registers via the parallel or serial interface.

track and hold amplifier

The track-and-hold amplifiers on the AD7656-1/AD7657-1/AD7658-1 allow the ADC to accurately convert an input sine wave of full-scale amplitude to 16-/14-/12-bit resolution, respectively. The input bandwidth of the track-and-hold amplifier is greater than the Nyquist rate of the ADC, even when the AD7656-1/AD765 71/1/AD768-1 operate at maximum throughput. These parts can handle input frequencies up to 4.5 MHz.

The track and hold amplifiers simultaneously sample their respective inputs on the rising edge of CONVST. The aperture time of the track and hold amplifier (i.e. the delay time between the external CONVST signal actually entering the hold state) is 10ns. It's nice to match all six tracks and keep the amp on one device and from one device to another. This makes it possible to sample more than six ADCs simultaneously. The end of a conversion is signaled by the falling edge of BUSY, at which point the track-hold amplifier returns to track mode and acquisition time begins.

analog input

The AD7656-1/AD7657-1/AD7658-1 can handle true bipolar input voltages. The logic level on the range pin or the value written to the RNGx bits in the control register determines the analog input range on the AD7656-1/AD7657-1/AD7658-1 for the next conversion. When the range pin or the RNGx bit is 1, the analog input range for the next conversion is ±2 × VREF.

When the RANGE pin or the RNGx bit is 0, the analog input range for the next conversion is ±4 × VREF.

Figure 25 shows the equivalent circuit for the analog input structure of the AD7656-1/AD7657-1/AD7658-1. Two diodes D1 and D2 provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal does not exceed the VDD and VSS supply rails by more than 300 mV. Signals above this value cause these diodes to be forward biased and start conducting current to the substrate. These diodes can draw up to 10mA without causing irreversible damage. Capacitor C1 in Figure 25 is typically about 4pF, mainly due to pin capacitance. Resistor R1 is a lumped element consisting of the on-resistance of the switch (i.e. track and hold switch). This resistance is typically about 3.5 kΩ. Capacitor C2 is the ADC sampling capacitor, and its capacitance is typically 10pf.

The AD7656-1/AD7657-1/AD7658-1 require dual VDD and VSS supplies for the high voltage analog input structure. These supplies must be equal to or greater than the analog input range (see Table 8 for the requirements of these supplies for each analog input range). The AD7656-1/AD7657-1/AD7658-1 require a low voltage AVCC supply of 4.75 V to 5.25 V to power the ADC core, the digital supply requires a DVCC supply of 4.75 V to 5.25 V, and the interface supply requires a V drive supply of 2.7 V to 5.25 V .

To meet the specified performance using the minimum supply voltage of the selected analog input range, the throughput rate may need to be reduced from the maximum throughput rate.

ADC transfer function

The output encoding of the AD7656-1/AD7657-1/AD7658-1 is two's complement. The designed transcoding occurs midway between consecutive integer LSB values, ie, 1/2 LSB, 3/2 LSB. The LSB size is FSR/65536 for the AD7656-1, FSR/16384 for the AD7657-1, and FSR/4096 for the AD7658-1. The ideal transfer characteristics are shown in Figure 26.

The size of the LSB depends on the selected analog input range (see Table 9).

Internal/External Reference

The REFIN/REFOUT pins allow access to the 2.5 V reference voltage of the AD7656-1/AD7657-1/AD7658-1, or allow the connection of an external voltage reference to provide a conversion reference source.

The AD7656-1/AD7657-1/AD7658-1 accommodate a 2.5 V external reference voltage. When applying external references through the REFIN/REFOUT pins, internal references must be disabled and reference buffers must be enabled. Alternatively, an external reference can be applied through the REFCAPx pins, in which case the internal reference should be disabled, it is recommended to disable the reference buffer to save power and minimize crosstalk. After reset, the AD7656-1/AD7657-1/AD7658-1 default to operating in external reference mode with the internal reference disabled and the reference buffer enabled.

Internal references can be enabled in hardware or software mode. To enable the internal reference in hardware mode, set the H/S SEL pin to 0 and the REFEN/ pin to 1. Enable digital information system

Internal reference in software mode, set H/S SEL to 1, and write to the control register, set DB9 of the register to 1. For internal reference mode, separate the REFIN/REFOUT pins with a 1µF capacitor.

The AD7656-1/AD7657-1/AD7658-1 each contain three on-chip reference buffers, as shown in Figure 27. Each of the three ADC pairs has an associated reference buffer. These reference buffers require external decoupling capacitors with 1µF capacitors on the REFCAPA, REFCAPB, and REFCAPC pins. The internal reference buffer can be disabled in software mode by writing to Bit DB8 in the internal control register. If the serial interface is selected, the internal reference buffer can be disabled in hardware mode by setting DB14/REFBUFEN/DIS pin high. If the internal reference and its buffer are disabled, the external buffer reference is applied to the REFCAPx pins.

Typical Wiring Diagram

Figure 28 shows a typical connection diagram for the AD7656-1/AD7657-1/AD7658-1, illustrating the reduction in the number and value of decoupling capacitors required. There are eight AVCC power pins on each part. The AVCC supply is the supply used for the AD7656-1/AD7657-1/AD7658-1 conversion process; therefore, they should be well separated. The AVCC supply applied to the eight AVCC pins can be decoupled using only a 1µF capacitor. The AD7656-1/AD7657-1/AD7658-1 can operate with an internal reference or with an externally applied reference. In this configuration, the assembly is configured to operate with an external reference. The REFIN/REFOUT pins are separated from the 1µF capacitor. Three internal reference buffers are enabled. Each REFCAPx pin is separated from a 1µF capacitor.

If the AVCC and DVCC supplies use the same power supply, place a ferrite or a small RC filter between the supply pins.

The AGND pin is connected to the AGND plane of the system. The DGND pin is connected to the digital ground plane in the system. Connect the AGND and DGND planes together at one location in the system. This connection should be as close as possible to the AD7656-1/AD7657-1/AD7658-1 in the system.

The VDRIVE power supply is connected to the same power supply as the processor. The voltage on VDRIVE controls the voltage value of the output logic signal.

Decouple the VDD and VSS signals with a minimum 1µF decoupling capacitor. These supplies are used in the high voltage analog input structure on the AD7656-1/AD7657-1/AD7658-1 analog inputs.

drive analog input

The driver amplifier, along with the analog input circuitry for the AD7656-1, must meet a 16-bit level (0.0015%) full-scale step input within the AD7656-1's specified 550ns acquisition time. To maintain the signal-to-noise ratio and transition noise performance of the AD7656-1, the noise generated by the driver amplifier needs to be as low as possible. Additionally, the driver needs to have a THD capability suitable for the AD7656-1.

The AD8021 meets these requirements. The AD8021 requires an external compensation capacitor of 10 pF. If a dual version of the AD8021 is required, the AD8022 can be used. The AD8610 and AD797 can also be used to drive the AD7656-1/AD7657-1/AD7658-1.

Interface options

The AD7656-1/AD7657-1/AD7658-1 offer two interface options: a high-speed parallel interface and a high-speed serial interface. The desired interface mode is selected via the SE/PAR SEL pin. The parallel interface can work in word (W/B=0) or byte (W/B=1) mode. In serial mode, the AD7656-1/AD7657-1/AD7658-1 can be configured in daisy-chain mode.

In parallel mode, a read operation only accesses the result associated with the conversion that just occurred. For example, consider the case where CONVST A and CONVST C are switched at the same time but CONVST B is not used. At the end of the conversion process, when BUSY goes low, a read is performed. Applying four read pulses (parallel mode) outputs data from V1, V2, V5 and V6. Since CONVST B is not toggled in this loop, the data in V3 and V4 are not output. However, when in serial mode, all zeros are output in place of ADC results from ADCs that are not included in the conversion cycle. See the Serial Interface section for more information.

Parallel interface (SE/PAR SEL=0)

The AD7656-1/AD7657-1/AD7658-1 consist of six 16-/14-/12-bit ADCs, respectively. By connecting all three CONVST pins (CONVST A, CONVST B, and CONVST C) together, all six ADCs can be sampled simultaneously. The AD7656-1/AD7657-1/AD7658-1 need to see a CONVST pulse to initiate a conversion; this should include both the CONVST falling edge and the CONVST rising edge. The rising edge of CONVST initiates a synchronous conversion on the selected ADC. The AD7656-1/AD7657-1/AD7658-1 each contain an on-chip oscillator that performs conversions. The conversion time, tCONV, is 3 microseconds. The busy signal goes low to indicate the end of the conversion. The falling edge of the busy signal is used to put the track hold amplifier into track mode.

The AD7656-1/AD7657-1/AD7658-1 also allow six ADCs to be converted in pairs simultaneously by independently pulsing the three converter pins. CONVST A is used to initiate synchronous conversions on V1 and V2, CONVST B is used to initiate synchronous conversions on V3 and V4, and CONVST C is used to initiate synchronous conversions on V5 and V6. The conversion results of the simultaneously sampled ADCs are stored in the output data registers. Note that once a rising edge occurs on either CONVST pin to initiate a conversion, further CONVST rising edges on any CONVST pin will be ignored while the busy state is high.

Data can be read from the AD7656-1/AD7657-1/AD7658-1 via a parallel data bus with standard CS and RD signals (W/B=0). To read data on the parallel bus, TIESE/PAR SEL is low. The CS and RD input signals are gated internally to enable conversion results to the data bus. When both CS and RD are logic low, the data lines DB0 to DB15 remain in a high impedance state.

The CS signal can be permanently clamped low and the RD signal can be used to access the conversion result. After the busy signal goes low, a read operation is possible. The number of read operations required depends on the number of ADCs sampling simultaneously (see Figure 29). If CONVST A and CONVST B are low at the same time, four read operations are required to obtain conversion results from V1, V2, V3, and V4. If CONVST A and CONVST C are low at the same time, four read operations are required to obtain conversion results from V1, V2, V5, and V6.

The conversion results are output in ascending order. For the AD7657-1, DB15 and DB14 contain two leading 0s, and DB[13:0] outputs the 14-bit conversion result. For the AD7658-1, DB[15:12] contains four leading 0s, and DB[11:0] outputs the 12-bit conversion result.

When using the three CONVST signals to independently initiate conversions on three ADC pairs, once a rising edge occurs on any one CONVST pin to initiate a conversion, then any further CONVST rising edges on any CONVST pin are ignored when busy.

While it is possible to initiate a conversion during a read sequence, it is not recommended because doing so may affect the performance of the conversion. For the specified performance, it is recommended to perform a read after conversion. For unused input channel pairs, connect the associated CONVST pin to VDRIVE.

If only an 8-bit bus is available, the AD7656-1/AD7657-1/AD7658-1 parallel interface can be configured to operate in byte mode (W/B=1). In this configuration, the DB7/HBEN/DCEN pins have the HBEN function. Each channel conversion result of the AD7656-1/AD7657-1/AD7658-1 can be accessed in two read operations, each of which provides eight bits of data on DB15 to DB8 (see Figure 30). The HBEN pin determines whether a read operation first accesses the high or low byte of the 16-bit conversion result. To always access the low-order bytes on DB15 to DB8 first, connect the HBEN pin to the low-order bits. To always access the high order bytes on DB15 to DB8 first, connect the HBEN pin to the high order. In byte mode, when all three CONVST pins are pulsed together to initiate simultaneous conversions on all six ADCs, 12 read operations are required to read six 16/14/12-bit conversion results. DB[6:0] should remain unconnected in byte mode.

software selection for adc

The H/S select pin determines the source of the ADC combination to be sampled simultaneously. When the H/S select pin is logic low, the combination of channels to be sampled simultaneously is determined by the CONVST A, CONVST B, and CONVST C pins. When the H/S SEL pin is logic high, the combination of channels selected for simultaneous sampling is determined by the contents of the DB15 to DB13 control registers. In this mode, the control register must be written.

The control register is an 8-bit write-only register. Data is written to this register using the CS and WR pins and the DB[15:8] data pins (see Figure 31). Control Register To select which ADC pair to sample simultaneously, set the corresponding data line high during a write operation.

The AD7656-1/AD7657-1/AD7658-1 control registers allow various ranges to be programmed on each ADC pair. DB12 to DB10 in the control registers are used to program the range on each ADC pair.

After a reset on the AD7656-1/AD7657-1/AD7658-1, the control register contains all 0s. The CONVST A signal is used to initiate a synchronous conversion on the channel combination selected by the control register. When operating in software mode (H/S selection = 1), the CONVST B and CONVST C signals can be limited to low bits. The number of read pulses required depends on the number of ADCs selected in the control register and whether the device is operating in word or byte mode. The conversion results are output in ascending order.

During the write operation, the data bus bit DB15 to the data bus bit DB8 are bidirectional, when RD is logic high and CS and WR are logic low, they become the inputs to the control register. When WR goes logic high, the logic states on DB15 to DB8 are latched into the control register.

Change the analog input range (H/S selection = 0)

The AD7656-1/AD7657-1/AD7658-1 range pins allow the user to select ±2 × VREF or ±4 × VREF as the analog input range for the six analog inputs. When the H/S SEL pin is low, the logic state of the range pin is sampled on the falling edge of the busy signal to determine the range for the next simultaneous conversion. When the range pin is logic high on the falling edge of the busy signal, the range for the next conversion is ±2 × VREF. When the range pin is logic low on the falling edge of the busy signal, the range for the next conversion is ±4 × VREF. After the reset pulse, the range is updated on the first falling busy edge.

Change the analog input range (H/S selection = 1)

The range can be changed by writing to the control register when the H/S select pin is high. DB[12:10] in the control register is used to select the analog input range for the next conversion. Each analog input pair has an associated range bit, allowing independent ranges to be programmed on each ADC pair. When the RNGx bit is set to 1, the range for the next conversion is ±2 × reference voltage. When the RNGx bits are set to 0, the range for the next conversion is ±4 × VREF.

Serial interface (SE/PAR SEL=1)

The AD7656-1/AD7657-1/AD7658-1 use their on-chip trimmed oscillators to simultaneously convert the selected channel pair on the rising edge of CONVST by pulsing one, two, or all three CONVST signals. After the rising edge of CONVST, the BUSY signal goes high, indicating that a conversion has begun. It returns low when the conversion is complete, 3 microseconds later. Any further CONVST rising edges on CONVST A, CONVST B, or CONVST C will be ignored as long as it is busy. The output registers are loaded with the new conversion result and can be read from the AD7656-1/AD7657-1/AD7658-1. To read the part's data from the serial interface, SE/PAR SEL should be tied high. The CS and SCLK signals are used to transfer data from the AD7656-1/AD7657-1/AD7658-1. These sections have three DOUT pins: DOUT A, DOUT B, and DOUT C. Data can be read from each section using one, two, or all three DOUT lines.

Figure 32 shows six simultaneous conversions and a read sequence using three DOUT lines. Additionally, in Figure 32, 32 SCLK transfers are used to access data from the AD7656-1/AD7657-1/AD7658-1; however, two 16-SCLK individual frame transfers with CS signals can also be used to access three data on the DOUT line. Any other SCLK applied after this will result in all zeros being output. When the serial interface is selected and conversion data is clocked on all three dual output lines, connect DB0/SEL A, DB1/SEL B, and DB2/SEL C to VDRIVE. These pins are used to energize the DOUT A to DOUT C lines, respectively.

Use DOUT A and DOUT B if the conversion data needs to be clocked out on both data output lines. To enable DOUT A and DOUT B, tie DB0/SEL A and DB1/SEL B to VDRIVE and tie DB2/SEL C low. When performing six simultaneous conversions and using only two dual output lines, data from the AD7656-1/AD7657-1/AD7658-1 can be accessed using a 48-SCLK transfer. Any other SCLK applied after this will result in all zeros being output. The read sequence shown in Figure 33 is used to convert simultaneously on all six ADCs using two dual output lines. If conversions occur simultaneously on all six ADCs, and only two dual output lines are used to read the results from the AD7656-1/AD7657-1/AD7658-1, the dual a will output the results from V1, V2, and V5, while Double B will output results from V3, V4 and V6.

Data can also be clocked using only one DOUT row, in which case DOUT A is used to access the conversion data. To configure the AD7656-1/AD7657-1/AD7658-1 to operate in this mode, connect DB0/SEL A to VDRIVE and DB1/SEL B and DB2/SEL C to low. The disadvantage of using only one DOUT line is reduced throughput. Data can be accessed from the AD7656-1/AD7657-1/AD7658-1 using one 96-SCLK transfer, three 32-SCLK single-frame transfers, or six 16-SCLK single-frame transfers. Any other SCLK applied after this will result in all zeros being output. When using the serial interface, tie the RD signal low and leave unused output lines unconnected.

Whether one, two, or three data output lines are used, if the specific CONVST pin is not used during the conversion cycle, all zeros will be output in place of the ADC result even if the associated ADC is not used during the conversion cycle. This means that, for example, if only CONVST B is pulsed and one data output pin is used, 64 sclks are required to access the results of V3 and V4, but if two or three data output lines are used, only 32 sclks are required.

serial read operation

Figure 34 shows the timing diagram for reading data from the AD7656-1/AD7657-1/AD7658-1 when the serial interface is selected. The SCLK input signal provides the clock source for the serial interface. The CS signal goes low to access data from the AD7656-1/AD7657-1/AD7658-1. The falling edge of CS takes the bus out of three states and times out the MSB of the 16-bit conversion result. The adc outputs 16 bits for each conversion result; the data stream of the AD7656-1 consists of 16 bits of conversion data, MSB first. The data stream of the AD7657-1 consists of two leading 0 and 14-bit conversion data, MSB first. The data stream of the AD7658-1 consists of four leading 0s and 12 bits of converted data, MSB first.

The first bit of the conversion result is valid on the first SCLK falling edge after the CS falling edge. The next 15 data bits are clocked on the rising edge of the SCLK signal. Data is valid on the falling edge of SCLK. To access each conversion result, 16 clock pulses must be provided to the AD7656-1/AD7657-1/AD7658-1. Figure 34 shows how to access the conversion result using a 16-SCLK read.

DAISY chain mode (DCEN=1, SE/PAR SEL=1)

When reading conversion data from the AD7656-1/AD7657-1/AD7658-1 using one/two/three dual pins, the DCEN pin can be used to configure the part to operate in daisy-chain mode. This daisy-chain capability allows multiple AD7656-1/AD7657-1/AD7658-1 devices to be cascaded together, which is useful for reducing component count and wiring connections. An example of the connection of two devices is shown in Figure 36. This configuration shows the use of two dual output lines per device. Simultaneous sampling of the 12 analog inputs can use a common CONVST signal. The DB5, DB4, and DB3 data pins are used as DCIN[A:C] data input pins for daisy-chain mode.

The rising edge of CONVST is used to initiate a conversion on the AD7656-1/AD7657-1/AD7658-1. After the busy signal goes low to indicate that the conversion is complete, the user can start reading data from both devices. Figure 37 shows the serial timing diagram when operating two AD7656-1/AD7657-1/AD7658-1 devices in daisy-chain mode.

The CS falling edge is used to frame serial transfers from the AD7656-1/AD7657-1/AD7658-1 devices, take the bus out of three states, and time out the MSB of the first conversion result. In the example shown in Figure 37, all 12 ADC channels are sampled simultaneously. In this example, the conversion result is read using two DOUT lines. CS frame 96-SCLK transmission. During the first 48 sclks, conversion data is transferred from device 2 to device 1. DOUT A on Device 2 transfers the converted data from V1, V2 and V5 to DCIN A in Device 1; DOUT B on Device 2 transfers the conversion results from V3, V4 and V6 to DCIN B in Device 1. During the first 48 sclks, device 1 transmits data to the digital host. DOUT A on Device 1 transfers conversion data from V1, V2, and V5; DOUT B on Device 1 transfers conversion data from V3, V4, and V6. In the last 48 sclks, device 2 dials 0 clock out, and device 1 moves the data dialed in from device 2 in the first 48 sclks into the digital host. This example can also be implemented using 6 individual frame transfers of 16-SCLK if DCEN is held high during the transfer.

Figure 38 shows the timing if two AD7656-1/AD7657-1/AD7658-1 devices are configured in daisy-chain mode and operate using three dual output lines. Assuming that all 12 inputs are sampled at the same time, CS is transmitted in frame 64 SCLK during a read operation. During the first 32 sclks of this transfer, the conversion result from Device 1 is clocked to the digital host and the conversion result from Device 2 is clocked to Device 1. During the last 32 sclks of the transfer, the conversion result from Device 2 clocks out from Device 1 and goes into the digital host, and Device 2 clocks out 0.

The maximum number of devices in the chain is limited by the required throughput per channel, based on application requirements, the SCLK frequency used, and the number of serial data lines used.

Standby/Partial Power-Down Operation Mode (SE/PAR SEL=0 or 1)

Each ADC pair can individually enter partial power-down mode at the end of a conversion by bringing the associated CONVST signal low before the falling edge of BUSY. If the CONVST pin is low when busy goes low, the associated ADC pair only enters partial power down mode when it is actually converting during that cycle, i.e. if that particular CONVST pin is used to trigger a conversion. To power the ADC pair, the CONVST signal should be turned high, telling the ADC pair to power and put the track-and-hold amplifier in track mode. After a partial power-down power-up time, the CONVST signal can receive a rising edge to initiate a valid conversion. In partial power-down mode, the reference buffer remains powered on. When one ADC pair is in partial power-down mode, conversions can still occur on the other fully powered ADCs. At point A of Figure 35, ADC 1 and ADC 2 enter a partial power-down state, while ADC 3 through ADC 6 remain fully powered on. At point B in Figure 35, ADC1 and ADC2 start to power up. Once the desired power-up time has elapsed, a conversion can be initiated on the next rising edge of CONVST, as shown.

The AD7656-1/AD765 71/1/AD765 8-1 have a standby mode that puts the device into a low-power mode (315 μW max). The AD7656-1/AD7657-1/AD7658-1 enter standby mode by driving input STBY logic low and power up again for normal operation by driving STBY logic high. When the AD7656-1/AD7657-1/AD7658-1 are in standby mode, the output data buffer remains functional, which means that the user can continue to access the conversion results of the part. This alternate feature can be used to reduce the average power consumption of the AD7656-1/AD7657-1/AD7658-1 when operating at lower throughput rates. At the end of each conversion, when BUSY goes low, the part can be put into standby and taken out of standby mode before the next conversion. The time for the AD7656-1/AD7657-1/AD7658-1 to come out of standby is called the wake-up time. The wake-up time limits the maximum throughput at which the AD7656-1/AD765 7-1/AD765 8-1 can operate when powered down between conversions.

Application Tips

layout

Design a printed circuit board (PCB) containing the AD7656-1/AD7657-1/AD7658-1 so that the analog and digital sections are separated and confined to different areas of the board.

Use at least one ground plane. It can be generic or split between digital and analog sections. In the case of a split plane, connect the digital and analog grounds in only one place, preferably under the AD7656-1/AD7657-1/AD7658-1, or at least as close to the part as possible.

If the AD7656-1/AD7657-1/AD7658-1 are in a system where multiple devices require an analog-to-digital ground connection, this connection should still only be made at one point (the star ground point), which should be as close as possible to the AD7656 -1/AD7657-1/AD7658-1. Good connection to ground plane. Avoid multiple ground pins sharing a single connection. Each ground pin should use a single via or multiple vias to the ground plane.

Avoid running digital lines under the device as doing so will couple noise onto the die. Allows the analog ground plane to run under the AD7656-1/AD7657-1/AD7658-1 to avoid noise coupling. Shield fast switching signals, such as CONVST or clocks, with digital ground to avoid radiating noise to other parts of the board, and fast switching signals should not run near analog signal paths. Avoid crossover of digital and analog signals. Traces on layers close to the board should run at right angles to each other to reduce the effects of feedthrough through the board.

The power supply lines for the AVCC, DVCC, VDRIVE, VDD, and VSS pins on the AD7656-1/AD7657-1/AD7658-1 should use as large traces as possible to provide a low impedance path and reduce the effect of faults on the power supply lines. Make good connections between the AD7656-1/AD7657-1/AD7658-1 power supply pins and the power supply lines on the board; this should include using one or more vias for each power supply pin.

Good decoupling is also important to reduce the supply impedance of the AD7656-1/AD7657-1/AD7658-1 and reduce the size of the supply spikes. Place decoupling capacitors close to (ideally right across) these pins and their corresponding ground pins. Also, place low ESR 1µF capacitors on each power supply pin, the REFIN/REFOUT pin, and each REFCAPx pin. Avoid sharing these capacitors between pins and use vias to connect the capacitors to the power and ground planes. Also, use wide and short traces between each via and the capacitor pads, or place the vias near the capacitor pads to minimize parasitic inductance. The AD7656-1/AD7657-1/AD7658-1 provide the user with a simplified decoupling solution that is pin and software compatible with the AD7656/AD7657/AD7658. Figure 28 outlines the recommended reduction decoupling required for the AD7656-1/AD7657-1/AD7658-1.

Power configuration

As outlined in the Absolute Maximum Ratings section, the analog inputs should not be applied to the AD7656-1/AD765 71/1/AD765 8-1 until the AD7656-1/AD765 71/1/AD768-1 power supply has been applied to the after the device. However, if there is a system analog signal conditioning circuit that provides conditions that differ from the VDD and VSS supplies of the AD7656-1/AD765 7-1/AD765 8-1, or if the analog input can be 1 applied before the power supply is established, then it is recommended to use an analog input series resistor and Schottky diode in series with the VDD and VSS supplies (see Figure 39).

This configuration should also be used if AVCC is applied to the AD7656-1/AD7657-1/AD7658-1 before VDD and VSS are applied.

Dimensions