feature

Highly integrated: 32-channel DAC within 12 mm × 12 mm CSPBGA adjustable voltage output range ensures monotonic readback capability DSP/microcontroller compatible serial interface; output impedance: 0.5Ω ( AD5532-1 , AD5532-2 ), 500 Ω (AD5532-3), 1 kΩ (AD5532-5); output voltage range: 10V (AD5532-1, AD5532-3, AD5532-5), 20V (AD5532-2); infinite sample and hold capability, Accuracy is ±0.018% over a temperature range of -40°C to +85°C.

application

Automatic test equipment; optical network; level setting; instrumentation; industrial control system; data acquisition; low cost I/O.

General Instructions

The AD5532 is a 32-channel 14-bit voltage output DAC with an additional infinite sample and hold mode. The selected DAC register is written through the 3-wire serial interface; VOUT for this DAC is then updated to reflect the new contents of the DAC register. DAC selection is done through address bits A0–A4. The output voltage range is determined by the bias voltage on the pins and the gain of the output amplifier. Due to the headroom of the output amplifier, it is limited from VSS+2v to VDD–2v.

The device operates at AVCC=5 V±5%; DVCC=2.7 V to 5.25 V; VSS=-4.75 V to -16.5 V; and VDD=8 V to 16.5 V. The AD5532 requires a stable 3 V reference on the offset voltage of the reference input and the disconnect input.

Product Highlights

1. 32 channels, one package 14-bit DAC, guaranteed monotonic.

2. Provide 74-lead CSPBGA package, the body size is 12 mm × 12 mm.

3. Sag/infinite sample and hold mode.

the term

DAC mode

Integral Nonlinearity (INL)

This is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is expressed as a percentage of full scale.

Differential Nonlinearity (DNL)

This is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. The specified DNL ±1 LSB maximum value guarantees monotonicity.

Offset

The offset is the measured value of the output, all zeros are loaded into the DAC, off_IN=0. Because the DAC rises to about 50mV from ground, this output is typically:

full scale error

This is a measure of the output error for all 1s loaded into the DAC. It is expressed as a percentage of full scale. See Figure 8. Calculated as

in

Output stabilization time

This is the time from the last data bit entering the DAC until the output settles to within ±0.39%.

settlement time

The time it takes for the output to settle within ±0.39% from a step change in the input voltage from 0 V to 3 V.

Digital-to-analog fault pulse

This is the faulty region injected into the analog output when the code in the DAC register changes state. It is designated as the fault region in nV secs when the digital code is changed by 1 LSB at the major carry transition (011). . . 11 to 100. . . 00 or 100. . . 00 to 011. . . 11) Yes.

digital crosstalk

This is the glitch pulse transferred to the scale output in one DAC, while a full-scale code change (all 1s to all 0s and vice versa) is written to the other DAC. It is expressed in nV secs.

Analog crosstalk

This is due to a full-scale change in the output of the other DAC (VOUT) moving to the fault region of the output of one DAC (VOUT). The fault area is expressed in nV secs.

digital feedthrough

This is a measure of the pulse injected into the analog output from the digital control input when the part is not written, i.e. when CS/SYNC is high. It is specified in nV secs and is measured by a worst-case change on a digital input pin, e.g. from 0 to 1 and vice versa.

Output Noise Spectral Density

This is random noise generated inside the measurement. Random noise is characterized by its spectral density (voltage per root Hertz). It is measured by loading all DACs to midscale and measuring the noise at the output. The unit of measurement is nV/(√Hz).

Output temperature coefficient

This is a way to measure the change in analog output with temperature. Expressed in ppm/°C.

DC Power Supply Rejection Ratio (PSRR)

DC Power Supply Rejection Ratio is a measure of the change in the analog output when the power supply voltages (VDD and VSS) change. It is expressed in dBs. VDD and VSS variation is ±5%.

DC crosstalk

This is the DC change in the output level of a DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output changes of all other DACs. Expressed in μV.

ISHA mode

VIN to VIN nonlinearity

A measure of the maximum deviation of the straight line from the VIN endpoint to the VUT transfer function. It is expressed as a percentage of full scale.

offset error

This is a way to measure the output error at VIN=70mV. Ideally, when VIN = 70mV:

Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal). It is expressed in mV and can be positive or negative. See Figure 9.

gain error

This is to measure the span error of the analog channel. It is the deviation of the slope of the transfer function, expressed in mV. See Figure 9. Calculated as: gain error = actual full-scale output - ideal full-scale output - offset error; where: ideal full-scale output = gain × 2.96 – ((gain – -1) × VOFFS_IN).

AC crosstalk

This is the area where a fault occurs on the output of one channel while the other channel is acquiring. It is expressed in nV secs.

Output stabilization time

This is the time from the busy state going high until the output settles to ±0.018%.

Acquisition time

This is the time it takes to get the VIN input. It's the length of the busy time that keeps a low profile.

Typical performance characteristics

Function description

The AD5532 consists of 32 DACs and one ADC (for ISHA mode) in a single package. In DAC mode, the 14-bit digital word is loaded into one of 32 DAC registers via the serial interface. It is then converted (with gain and offset) to an analog output voltage (VOUT0–VOUT31).

To update the output voltage of the DAC, the required DAC is addressed through the serial port. After loading the DAC address and code, the selected DAC will convert the code.

At power-up, all DACs (including the offset channel) are loaded with zeros. Each of the 33 DACs is internally offset from GND by 50 mV (typ), so outputs VOUT 0 to VOUT 31 are 50 mV (typ) at power-up, if the OFFS_-IN pin is offset directly by the on-board The channel (OFFS_-OUT) is driven, i.e. if OFFS_-IN is 50 mV, VOUT = (Gain × VDAC) – (Gain-1) × VOFFS_-IN = 50 mV.

Output buffer stage gain and offset

The function of the output buffer stage is to convert the 50 mV–3 V output of the DAC to a wider range. This is done by increasing the DAC output by 3.52/7 and offsetting the voltage with the voltage in the pin on off_.

VDAC is the output of the DAC.

VOFFS_-IN is the voltage at OFFS_ in the pin.

The following table shows how the output range on VOUT is related to the user-supplied offset voltage.

VOUT is limited only by the headroom of the output amplifier.

VOUT must be within maximum ratings.

Bias voltage channel

The offset voltage can be supplied externally by the user at off-IN, or by an additional offset voltage channel on the device itself. The offset can be set in two ways. In ISHA mode, the desired bias voltage is set on the VIN and obtained by the bias channel. In DAC mode, the code corresponding to the offset value is loaded directly into the offset DAC. The DAC output of this offset channel is connected directly to off_OUT. Off_ can be used as a bias voltage for 32 output amplifiers by connecting to this bias voltage. It is important to choose the offset so that VOUT is at the maximum rating.

Reset function

The reset function on the AD5532 can be used to reset all nodes on the device to a power-on reset state. This is accomplished by applying a low-pass pulse of 90 ns to 200 ns on the track/reset pin on the device. If the applied pulse is less than 90ns, a fault is assumed and no action is taken. If the applied pulse is greater than 200 ns, this pin takes its track function on the selected channel, switches the VIN to the output buffer, and is acquired on the channel until the rising edge of the track occurs.

ISHA mode

In ISHA mode, the input voltage VIN is sampled and converted into a digital word. During acquisition, the non-vertical inputs of the output buffers (gain and offset stages) are tied to VIN to avoid spurious outputs while the DAC acquires the correct code. This is done in 16µs max. The updated DAC output then assumes control of the output voltage. The output voltage of the DAC is connected to the non-rotating input of the output buffer. Because the channel output voltage is actually the output of the DAC, there is no droop associated with it. As long as the power to the device is maintained, the output voltage is constant until the channel is addressed again. Since the offset of the internal DAC from GND is 70 mV (max), the minimum VIN in ISHA mode is 70 mV. The maximum VIN is 2.96 V due to the upper deadband of 40 mV(max).

Analog input (ISHA mode)

Figure 19 shows the equivalent analog input circuit. Capacitor C1 is typically 20pf attributable to pin capacitance and 32 off channels. An additional 7.5 pF (typ) is turned on when a channel is selected. Capacitor C2 is charged to the voltage previously obtained on the particular channel, so it must be charged/discharged to the new level. The external power supply must be able to charge and discharge this additional capacitor within the channel-selected 1µs–2µs range in order to be able to obtain the VIN accurately. Therefore, a low impedance source is recommended.

A large source impedance can greatly affect the performance of the ADC. An input buffer amplifier may be required.

Track function (ISHA mode)

Normally in the ISHA mode of operation, the track is held high and acquisition begins when the channel is addressed. However, if the track is low while the channel is being addressed, the vehicle identification number (VIN) switches to the output buffer and does not acquire on the channel until the rising edge of the track. During this phase, the busy pin goes low until the acquisition is complete, at which point the DAC assumes control of the output buffer's voltage and VIN can be changed again without affecting the output value.

This is useful in applications where the user wants to increase the VIN until VOUT reaches a certain level (see Figure 20). During the rising process of the VIN, it is not necessary to continuously acquire the VIN. The rail can be kept low and brought high only when VOUT reaches the desired voltage. At this stage, the acquisition of the vehicle identification number begins.

In the example shown, the output of the pin driver requires a desired voltage. This voltage is represented by an input of the comparator. The microcontroller/microprocessor boosts the input voltage on the VIN through the DAC. When the voltage on the VIN rises, the track remains low so that the VIN is not continuously acquired. When the output of the pin driver reaches the desired voltage, the comparator output switches. The µC/µP then knows what code needs to be entered to get the desired voltage at the DUT. The track input is now high and the part starts getting the VIN. During this phase, the vehicle is less busy until the VIN is obtained. Then, the output buffer switches from VIN to the output of the DAC.

operating mode

The AD5532 can be used in four different modes of operation. These modes are set by two mode bits (the first two bits of the serial word).

1. ISHA mode

In this mode, a channel is addressed, and that channel acquires the voltage on VIN. This mode requires a 10-bit write (see Figure 21a) to address the relevant channel (VOUT0–VOUT31, offset channel or all channels). Write MSB first.

2. DAC mode

In this standard mode, the selected DAC registers are loaded serially. This requires a 24-bit write (10-bit addressing the associated DAC plus an additional 14-bit DAC data). Write MSB first. In DAC mode, the user must allow 400 ns (minutes) between consecutive writes.

3. Get and read back mode

This mode allows the user to obtain the Vehicle Identification Number (VIN) and read the data in a specific DAC register. The associated channel is addressed (10-bit write, MSB first) and VIN is acquired within 16 μs (max).

After acquisition, after the next falling edge of synchronization, the data in the associated DAC register is clocked out on the DOUT line in a 14-bit serial format. The full acquisition time must elapse before the DAC register data can be clocked.

4. Readback mode

Again, this is a readback mode, but no acquisition is performed. The associated channel is addressed (10-bit write, MSB first), and on the next falling edge of synchronization, the data in the associated DAC register is clocked out to the DOUT row in 14-bit serial format. The user must allow 400 ns (minimum) between the last falling edge of SCLK for a 10-bit write and the synchronous falling edge for a 14-bit readback. The sequential read and write words are shown in Figure 21.

This feature allows the user to read the DAC register code for any channel. In DAC mode, this is useful when verifying write cycles. In ISHA mode, readback is useful if the system is already calibrated and the user wants to know what code in the DAC corresponds to the desired voltage on VOUT. If this voltage is needed again, the user can enter code directly into the DAC register without going through the acquisition sequence.

serial interface

The serial interface allows easy interfacing with most microcontrollers and DSPs such as PIC16C, PIC17C, QSPI, SPI, DSP56000, TMS320 and ADSP-21xx without any glue logic. When connected to an 8051, SCLK must be inverted. The Microprocessor Interface section explains how to interface with some popular DSPs and microcontrollers. Figure 4, Figure 5, and Figure 6 show the timing diagrams for serial reads and writes to the AD5532. The serial interface can work with both continuous and non-continuous serial clocks. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift register. Any other edges while synchronizing are ignored until the correct number of bits is shifted in or out. SCLK is ignored when the correct number of bits for the selected mode is shifted in or out. For another serial transfer, the counter must be reset by a synchronous falling edge.

In readback, the synchronization causes DOUT to leave its high-impedance state, and data is clocked out on the DOUT line and on the subsequent rising edge of SCLK. On the falling edge of the 14th SCLK, the double pin returns to a high impedance state. Data is locked to the sync signal on the first SCLK falling edge after the falling edge and subsequent SCLK falling edges. During readback, DIN is ignored. Serial interfaces may not shift data in or out until the falling edge of the sync signal is received.

Parallel interface (ISHA mode only)

The SE/PAR bit must be tied low to enable the parallel interface and disable the serial interface. As described in Table 11, the parallel interface is controlled by 9 pins.

Microprocessor interface

AD5532 to ADSP-21xx interface

The ADSP-21xx DSPs are easy to interface with the AD5532 without additional logic.

After motion is enabled, data transfer is initiated by writing a word to the TX register. During the write sequence, data is clocked to the AD5532 on each rising edge of the DSP serial clock and on the falling edge of its SCLK. In readback, 16-bit data is clocked out of the AD5532 on each rising edge of SCLK and clocked into the DSP on the rising edge of SCLK. DIN is ignored. In this configuration, the valid 14-bit data is concentrated in the 16-bit RX register. The motion control register settings should be as shown in Table 12.

Figure 22 shows the connection diagram.

AD5532 to MC68HC11

The Serial Peripheral Interface (SPI) on the MC68HC11 is configured with Master Mode (MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit (CPHA) = 1. SPI is configured by writing to the SPI Control Register (SPCR) - see . The SCK of the 68HC11 drives the SCLK of the AD5532, the MOSI output drives the serial data line (DIN) of the AD5532, and the MISO input is driven by DOUT. The 68HC11 user manual sync signal comes from the port line (PC7). When data is sent to the AD5532, the sync line is taken low (PC7). Data displayed on the MOSI output is valid on the falling edge of SCK. Serial data for the 68HC11 is transmitted in 8-bit bytes, with only 8 falling clock edges during the transmission cycle. The data MSB is transferred first. Transfer In ISHA mode, the data in the SPDR register must be left-aligned. PC7 must be pulled low to start the transfer. It gets turned up and down again before another read/write cycle happens. Figure 23 shows a connection diagram.

AD5532 to PIC16C6x/7x

The PIC16C6x/7x Synchronous Serial Port (SSP) is configured as an SPI master with the clock polarity bit set to 0. This is done by writing to the Synchronous Serial Port Control Register (SSPCON). See the PIC16/17 Microcontroller User's Manual. In this example, I/O port RA1 is used for pulse synchronization and enables the serial port of the AD5532. This microcontroller transfers only 8 bits of data during each serial transfer operation; therefore, depending on the mode, two or three consecutive read/write operations are required. Figure 24 shows the connection diagram.

AD5532 to 8051

The AD5532 requires a clock that is synchronized with the serial data. Therefore, the 8051 serial interface must operate in mode 0. In this mode, serial data is entered and exited through RXD, and a shift clock is output on TXD. Figure 25 shows how the 8051 is connected to the AD5532. Because the AD5532 shifts out data on the rising edge of the shift clock and latches the data on the falling edge, the shift clock must be inverted. The AD5532 requires its data to have MSB first. Because the 8051 outputs the LSB first, the transmit routine must take this into account.

Application circuit

AD5532 in a typical ATE system

The AD5532 is ideal for use in automated test equipment. Several DACs are required to control pin drivers, comparators, active loads and signal timing. Traditionally, a sample and hold device is used in this application.

The AD5532 has several advantages: no refresh required, no droop, elimination of pedestal errors, and no need for additional filtering to eliminate glitches. Overall, a higher level of integration is achieved in a smaller area (see Figure 26).

Typical Application Circuit (DAC Mode)

The AD5532 can be used in many optical networking applications that require a large number of DACs to perform control and measurement functions. In the example shown in Figure 27, the output of the AD5532 is amplified and used to control the driver to determine the position of the MEMS mirror in the optical switch. The exact position of each mirror is measured with sensors. The sensor readings are mixed using four dual 4-channel matrix switches (ADG739) and fed back to an 8-channel 14-bit ADC (AD7856).

The control loop is driven by the ADSP-2191M, a 16-bit fixed-point DSP, 3 motion interfaces and 2 SPI ports. The DSP uses some of these serial ports to write data to the DAC, control the multiplexer, and read data from the ADC.

Typical Application Circuit (ISHA Mode)

The AD5532 can be used to set the voltage levels on 32 channels, as shown in the following circuit. The AD780 provides the 3 V reference for the AD5532 and AD5541 16-bit DACs. A simple 3-wire interface is used to write to the AD5541. Since the output resistance of the AD5541 is 6.25 kΩ (typ), the time required to charge and discharge the capacitor at the VIN pin is very long. Therefore, the AD820 is used to buffer the DAC output. Note that when laying out the circuit, it is important to keep the noise on the VIN and refill to a minimum.

Power decoupling

In any circuit where accuracy is important, careful consideration of power and ground return layout helps ensure rated performance. The printed circuit board on which the AD5532 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5532 is in a system and multiple devices require an AGND to DGND connection, this connection should only be made at one point. The star ground point should be as close as possible to the device. For power supplies with multiple pins (VSS, VDD, AVCC), it is recommended to tie these pins together. The AD5532 should have ample supply bypassing of 10µF in parallel, and 0.1µF on each supply should be as close to the package as possible, ideally close to the device. The 10µF capacitors are of the tantalum bead type. The 0.1µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as a common ceramic type that provides a high frequency, low impedance path to ground to handle transient currents from internal logic switches.

The power lines to the AD5532 should use as large traces as possible to provide a low impedance path and reduce the effect of faults on the power lines. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other parts of the board, and must not run near the reference input. A ground wire routed between the DIN and SCLK lines helps reduce crosstalk between them (not needed on multi-layer boards because there is a separate ground plane, but separating the lines helps reduce crosstalk).

Note that noise on the VIN and refill lines must be minimized. Especially for optimum ISHA performance, the VIN line must remain noise-free. Depending on the noise performance of the board, it may be necessary to install a noise filter capacitor on the VIN line. If this capacitor is necessary, the source driving VIN may need to be buffered for optimal throughput. Avoid crossover of digital and analog signals. The traces on opposite sides of the board should be at right angles to each other. This reduces feedthrough effects through the board. Micro-stripe technology is by far the best, but dual panels are not always possible. In this technique, the component side of the board is dedicated to the ground plane, while the signal lines are placed on the solder side.

As is the case with all thin packages, care must be taken to avoid bending the package and avoid point loads on the surface of the package during assembly.

Dimensions