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2022-09-23 10:21:31
The AD5383 is a complete, 3 V/5 V, single-supply, 32-channel, 12-bit DENSADAC
feature
Guaranteed monotonic; input error: ±1 LSB maximum; on-chip 1.25 V/2.5 V, 10 ppm/°C reference; temperature range: –40°C to +85°C; rail-to-rail output amplifier; power-down mode; package type: 100 -lead LQFP (14 mm x 14 mm); user interface; parallel serial (SPI-/QSPI-/MICROWIRE-/DSP compatible with data readback); I2C compatible rugged 6.5 kV HBM and 2 kV FICDM ESD rating.
Comprehensive function
Channel Monitor: Simultaneously update output to user-programmable code Amplifier boost mode with LDAC clear function to optimize slew rate User-programmable offset and gain adjustment switch mode, enable square wave thermal monitoring.
application
Variable Optical Attenuators (VOA); Level Setting (ATE); Optical Micro-Electro-Mechanical Systems (MEMS); Control Systems; Instrumentation.
General Instructions
The AD5383 is a complete, single-supply, 32-channel, 12-bit DENSADAC® available in a 100-lead LQFP package. All 32 channels have an on-chip output amplifier with rail-to-rail operation. The AD5383 includes programmable internal 1.25 V/2.5 V, 10ppm/°C reference; an on-chip channel monitor function that multiplexes the analog output to a common MON_OUT pin for external monitoring; and an output amplifier boost mode, Allows optimization of amplifier slew rate.
Features of AD5383:
(1), double-buffered parallel interface, 20 ns WR pulse width.
(2), SPI-/QSPI-/MICROWIRE-/DSP compatible serial interface, the interface speed exceeds 30mhz.
(3), IC compatible interface supporting 400 kHz data transfer rate.
The input register followed by the DAC register provides double buffering, allowing the DAC output to be updated independently or simultaneously using the LDAC input.
Each channel has a programmable gain and offset adjustment register, allowing the user to fully calibrate any DAC channel. With boost turned off, power consumption is typically 0.25mA/channel.
the term
Relative accuracy
Relative accuracy or endpoint linearity is a measure of the maximum deviation of a straight line through the endpoints of the DAC transfer function. Measured after adjustment for zero-scale error and full-scale error, expressed in LSB.
Differential nonlinearity
Differential nonlinearity is the difference between the measured variation and the ideal 1lsb variation of any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum guarantees monotonicity.
Zero scale error
Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC register. Ideally, with all 0s loaded into the DAC, m=all 1s, c=2n-1, VOUT(zero-scale)=0 V, zero-scale error is a measure of the difference between VOUT(real) and VOUT(ideal) , in mV. This is mainly due to the offset of the output amplifier.
offset error
Offset error is the difference between VOUT (actual) and VOUT (ideal) in the linear region of the measured transfer function, in mV. Offset error is measured on the AD5383-5 and AD5383-3, code 32 is loaded into the DAC register, and code 64 is loaded on the AD5383-3.
gain error
Gain error is specified over the linear range of the output range, between VOUT=10 mV and VOUT=AVDD-50 mV. It is the slope deviation of the DAC transfer characteristic from ideal, expressed in %FSR at no load on the DAC output.
DC crosstalk
DC crosstalk is the DC change in the output level of one DAC at midscale in response to a full-scale code (all 0s to all 1s and vice versa) and the output changes of all other DACs. Expressed in LSB.
DC output impedance
The DC output impedance is the effective output source resistance.
It is mainly based on packaged lead resistors.
Output Voltage Settling Time Output voltage settling time is the time required for the output of the DAC to settle to a specified level for a quarter to quarter full-scale input change, measured from a busy rising edge.
Digital-to-analog fault energy
Digital-to-analog fault energy refers to the energy injected into the analog output during master code transitions. It is designated as a fault region in nV-s. Measured by toggling the DAC register data between 0x1FF and 0x2000.
DAC-to-DAC crosstalk
DAC-to-DAC crosstalk is a glitch pulse that occurs in the output of one DAC due to a digital change and a subsequent change in the analog output of another DAC. Victim channel is loaded with midscale. DAC-to-DAC crosstalk is specified in nV-s.
digital crosstalk
A glitch pulse transmitted to the output of one converter due to a change in the DAC register code of the other converter is defined as digital crosstalk and is specified in nV-s.
digital feedthrough
When the device is not selected, high frequency logic activity on the device's digital inputs can capacitively couple across and through the device to appear as noise on the VOUT pin. It can also be connected along the power and ground wires. This noise is digital feedthrough.
Output Noise Spectral Density
The output noise spectral density is the random noise generated inside the measurement. Random noise is characterized by its spectral density (voltage per √Hz). It is measured by loading all DACs to midscale and measuring the noise at the output. Measured in nV/√Hz in a 1 Hz bandwidth of 10 kHz.
Typical performance characteristics
Function description
DAC Architecture - Overview
The AD5383 is a complete, single-supply, 32-channel voltage output DAC that provides 12-bit resolution. The part is available in a 100-lead LQFP package and has parallel and serial interfaces. The Product includes an internal, software-selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used to drive buffered reference inputs; alternatively, these inputs can be driven with an external reference. Internal/external reference selection is made through the CR8 bit in the control register; if internal reference is selected, CR10 selects the reference amplitude. All channels have an on-chip output amplifier with rail-to-rail output capable of driving 5 kΩ into a 200 pF load.
The structure of a single DAC channel consists of a 12-bit resistor string DAC and an output buffer amplifier operating in a gain of 2. This resistor string structure ensures the monotonicity of the DAC. The 12-bit binary digit code loaded into the DAC register determines at which node on the string the voltage is tapped before feeding it to the output amplifier. Each channel on these devices contains independent offset and gain control registers, allowing the user to digitally fine-tune the offset and gain. These registers enable the user to calibrate errors throughout the signal chain, including the DAC, using the internal m and c registers, which hold the correction factors. All channels are double-buffered, allowing simultaneous updates of all channels using the LDAC pin. Figure 27 shows a block diagram of a single channel on the AD5383. The digital input transfer function of each DAC can be expressed as:
Where: x2 = data word loaded into the resistor string DAC; x1 = 12-bit data word written to the DAC input register; m = gain factor (default 0xFFE). The gain coefficient is written to the 11 most significant bits (DB11 to DB1), and the LSB (DB0) is 0; n = DAC resolution (n = 12 for AD5383); c = 12-bit offset coefficient (default is 0x800).
The complete transfer function of these devices can be expressed as:
where: x2 is the data word loaded into the resistor string DAC. Relative to the internal reference voltage or externally applied to the DAC output/re-input pins. For the specified performance, an external reference voltage of 2.5 V is recommended for the AD5383-5 and an external reference voltage of 1.25 V is recommended for the AD5383-3.
data decoding
The AD5383 contains a 12-bit data bus from DB11 to DB0. Depending on the values of REG1 and REG0 (see Table 9), this data is loaded into the addressed DAC input register, offset (c) register, or gain (m) register.
On-chip Special Purpose Function Registers (SFRs)
The AD5383 contains a number of Special Function Registers (SFRs), as shown in Table 13. SFR is addressed with REG1=REG0=0 and decoded to address bit A0 with address bit A4.
SFR command
NOP (no operation)
REG1=REG0=0, A4 to A0=00000
Does nothing but is useful in serial readback mode to time out data on DOUT for diagnostics. During NOP operation, the busy pulse is low.
Write CLR code
REG1=REG0=0, A4 to A0=00001
DB11 to DB0=contains CLR data
Turning the CLR line low or performing a soft clear function loads the contents of the DAC register with the data contained in the user-configurable CLR register and sets VOUT0 to VOUT31 accordingly. This is useful for setting a specific output voltage under clear conditions. This also facilitates calibration; the user can load either full-scale or zero-scale into the clear code register, then issue a hardware or software clear to load this code to all DACs, eliminating the need for a separate write to each DAC. Defaults to all zeros at boot.
Soft coherent lidar
REG1=REG0=0, A4 to A0=00010 DB11 to DB0=don’t care
Executing this instruction executes the CLR, which has the same function as that provided by the external CLR pin. The DAC output is loaded with the data in the CLR code register. It takes 35 microseconds to fully execute the soft CLR, as indicated by the busy low time.
soft power off
REG1=REG0=0, A4 to A0=01000 DB11 to DB0=don’t care
Executing this command performs a global power-down function that puts all channels into low-power mode, reducing the analog supply current to a maximum of 2 microamps, and the digital current to a maximum of 20 microamps. In power-down mode, the output amplifier can be configured as a high-impedance output or provide a 100 kΩ load to ground. The contents of all internal registers are preserved in power-down mode. Registers cannot be written to while powered down.
soft start
REG1=REG0=0, A4 to A0=01001 DB11 to DB0=don’t care
This command is used to power up the output amplifier and internal reference. Power down time is 8µs, hardware power down and software functions are internally combined on a digital or function seat.
soft reset
REG1=REG0=0, A4 to A0=01111 DB11 to DB0=don’t care
This command is used to implement a software reset. All internal registers are reset to their default values of m for full scale and c for zero scale. The contents of the DAC registers are cleared, setting all analog outputs to 0 V. The soft reset activation time is 135 microseconds. A soft reset is performed only when the AD5383 is not in power down mode.
Control Register Read/Write
REG1=REG0=0, A4 to A0=01100, the R/W state determines whether the operation is a write (R/W=0) or a read (R/W=1). DB11 to DB0 contain control register data.
control register content
CR11: Power-off state. This bit is used to configure the output amplifier state when powered down.
CR11=1: Amplifier output is high impedance (power on by default).
CR11=0: The amplifier output is 100 kΩ to ground.
CR10: Reference selection. This bit selects the AD5383's operating internal reference. The CR12 is programmed as follows:
CR10=1: The internal reference voltage is 2.5V (default value of AD5383-5), the recommended operating reference voltage of AD5383-5.
CR10=0: The internal reference voltage is 1.25 V (default value of AD5383-3), the recommended operating reference voltage of AD5383-3.
CR9: Current Boost Control. This bit is used to increase the current in the output amplifier, thereby changing its slew rate. This bit is configured as follows:
CR9=1: Start boost mode. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing power dissipation.
CR9=0: Boost mode is off (default is power on). This reduces bias current in the output amplifier, reducing overall power dissipation.
CR8: Internal/External Reference. This bit determines whether the DAC uses its internal reference or the reference from an external application.
CR8=1: Internal references are enabled. The reference output depends on the data loaded into CR10.
CR8=0: select external reference (default is power on).
CR7: Channel Monitor Enable (see Channel Monitor Function).
CR7=1: Monitor is enabled. This will enable the channel monitor function. After a monitor channel is written to the SFR register, the selected channel output is routed to the MON_OUT pin.
CR7=0: Monitor disabled (default is powered). When the monitor is disabled, the MON U OUT pin is 3.
CR6: Thermal monitoring function. This function is used to monitor the internal die temperature of the AD5383 when enabled. The thermal monitor reduces the power of the output amplifier when the temperature exceeds 130°C. This feature can be used to protect the device if multiple output channels are shorted at the same time, potentially exceeding the power consumption. Soft power-on will re-enable the output amplifier if the die temperature falls below 130°C.
CR6=1: Thermal monitoring enabled.
CR6=0: Thermal monitor disabled (default is power up).
CR5 and CR4: Never mind.
CR3 to CR0: The toggle function is enabled. This function allows the user to toggle the output between the two codes loaded into the A and B registers of each DAC. Control register bits CR3 to CR0 are used to enable a single bank of eight channels to operate in toggle mode. A logic 1 written to any bit enables a group of channels; a logic 0 disables a group of channels. LDAC is used to switch between the two registers. A logic 1 enables a group of channels; a logic 0 disables a group of channels.
Channel monitoring function
REG1=REG0=0, A4 to A0=01010
DB11 to DB6=Contains the data to be addressed to the monitored channel.
A channel monitor function is available on the AD5383. This feature includes a multiplexer that is addressed through the interface, allowing any channel output or signal connected to the MON_-IN pin to be routed to the MON_-OUT pin for monitoring using an external ADC. Before routing any channel to MON U OUT, the channel monitor function must be enabled in the control register. On the AD5383, DB11 to DB6 contain the channel address of the channel being monitored. Select channel address 63 to tri-state MON_OUT.
hardware function
Reset function
Bringing the reset line low resets the contents of all internal registers to their power-on-reset state. Reset is a negative edge sensitive input. The default values correspond to m at full scale and c at zero scale. The contents of the DAC register are cleared, setting VOUT0 to VOUT31 to 0 V. This sequence takes up to 270 microseconds.
The falling edge of reset initiates the reset process; busy goes low for the duration and returns high when reset is complete. When the busy signal is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation and ignores the state of the reset pin until the next falling edge is detected. A soft reset is only performed when the AD5383 is not in power down mode.
Asynchronous clear function
Turning the CLR line low will clear the contents of the DAC register to the data contained in the user-configurable CLR register and set VOUT0 to VOUT31 accordingly. This function can be used for system calibration to load zero and full scale to all channels. The execution time of the CLR is 32 microseconds.
Busy and LDAC functions
BUSY is a digital CMOS output that indicates the state of the AD5383. Each time the user writes new data to the corresponding x1, c, or m register, the value of x2 is calculated, which is the internal data loaded into the DAC data register. During the computation of x2, the busy output goes low. When BUSY is low, the user can continue to write new data to the x1, m or c registers, but no DAC output updates. By driving the LDAC input low, the DAC output is updated. If LDAC goes low while busy, the LDAC event is stored and the DAC output is updated immediately after going high while busy. The user can hold the LDAC input permanently low, in which case the DAC output is updated as soon as BUSY goes high. Busy also goes low during power-on reset and when a falling edge is detected on the reset pin. During this time, all interfaces are disabled and any events on LDAC are ignored. The AD5383 includes an additional feature that the DAC register is not updated unless its x2 register has been written since the last time LDAC was low. Normally, when LDAC goes low, the DAC register is filled with the contents of the x2 register. However, the AD5383 will only update the DAC registers if the x2 data has changed, thereby eliminating unnecessary digital crosstalk.
FIFO operation in parallel mode
The AD5383 includes a FIFO to optimize operation when operating in parallel interface mode. FIFO Enable (level sensitive, active high) is used to enable the internal FIFO. When connected to a DVDD, the internal FIFO is enabled, allowing the user to write to the device at full speed. FIFO is only available in parallel interface mode. At power-up, after CLR or reset, the state of the FIFO EN pin is sampled to determine if the FIFO is enabled. In serial or IC interface mode, FIFO-EN should be held low. Up to 128 consecutive instructions can be written to the FIFO at the highest speed in parallel mode. When the FIFO is full, any further writes to the device are ignored. Figure 29 shows a comparison of channel update time between FIFO mode and non-FIFO mode. Figure 29 also provides an overview of digit loading times.
power-on reset
The AD5383 contains a power-on reset generator and state machine. A power-on reset resets all registers to a predefined state and configures the analog outputs to high impedance. During the power-on reset sequence, the busy pin goes low, preventing data from being written to the device.
power outage
The AD583 includes a global power-down feature that puts all channels into a low-power mode and reduces the analog power consumption to 2µA, reducing the maximum power consumption to 20 seats. In power-down mode, the output amplifier can be configured as a high-impedance output or provide a 100 kΩ load to ground. The contents of all internal registers are preserved in power-down mode. When the power is removed, the settling time of the amplifier will disappear before the output reaches its correct value.
interface
The AD5383 contains parallel and serial interfaces. Additionally, the serial interface can be programmed to be compatible with SPI, DSP, MICROWIRE or IC. The SE/PAR pin selects parallel and serial interface modes. In serial mode, the SPI/IC pins are used to select DSP, SPI, MICROWIRE or IC interface mode.
These devices use an internal FIFO memory that allows high-speed sequential writes in parallel interface mode. While executing the write command, the user can continue to write new data to the device. The BUSY signal represents the current state of the device and goes low when executing instructions in the FIFO. In parallel mode, up to 128 consecutive instructions can be written to the FIFO at maximum speed. When the FIFO is full, any further writes to the device are ignored.
To minimize device power consumption and on-chip digital noise, the active interface is only fully powered up when writing to the device, that is, on the falling edge of WR or the falling edge of SYNC.
Serial interface compatible with DSP, SPI, MICROWIRE
The serial interface can operate with at least three wires in standalone mode or four wires in daisy-chain mode. Daisy chaining allows many devices to be cascaded together to increase the system channel count. The SE/PAR pin must be tied high and the SPI/IC pin (pin 97) should be tied low for a DSP/SPI/Microwire compatible serial interface. In serial interface mode, the user does not need to drive the parallel input data pins. The control pins of the serial interface are:
Sync, DIN, SCLK - Standard 3-wire interface pins.
DCEN - Select standalone mode or daisy-chain mode.
SDO - Data output pin for daisy-chain mode.
Figure 3 and Figure 5 show the timing diagrams for serial writes to the AD5383 in standalone and daisy-chain modes. The 24-bit data word format for the serial interface is shown in Table 17.
When A/B toggle mode is enabled, this pin selects whether data is written to the A register or the B register. When toggle is disabled, this bit should be set to zero to select the A data register.
R/W is the read or write control bit.
A4 to A0 address the input channels.
REG1 and REG0 select the register to which data is written.
DB11 to DB0 contain input data words.
Ten is a state of indifference.
solo mode
Independent mode is enabled by connecting the DCEN (Daisy Chain Enable) pin low. The serial interface can work with both continuous and non-continuous serial clocks. The first falling edge of synchronization starts the write cycle and resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted into the serial shift register. Any other edges (except falling edges) while synchronizing are ignored until 24 bits are clocked. Once shifted in 24 bits, SCLK will be ignored. For another serial transfer, the counter must be reset by a synchronous falling edge.
Daisy Chain Mode
For systems with multiple devices, the SDO pins can be used to chain multiple devices together. This daisy-chain mode can be used for system diagnostics and to reduce the number of serial interface lines.
By connecting the DCEN (Daisy Chain Enable) pin high, the daisy chain mode is enabled. The first falling edge of synchronization begins the write cycle. When sync is low, SCLK is continuously applied to the input shift register. If more than 24 clock pulses are applied, the data will fluctuate out of the shift register and appear on the SDO line. This data is clocked on the rising edge of SCLK and is valid on the falling edge. A multi-device interface is constructed by connecting the SDO of the first device to the DIN input of the next device in the chain. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24N, where N is the total number of AD538x devices in the chain.
Sync will be high when the serial transfer to all devices is complete. This locks the input data in each device in the daisy chain and prevents any further data from entering the input shift register.
If a high sync occurs before 24 clocks into the section, it is considered a bad frame and the data is discarded. The serial clock can be a continuous clock or a gated clock. A continuous SCLK source should only be used if synchronization can be kept at the correct number of clock cycles low. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and a high sync must follow the final clock to lock the data.
readback mode
Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. When R/W=1, bits A4 to A0, combined with bits REG1 and REG0, select the register to be read. The remaining data bits in the write sequence are not important. During the next SPI write, the data appearing on the SDO output will contain the data from the previously addressed register. For single register reads, the NOP command can be used to clock out the data of the selected register on the SDO. Figure 30 shows the readback sequence. For example, to read back the m register of channel 0 on the AD5383, the following sequence should be implemented. First, write 0x404XXX to the AD5383 input registers. This configures the AD5383 in read mode and selects the m register for channel 0. Note that data bits DB11 to DB0 are not significant. Next is the second write, a NOP condition, 0x000000. During this write, the data from the m register is clocked on the DOUT line, i.e. the clocked data will contain the data from the m register (in bits DB11 to DB0) and the first 10 bits contain the previously written address information. In readback mode, the sync signal must frame the data. Data is clocked on the rising edge of SCLK and valid on the falling edge of the SCLK signal. If SCLK idles high between write and read operations for a readback operation, the first bit of data will be clocked on the falling edge of sync.
I2C serial interface
The AD5383 has an IC-compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (symptom self-rating scale). SDA and SCL facilitate the AD5383 and the host at frequencies up to 400 kHz. Figure 6 shows a 2-wire interface timing diagram including different modes of operation. When selecting the IC operation mode, first configure the serial operation mode (SE/PAR=1); then by configuring the SPI/IC pin to logic 1. The device is connected to the IC bus as a slave (ie, the AD5383 does not generate a clock). AD5383 has 7-bit slave address 10101 (AD1) (AD0). 5 msbs are hard-coded and 2 lsbs are determined by the state of AD1 and AD0 pins. Hardware configuration AD1 and AD0 allow four of these devices to be configured on the bus.
One data bit is transferred every SCL clock cycle. During the high period of the SCL clock pulse, the data on SDA must remain stable. A change in SDA while SCL is high is the control signal that configures the start and stop conditions. Both SDA and SCL are pulled high by external pull-up resistors when the IC bus is not busy.
start and stop conditions
The master device initiates communication by issuing a start condition. The start condition is a high-to-low transition on SDA with SCL high. A stop condition is a low-to-high transition on SDA while SCL is high. A start condition from the master device signals the AD5383 to begin a transfer. Parking conditions left the bus empty. If a Repeated Start condition (Sr) is generated instead of a Stop condition, the bus will remain active.
Repeated Start Condition
A Repeated Start (Sr) condition indicates a change in data direction on the bus. Sr can be used when a bus master is writing to multiple IC devices and wants to maintain control of the bus. 2
Acknowledgement Bit (ACK)
The Acknowledgement Bit (ACK) is the 9th bit appended to any 8-bit data word. ACK is always generated by the receiving device. The AD5383 device generates an ACK by pulling SDA low during the ninth clock cycle when receiving an address or data. Monitoring ACK allows detection of unsuccessful data transfers. Unsuccessful data transfers can occur if the receiving device is busy or has a system failure. If the data transfer is unsuccessful, the bus master should retry the communication.
AD5383 Slave
The bus master initiates communication with the slave by issuing a START condition preceded by a 7-bit slave address. When idle, the AD5383 waits for a start condition, followed by the slave address. The LSB of the address word is the read/write (R/W) bit. The AD5383 is a receive-only device; when communicating with the AD5383, R/W=0. After receiving the correct address 10101 (AD1) (AD0), the AD5383 issues an ACK by pulling SDA low for one clock cycle.
The AD5383 has four different user-programmable addresses determined by the AD1 and AD0 bits.
write operation
There are three specific modes for writing data to the AD5383 DAC.
4-byte mode
When writing to the AD5383 DAC, the user must begin with an address byte (R/W=0) after which the DAC confirms that it is ready to receive data by pulling SDA low. The address byte is followed by the pointer byte; this indicates the specific channel in the DAC to be addressed, which the DAC also acknowledges. Two bytes of data are then written to the DAC, as shown in Figure 31. A stop condition then occurs. This allows the user to update a single channel within the AD5383 at any time and requires four bytes of data to be transferred from the master node.
3-byte mode
In 3-byte mode, the user can update multiple channels in one write sequence without writing the device address byte each time. The device address byte is required only once; the subsequence channel update requires the pointer byte and the data byte. In 3-byte mode, the user starts with an address byte (R/W=0), after which the DAC confirms that it is ready to receive data by pulling SDA low. The address byte is followed by the pointer byte. This will address the specific channel to be addressed in the DAC, which will also be acknowledged by the DAC. Next are two data bytes. REG1 and REG0 determine which registers to update.
If the stop condition is not after the data byte, the other channel can be updated by sending a new pointer byte and data byte. This mode requires only three bytes to be sent to update any channel after the device is initially addressed and reduces software overhead when updating AD5383 channels. Anytime there is a stop state exiting this mode. Figure 32 shows a typical configuration.
2-byte mode
After 2-byte mode initialization, the user can update the channels sequentially. The device address byte is only needed once, and the address pointer is configured for auto-increment or burst mode.
The user must start with an address byte (R/W=0) after which the DAC confirms that it is ready to receive data by pulling SDA low. The address byte is followed by a specific pointer byte (0xFF) which initiates burst mode of operation. The address pointer is initialized to channel 0, the data behind the pointer is loaded into channel 0, and the address pointer is automatically incremented to the next address.
The REG0 and REG1 bits in the data byte determine which register is updated. In this mode, after initialization, only two data bytes are required to update the channel. The channel address is auto-incremented from address 0 to channel 31, then returns to normal 3-byte mode of operation. This mode allows data transfer to all channels in a block and reduces software overhead when configuring all channels. Anytime there is a stop state exiting this mode. Toggle mode is not supported in 2-byte mode. Figure 33 shows a typical configuration.
Parallel interface
The SE/PAR pin must be tied low to enable the parallel interface and disable the serial interface. Figure 7 shows the timing diagram for parallel writes. The parallel interface is controlled by the CS, WR, REG0, REG1, A4 to A0, and DB11 to DB0 pins.
CS pin
Active low device select pin.
WR pin
On the rising edge of WR, with CS low, the address on pins A4 to A0 is latched; the data on the data bus is loaded into the selected input register.
REG0, REG1 pins
The REG0 and REG1 pins determine the destination register for data written to the AD5383.
Pins A4 to A0
Each of the 32 DAC channels can be individually addressed.
Pins DB11 to DB0
The AD5383 accepts a direct 12-bit parallel word from DB11 to DB0, where DB11 is the most significant bit and DB0 is the least significant bit.
Microprocessor interface
Parallel interface
The AD5383 can be connected to various 16-bit microcontroller-controllers or digital signal processors. Figure 35 shows the AD5383 family interfacing with a general-purpose 16-bit microcontroller/DSP processor. The lower address line of this processor is connected to A4 on the AD5383. The above address line is decoded to provide CS and LDAC signals for AD5383. The timing of the fast interface AD5383 allows direct connection to microcontrollers and DSPs, as shown in Figure 35.
AD5383 to MC68HC11
The Serial Peripheral Interface (SPI) on the MC68HC11 is configured in master mode (MSTR=1), clock polarity bit (CPOL)=0 and clock phase bit (CPHA)=1. SPI is configured by writing to the SPI Control Register (SPCR) - see the 68HC11 User Manual. The SCK of the 68HC11 drives the SCLK in the AD5383, the MOSI output drives the AD5383's serial data line (DIN), and the MISO input is driven by DOUT. This sync signal comes from the port line (PC7). When data is sent to the AD5383 on the sync line, it is taken low (PC7). Data is displayed on the MOSI output on the falling edge of SCK. Sending serial data from the 68HC11 in 8-bit bytes, only 8 falling clock edges appear in the transfer cycle.
AD5383 to PIC16C6x/7x
The Synchronous Serial Port (SSP) is configured as an SPI master with the clock polarity bit set to 0. This is done by writing to the Synchronous Serial Port Control Register (SSPCON). See the PIC16/17 Microcontroller User's Manual. In this example I/O, port RA1 is used for pulse synchronization and enables the serial port of the AD5383. The microcontroller transfers only 8 bits of data during each serial transfer operation; therefore, depending on the mode, three consecutive read/write operations may be required. Figure 36 shows the connection diagram.
AD5383 to AD5383
A clock that is synchronized with the serial data is required. Therefore, the 8051 serial interface must operate in mode 0. In this mode, serial data is entered and exited through RXD, and a shift clock is output on TXD. Figure 37 shows how the 8051 is connected to the AD5383. Because the AD5383 shifts out data on the rising edge of the shift clock and latches the data on the falling edge, the shift clock must be inverted. The AD5383 requires its data to be MSB first. Because the 8051 outputs the LSB first, the transmit routine must take this into account.
AD5383 to ADSP-BF527
Figure 38 shows the serial interface between the AD5383 and the ADSP-BF527. The ADSP-BF527 should be set to operate in motion transmission alternate frame mode. The ADSP-BF527 SPORT is programmed through motion control registers and should be configured as follows: internal clock operation, active low frame, and 16-bit word length. After enabling motion, a transfer is initiated by writing a word to the Tx register.
application information
Power decoupling
In any circuit where accuracy is important, careful consideration of power and ground return layout helps ensure rated performance. The printed circuit board on which the AD5383 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5383 is in a system where multiple devices require an AGND to DGND connection, the connection should be made at only one point, a star ground point as close as possible to the devices.
For power supplies with multiple pins (AVDD, DVD), the pins should be tied together. The AD5383 should have adequate supplies, 0.1µF in parallel with 10µF on each supply, located as close to the package as possible, ideally facing the device. The 10µF capacitors are of the tantalum bead type. The 0.1µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like common ceramic types that provide a high frequency, low impedance path to ground to handle transient currents from internal logic switches.
The power lines to the AD5383 should use as large traces as possible to provide a low impedance path and reduce the effect of faults on the power lines. Fast switching signals such as clocks should use a digital ground shield to avoid radiating noise to other parts of the board and must not run near the reference input. A ground wire routed between the DIN and SCLK lines will help reduce crosstalk between them (this is not necessary on multilayer boards as there will be a separate ground plane, but separating the lines will help reduce crosstalk). Noise on the VIN and refill lines must be minimized.
Avoid crossover of digital and analog signals. The traces on opposite sides of the board should be at right angles to each other. This reduces feedthrough effects through the board. Micro-stripe technology is by far the best, but dual panels are not always possible. In this technique, the component side of the board is dedicated to the ground plane, while the signal lines are placed on the solder side.
Power sequence
For the AD5383 to work properly, use the DVD first, then use AVDD at the same time or within 10ms of the DVD. This sequence ensures that the power-on reset circuit sets the registers to their default values and holds the analog outputs at 0 V until a valid write occurs. A hardware reset is issued when AVDD cannot be applied within 10 ms of DVDD. This will trigger the power-on reset circuit and load the default register values. In the case where the initial power supply has the same or lower voltage as the second power supply, a Schottky diode can be used to temporarily supply power until the second power supply is turned on. Table 18 lists the power supply sequence and datasheet recommended diode connections. Alternatively, a load switch such as the ADP196 can be used to delay the first power supply until the second power supply is turned on. Figure 41 shows a typical configuration using the ADP196. In this case, AVDD is applied first. This voltage does not appear at the AVDD pin of the AD5383 until DVD is applied and the EN pin is raised. The result is that both AVDD and DVDD are applied to the AD5383.
Typical Configuration Circuit
Figure 43 shows a typical configuration of the AD5383-5 when used with external references. In the circuit shown, all a GND, SIGNAL-GND, and DAC-GND pins are connected to a common AGND. AGND and DGND are connected together on the AD5383 device. At power-up, the AD5383 defaults to external reference operation. All AVDD lines are tied together and driven from the same 5 V supply. 0.1µF ceramic and 10µF tantalum capacitors are recommended for decoupling close to the device. In this application, the reference for the AD5383-5 is provided externally from the ADR421 or ADR431 2.5 V reference. Suitable external references for the AD5383-3 include the ADR3412 1.2 V reference. The reference should be disconnected at the re-output/re-input pins of the device using a 0.1µF capacitor.
Figure 44 shows a typical configuration when using internal references. At power-up, the AD5383 defaults to an external reference; therefore, the internal reference needs to be configured and turned on by writing to the AD5383 control register. Control Register Bit CR10 allows the user to select the reference value; Bit CR8 selects the internal reference. It is recommended to use 2.5V reference voltage when AVDD=5V, and 1.25V reference voltage when AVDD=3V.
Numerical connections are omitted for clarity. The AD5383 contains an internal power-on reset circuit with a 10-millisecond power-up time. If the power supply ramp rate exceeds 10 ms, the user should reset the AD5383 during initialization to ensure that the calibration data is properly loaded into the device.
Channel monitoring function
The AD5383 includes a channel monitor function consisting of a multiplexer addressed through the interface, allowing any channel output to be routed to this pin for monitoring with an external ADC. Before routing any channel to MON U OUT, the channel monitor function must be enabled in the control register. Table 16 contains the decoding information needed to route any channel to MON_OUT. To tri-state MON U OUT, select channel address 63. Figure 45 shows a typical monitoring circuit using a 12-bit Synthetic Aperture Radar ADC in a 6-lead SOT-23 package. The controller output port selects the channel to be monitored, and the input port reads the converted data from the ADC.
Switch mode function
The toggle mode feature allows the output signal to be generated using the LDAC control signal that toggles between the two DAC data registers. This function uses the SFR control register to configure as follows. Use REG1=REG0=0 and A4 to write A0=01100 to specify the control register write. The toggle mode function is enabled in groups of eight channels using bits CR3 to CR0 in the control register. See the AD5383 Control Register Write/Read section. Figure 46 shows a block diagram of the switching mode implementation. Each of the 32 DAC channels on the AD5383 contains A and B data registers. Note that the B register can only be loaded when toggle mode is enabled. The sequence of events when configuring the AD5383 for switching mode is:
1. Enable toggle mode for the desired channel via the control register.
2. Load the data into the register.
3. Load the data into the B register.
4. Apply LDAC.
The LDAC is used to switch between the A and B registers to determine the analog output. The first LDAC configures the output to reflect the data in the A register. This mode offers a significant advantage if the user wishes to generate square waves at the outputs of all 32 channels, as a liquid crystal-based variable optical attenuator may need to be driven. In this case, the user writes to the control register and enables the toggle function by setting CR3 to CR2=1, thus enabling four groups of eight for toggle mode operation. The user must then load data into all 32 A and B registers. Toggling the LDAC sets the output value to reflect the data in the A and B registers. The frequency of the LDAC determines the frequency of the square wave output.
The toggle mode is disabled through the control register. The first LDAC after disabling the toggle mode updates the output with the data contained in the A register.
Thermal monitoring function
The AD5383 has a temperature shutdown feature to protect the chip when multiple outputs are shorted. The short-circuit current of each output amplifier is typically 40 mA. Operating the AD5383 at 5 volts, each shorted amplifier dissipates 200 mW. This equates to additional watts of power dissipation when five channels are shorted. For 100-lead LQFP, θJA is typically 44°C/W.
The thermal monitor is enabled by the user via CR6 in the control register. The output amplifier on the AD583 automatically powers down if the die temperature exceeds about 130°C. After a thermal shutdown, if the temperature drops below 130°C, or if the thermal monitor function is turned off by registering the seat, the user can re-enable the section by restarting the soft power.
Optical attenuator
Based on its high channel count, high resolution, monotonicity, and high level of integration, the AD5383 is ideal for optical attenuation applications in dynamic gain equalizers, variable optical attenuators (VOAs), and optical add-drop multiplexers (OADMs). In these applications, each wavelength is extracted individually using an arrayed waveguide; its power is monitored via a photodiode - an ance amplifier and ADC in a closed-loop control system. The AD5383 controls the optical attenuator for each wavelength, ensuring that the power at all wavelengths is equalized before multiplexing onto the fiber. This prevents information loss and saturation from occurring during further amplification stages along the fiber.
Utilize first in first out
The AD5383 FIFO mode optimizes the overall system update rate in applications that need to update a large number of channels. FIFO mode is only available when parallel interface mode is selected. The FIFO EN pin is used to enable the FIFO. The state of FIFO EN is sampled during initialization. Therefore, the FIFO state can only be changed by resetting the device. For example, in telescopes that provide atmospheric distortion cancellation, a large number of channels need to be updated in a short period of time. Up to 320 channels need to be updated in the range of 25 to 30 microseconds in such a system. 320 channels require the use of 10 AD5383s. With FIFO mode enabled, the data write cycle is 40 ns; therefore, each group of 32 channels can be fully loaded in 1.28 microseconds. In FIFO mode, a full set of 32 channels is updated in 11.5 microseconds. The time required to update all 320 channels is 11.5 microseconds + 9 x 1.28 microseconds = 23 microseconds. Figure 48 shows the FIFO operation scheme.
Dimensions