illustrate

Available in 8-pin dip or SO-8 package types respectively, the HCPL-772X or HCPL-072X optocouplers utilize the latest CMOS integrated circuit technology to achieve excellent performance with extremely low power consumption. The HCPL-772X/072X only needs two bypass capacitors to achieve full CMOS compatibility. The basic building blocks of the HCPL-772X/072X are the CMOS LED driver chip, high-speed LED and CMOS detector integrated circuits. A CMOS logic input signal controls the LED driver chip to supply current to the LED. The detector integrated circuit includes an integrated photodiode, high-speed transconductance amplifier, and voltage comparator output driver.

Pin 3 is the anode of the internal LED and must be left unconnected for datasheet performance. Pin 7 is not connected internally. A 0.1µF bypass capacitor must be connected between pins 1 and 4, 5 and 8

feature

+5 V CMOS compatibility with 20 ns max strut. Delay bias

High Speed: 25 MBd

Maximum 40 ns strut. Delay

10 kV/µs minimum common mode rejection

-40 to 85°C temperature range

Safety and Regulatory Approvals

UL recognized

3750 Vrms per UL 1577 for 1 minute

5000 Vrms for 1 minute per UL 1577 (for HCPL-772X option 020)

CSA Parts Acceptance Notice #5

IEC/EN/DIN standard EN60747-5-5

For HCPL-772X option 060, VIORM=630 V peak

For HCPL-072X option 060, VIORM=567 V peak

application

Digital Fieldbus Isolation: CC-Link, DeviceNet, Profibus, SDS AC Plasma Display Panel Horizontal Movement

multiplex data transmission

computer peripheral interface

Microprocessor System Interface

Reflow Soldering Thermal Profile

Recommended reflow conditions are in accordance with JEDEC Standard J-STD-020 (latest edition). Non-halide flux should be used

All Avago datasheets report the leakage and gaps inherent in the optocoupler assembly itself. These are the starting point requirements that equipment designers need when determining circuit insulation. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must meet the specified standards for individual devices. The surface of the printed circuit board between the solders for creepage must account for the rounded corners of the input and output leads. There are recommended techniques such as grooves and ribs that can be used on printed circuit boards to achieve the required creepage and clearance. Creep and clearance distances also vary based on factors such as pollution levels and insulation levels.

Refer to the optocoupler section in the Isolation and Control Component Designer's Catalog, in the Product Safety Regulations section (IEC/ for detailed instructions on Method a and Method b partial discharge test profiles.

Note: These optocouplers are only suitable for "safe electrical isolation" within the safety limit data. The maintenance of safety data is ensured through the protection circuit. Surface mount is classified as Class A according to CECC 00802.

Electrical Specifications

Unspecified test conditions can be anywhere within the recommended operating range.

All typical specifications are TA=+25°C, VDD1=VDD2=+5 V.

notes:

1. The absolute maximum ambient operating temperature means that the equipment will not be damaged if operated under these conditions. It has no guaranteed functionality.

2. When VI When VI is high.

3. tPHL propagation delay is the signal measured from the 50% level of the falling edge of VI to the 50% level of the falling edge of the VO signal. The tPLH propagation delay is the signal measured from the 50% level of the rising edge of VI to the 50% level of the rising edge of the VO signal.

4.PWD is defined as |tPHL-tPLH|. %PWD (Percent Pulse Width Distortion) is equal to PWD divided by the pulse width.

5. tPSK is equal to the recommended operating conditions for the worst case difference in tPHL and/or tPLH between units over a given temperature range.

6.CMH is the maximum common mode voltage slew rate that can be maintained while maintaining VO>0.8 VDD2. CML is the greatest common denominator to maintain the mode voltage slew rate while maintaining VO < 0.8V. The common-mode voltage slew rate applies to rising and falling common-mode voltage edges.

7. The no-load dynamic power consumption is calculated as follows: CPD*VDD2*f+IDD*VDD, where f is the switching frequency in MHz.

8. A device that is considered a two-terminal device: pins 1, 2, 3, and 4 are shorted together, and pins 5, 6, 7, and 8 are shorted together.

9. According to UL1577, each HCPL-072X is verified by applying insulation test voltage ≥4500 VRMS for 1 second (leak detection current limit, II-O≤5μA). Each HCPL-772X is verified to test current limit by applying insulation test voltage ≥4500 Vrms for 1 second (leak detection). II-O≤5μA)

10. The input and output instantaneous withstand voltage is the dielectric voltage rating and should not be interpreted as the input and output continuous rated voltage. For continuous voltage ratings, see Equipment Level Safety Specifications or Avago Application Note 1074 "Optocoupler Input Output Continuous Voltage"

11. Competitive intelligence is the capacitance measured at pin 2 (VI)

Application Information Bypass and PC Board Layout

The HCPL-772X/072X optocouplers are very easy to use. No external interface circuit is required because the HCPL-772X/072X uses high-speed CMOS integrated circuit technology, allowing CMOS logic to be directly connected to the input as well as the output. As shown in Figure 10, the only external components required for proper operation are two bypass capacitors. The capacitor value should be between 0.01µF and 0.1µF. For each capacitor, the total lead length between the capacitor and power pins should not exceed 20mm. Figure 11 shows the recommended board layout for printing the HPCL-772X/072X.

Propagation Delay, Pulse Width Distortion, and Propagation Delay Deviation Propagation delay is an advantage that describes the speed at which logic signals travel through a system. This low-to-high propagation delay (tPLH) is the propagation of the input signal to the output, causing the output to go from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time it takes for the input signal to propagate to the output, causing the output to change from high to low. See Figure 12.

Pulse Width Distortion (PWD) is TPHL and TPLH and usually determines the rate capability of the maximum data transfer system. PWD can be divided by PWD (ns) by the minimum pulse width (ns) of the transmission. Typically, a pulse width of 20-30% of the minimum pulse width is acceptable. Propagation delay skew is an important parameter to consider In parallel data applications, signal synchronization on parallel data lines is an issue. If parallel data is sent through a set of optocouplers, differences in propagation delay will result in data arriving at the optocoupler output at different times. If the difference in propagation delay is large enough, it will determine the maximum rate parallel data can be sent through the optocoupler. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, tPLH or tPHL, for any given optocoupler group operating under the same conditions (i.e. same drive current, supply voltage, output load and operating temperature) . As shown in Figure 13, tPSK is the shortest propagation delay, tPLH or tPHL, and the longest propagation delay, tPLH or tPHL, if the inputs of a group of optocouplers are turned on or off at the same time. As mentioned earlier, TPSK can determine the maximum value. Parallel data transfer rate. Figure 14 is a diagram of a typical parallel data application timing clock and data lines sent through optocouplers. This figure shows the input and output of an optocoupler. In this case the data slave clock is assumed.

Propagation delay skew indicates where an edge might be sent through an optocoupler. Figure 14 shows the uncertainty on the data and clock lines. It is important that the two uncertainty regions do not overlap, otherwise the clock signal may arrive before all data outputs are resolved, or some data outputs may start changing before the clock signal arrives. Based on these considerations, the absolute minimum pulse width that can be sent through an optocoupler in a parallel application is two tPSKs. A prudent design should use a slightly longer pulse width to ensure that the rest of the circuit does not cause a malfunction. The HCPL-772X/072X optocouplers offer guaranteed specifications for superior propagation delay, pulse width distortion and propagation delay deviation over recommended temperature and power supply ranges.

Digital Fieldbus Communication Networks To date, despite its many shortcomings, the 4-20 mA analog current loop has been the most widely accepted standard for process control system implementation. In today's manufacturing environment, however, automated systems are expected to help manage the process, not just monitor it. With the advent of digital fieldbus communication networks such as CC-Link, DeviceNet, PROFIBUS and Intelligent Distributed Systems (SDS) disappeared were the days of limited information. The controller can now receive multiple readings from field devices (sensors, actuators, etc.) in addition to diagnostic information. The physical model communication network for these digital fieldbuses is very similar, as shown in Figure 15. Each includes one or more buses, an interface unit, optical isolation, transceivers, and sensing and/or actuation means.

Optical Isolation of Fieldbus Networks To fully realize the benefits of these networks, Avago recommends using optocouplers to provide galvanic isolation. Because network communication is bidirectional (including receiving data and transmitting data to the network), two Avago optocouplers are required. By providing galvanic isolation, data integrity is maintained by reducing noise and eliminating false signals. Furthermore, the network is protected to the maximum. From power system faults and ground loops. Within an isolated node, such as the DeviceNet node shown in Figure 16, some components of the node are not referred to the V-ground of the network. Figure 16. Typical DeviceNet Nodes These components can include devices with serial ports, parallel ports, RS-232 and RS-485 type ports. As shown in Figure 16, power from the network is used only for transceivers and optocouplers. An isolated digital fieldbus network connected to one of the three types of nodes is best to use HCPL-772X/072X optocouplers. For each network the HCPL-772X/072X meet critical propagation delay and pulse width distortion requirements over a temperature range of 0°C to +85°C and a supply voltage range of 4.5V to 5.5V.

Implementing CC-Link with HCPL-772X/072X Developed CC-Link (Control and Communication Link) to integrate control and information in the underlying network (field network) through a PC, thereby making a multi-vendor environment a reality. It has data control and message exchange functions, as well as bit control functions, and operates at speeds up to 10 Mbps. Figure 17. Recommended CC Link Application Circuit Power and Bypass The recommended CC link circuit is shown in the figure. Because the HCPL-772X/072X are fully compatible using CMOS logic level signals, the optocoupler is directly connected to the transceiver. Two bypass capacitors (values between 0.01 and 0.1 μF) are required and should be placed as close as possible to the input and output power pins of the HCPL-772X/072X. For each capacitor, the total lead length between the two capacitor ends and the power pins should not exceed 20mm. Bypass capacitors are required due to the high-speed digital nature of the signal inside the optocoupler.

When using the HCPL-772X/072X to implement DeviceNet and SDS with transmission rates up to 1 Mbit/s, both DeviceNet SDSs are based on the same broadcast-oriented, communication protocol - Controller Area Network (Yes). Three types of stand-alone nodes are recommended for these networks: powered by the network (Figure 18), stand-alone nodes with transceivers powered by the network (Figure 19), and stand-alone nodes powered by the network (Figure 20). Figure 18. Standalone nodes powered by the network. Network Powered Standalone Node with Transceiver Figure 19 shows that there is another source of information for a node powered by two networks. In this case, the transceiver and the isolated (network) side of the two optocouplers are powered by the network. The rest of the node requires a lot of energy from the AC line which is very useful when applied. This method is also preferable because it does not overload the network. What's more, the unique "dual inversion" design of the HCPL-772X/072X ensures that AC line power at the node is lost or the node shuts down. Specifically, when the input power (VDD1) to the HCPL-772X/072X is removed in the transmission path, a recessive bus state is ensured as the HCPL-772X/072X output voltage (VO) is too high. Network Powered Standalone Nodes This type of node is very flexible, as shown in the figure.

Figure 18 is considered "isolated" because the components have the same ground reference. However, all components are still powered by the network. This node contains two supervisors: one is independent for the controller, node-specific application and isolates (nodes) the two optocoupler edges, and the other is non-isolated. A non-isolated regulator provides the transceiver and two optocouplers. Bus V+ Sensing It is recommended to implement the Bus V+ detection block shown in Figure 19. An isolated PHY with no power accumulates errors and shuts down the bus when attempting to transmit. The bus V+ heartbeat will be used to change the BOI property of the DeviceNet object to an "autoreset" (01) value. See Volume 1, Section 5.5.3. This causes the node to keep resetting until bus power is detected. Once power is detected, the BOI property will return to the "Wait for bus down" (00) value. The BOI attribute should not be kept in the "auto reset" (01) value as this would break the errorable limit. Any inexpensive low frequency opto-isolator can be used for this function.

Standalone Nodes Powering the Network Figure 20 shows the nodes supplying power to the network. The AC line powers a regulator that supplies 5 volts locally. The AC line also powers the 24V isolated power supply to power the network, another 5V regulator, and one of the two optocouplers on the transceiver power and isolated (network) side. This method is recommended when there are a limited number of devices on the network that don't require much power and therefore don't need a separate power supply. Figure 19. Standalone node with network powered transceivers. What's more, the unique "dual inversion" design of the HCPL-772X/072X ensures that AC line power at the node is lost or the node shuts down. Specifically, when the input power (VDD1) to the HCPL-772X/072X is removed in the transmission path, a recessive bus state is ensured as the HCPL-772X/072X output voltage (VO) is too high.

Power and Bypass

The recommended DeviceNet application circuit is shown in Figure 21. Because the HCPL-772X/072X is fully compatible with CMOS logic level signals, the optocoupler is directly connected to the CAN transceiver. Two bypass capacitors (values between 0.01 and 0.1µF) are required and should be placed as close as possible to Figure 21. Recommended equipment network application circuit Implement PROFIBUS with HCPL-772X/072X PROFIBUS is the abbreviation of process field bus, which is essentially a twisted pair serial link very similar to RS-485 to achieve high-speed communication up to 12MBd. As shown in Figure 22, a PROFIBUS controller (PBC) establishes a field automation unit (control or central processing station) or field device and transmission medium. The PBOC includes a transceiver, optical isolation, framed character transmitter/receiver (UART) and has an interface with PROFIBUS users. Figure 22. Fieldbus Controller (PBC) to HCPL input and output power pins - 772X/072X. For each capacitor, the total lead length between the ends of the capacitor and the power pin should not exceed 20 mm. Bypass capacitors are required because of the signal inside the optocoupler.

Power and Bypass

The recommended PROFIBUS application circuit is as shown in Figure 23. Because the HCPL-772X/072X is fully compatible with CMOS logic level signals, the optocoupler is directly connected to the transceiver. Double bypass capacitors (values between 0.01 and 0.1µF) are required and should be placed as close as possible to the input and output power pins of the HCPL-772X/072X. For each capacitor, the total lead length between the ends of the capacitor and the power pin should not exceed 20 mm. Bypass capacitors are required because of the signal inside the optocoupler. Much like a multi-drop RS485 system, the HCPL-061N optocoupler provides transmit disable enabling the bus during each master/slave transmit cycle. Specifically the HCPL-061N by putting it into high state mode. In addition, the HCPL-061N switches the RX/TX driver IC to listen mode. The HCPL-061N offers HCMO compatibility and high CMR performance (1kV/µs at VCM=1000 V) critical in industrial communication interfaces.