feature

SNR=71.8dbc (72.8dbfs) to 70mhz@125msps; SFDR=85 dBc to 70 MHz@125 MSPS; Low Power: 750mW@125ms/s; SNR=71.6dbc (72.6dbfs) to 70mhz @150msps; SFDR=84 dBc to 70 MHz @ 150 MSPS; Low Power: 820 mW @ 150 ms/s; 1.8V analog supply operation; 1.8 V to 3.3 V CMOS output supply or 1.8 V LVD; output supply; integer 1 to 8 input clock divider; if sampling frequency up to 450 MHz; internal ADC voltage reference; integrated ADC sample and hold input; flexible analog input range: 1 volt P to 2 VPP; differential analog input with 650 MHz bandwidth; Null ratio stabilizer; 95dB channel isolation/crosstalk; serial port control; user-configurable built-in self-test (BIST) function; power-saving power-down mode; integrated receive function; fast detect/threshold bits;

application

Communication; diversity radio system; multi-mode digital receiver; GSM, EDGE, WCDMA, LTE, CDMA2000, WiMAX, TD-SCDMA; I/Q demodulation system; smart antenna system; general software radio; broadband data applications.

Product Highlights

1. Integrated dual 14-bit 80/105/125/150 MSPS analog-to-digital converters.

2. Fast over-range detection and serial output signal monitoring.

3. Signal monitor block with dedicated serial output mode.

4. Proprietary differential input, maintains good signal-to-noise performance at input frequencies up to 450 MHz.

5. Operation of a 1.8V power supply and a separate digital output drive power supply to accommodate 1.8V to 3.3V logic families.

6. A standard serial port interface that supports various product features and functions, such as data formatting (offset binary, duplex or gray coding), support for clock DCS, power down and voltage reference modes.

7. Pin compatibility with AD9627, AD9627-11 and AD9600 for easy migration from 14-bit to 12-bit, 11-bit or 10-bit.

General Instructions

The AD9640 is a dual 14-bit 80/105/125/150 MSPS analog-to-digital converter (ADC). The AD9640 is designed to support communications applications requiring low cost, small size, and versatility.

The dual ADC core adopts a multi-stage differential pipeline structure and integrates output error correction logic. Each ADC features a wideband differential sample-and-hold analog input amplifier that supports multiple user-selectable input ranges. An integrated voltage reference simplifies design considerations. A duty cycle stabilizer is provided to compensate for changes in the ADC clock duty cycle, allowing the converter to maintain excellent performance.

The AD9640 has several features that simplify the automatic gain control (AGC) function in the system receiver. The fast detection function allows fast out-of-range detection, outputting 4-bit input stage information with very low latency.

Additionally, a programmable threshold detector allows monitoring of input signal power using the ADC's four fast detect bits with very low latency. If the input signal level exceeds a programmable threshold, the fine upper threshold indicator goes high. Since this threshold is set from four msb, the user can quickly reduce the system gain to avoid overrange conditions.

The second AGC-related function is the signal monitor. This block allows the user to monitor the composite amplitude of the input signal, which helps to set the gain to optimize the dynamic range of the overall system.

ADC output data can be routed directly to two external 14-bit output ports. These outputs can be programmed from 1.8 V to 3.3 V CMOS or 1.8 V LVD.

Flexible power-down options allow large power savings when needed.

Programming for setup and control is done using a 3-bit SPI-compatible serial interface.

The AD9640 is available in a 64-lead LFCSP and is specified over the industrial temperature range of -40°C to +85°C.

Equivalent Circuit

theory of operation

The AD9640 dual ADC design can be used for signal diversity reception, where the ADCs operate on the same carrier, but from two separate antennas. ADCs can also be operated with separate analog inputs. The user can use appropriate low-pass or band-pass filtering at the ADC input to sample any f/2 frequency band from dc to 200mhz with little loss of ADC performance. Operation on the 450mhz analog input is allowed, but at the expense of increased ADC distortion.

In non-dispersive applications, the AD9640 can be used as a baseband receiver with one ADC for the I input data and the other for the Q input data.

A synchronization function is provided, allowing timing to be synchronized across multiple channels or multiple devices.

Programming and control of the AD9640 is done using a 3-bit SPI compatible serial interface.

ADC Architecture

The AD9640 architecture consists of a dual front-end sample-and-hold amplifier (SHA) and a pipelined switched capacitor ADC. In the digital correction logic, the quantized outputs from each stage are combined into a final 14-bit result. The pipelined architecture allows the first stage to operate on a new input sample and the remaining stages to operate on previous samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last stage, consists of a low-resolution flash ADC connected to a switched-capacitor digital-to-analog converter (DAC) and an interstage residual amplifier (MDAC). The residual amplifier amplifies the difference between the reconstructed DAC output and the flash input in the next stage of the pipeline. One bit redundancy is used per stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC.

The input stage of each channel contains a differential SHA that can be ac or dc coupled in differential or single-ended mode. The output scratch block aligns the data, performs error correction, and passes the data to the output buffer. The output buffer is powered by a separate supply, allowing the output voltage swing to be adjusted. During power down, the output buffers go into a high impedance state.

Analog Input Considerations

The analog input to the AD9640 is a differential switched capacitor SHA designed for optimum performance when dealing with differential input signals.

The clock signal alternately switches the SHA between sample mode and hold mode (see Figure 45). When the SHA switches to sampling mode, the signal source must be able to charge the sampling capacitor and settle within 1/2 of the clock period.

Small resistors in series with each input help reduce the peak transient current required to drive the source output stage. A parallel capacitor can be placed at the input to provide dynamic charging current. This passive network creates a low-pass filter at the ADC input; therefore, the exact value depends on the application.

In IF undersampling applications, any parallel capacitors should be reduced. Combined with the driving source impedance, they limit the input bandwidth. See AN-742 Application Note, Frequency Domain Response of Switched Capacitor ADCs; AN-827 Application Note, Resonance Method for Connecting Amplifiers to Switched Capacitors

ADC and Analog Dialogue article, "Transformer-Coupled Front Ends for Wideband A/D Converters" Learn more about this topic.

For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched.

An internal differential reference buffer generates positive and negative reference voltages that define the input range of the ADC core. The span of the ADC core is set by the buffer to be 2 × VREF.

Input common mode

The analog inputs of the AD9640 have no internal dc bias. In AC-coupled applications, the user must provide this bias externally. Set the device to V = 0.55 × AVDD for best performance, but the device has a wider range of functions and reasonable performance (see Figure 44). An on-board common-mode voltage reference is included in the design, available from the CML pin. Best performance is obtained when the common-mode voltage of the analog inputs is set by the CML pin voltage (typically 0.55 × AVDD). The CML pin must be separated from ground by a 0.1µF capacitor, as described in the Applications Information section.

Differential Input Configuration

Best performance is obtained when driving the AD9640 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible ADC interface.

The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9640 (see Figure 46), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.

For baseband applications where signal-to-noise ratio is a critical parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 47. To bias the analog input, the CML voltage can be connected to the center tap of the transformer secondary winding.

Signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz, and excessive signal power can also cause the core to saturate, resulting in distortion.

At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is insufficient to achieve the true SNR performance of the AD9640. For applications where signal-to-noise ratio is a critical parameter, a differential dual balun coupled input configuration is recommended (see Figure 49 for an example).

An alternative to using a transformer-coupled input at the frequency of the second Nyquist zone is to use the AD8352 differential driver. An example is shown in Figure 50. See the AD8352 data sheet for more information.

In any configuration, the value of the shunt capacitor C depends on the input frequency and source impedance and may need to be reduced or removed. Table 13 shows suggested values for setting up the RC network. However, these values are dependent on the input signal and should only be used as a start-up guide.

Single-ended input configuration

Single-ended inputs can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to excessive input common-mode oscillation. If the source impedances at each input are matched, there should be little impact on the SNR performance. Figure 48 details a typical single-ended input configuration.

voltage reference

A stable and accurate voltage reference is built into the AD9640. The input range can be adjusted by changing the reference voltage applied to the AD9640 using the internal reference voltage or an externally applied reference voltage. The input range of the ADC tracks linear changes in the reference voltage. Various reference modes are summarized in the following sections. The Reference Decoupling section describes the reference best practice PCB layout.

Internal reference connection

The comparator within the AD9640 senses the potential at the sense pin and configures the reference into four possible modes, as shown in Table 14. If the sensor is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 51), setting VREF to 1V. Connecting the sensor pin to VREF switches the reference amplifier output to the sensor pin, completing the loop and providing a 0.5V reference output. As shown in Figure 52, if the resistor divider is connected outside the chip, the switch is again set to the sense pin. This puts the reference amplifier in a non-vertical mode and the VREF output is defined as:

The input range of the ADC is always equal to twice the reference pin voltage of the internal or external reference.

If the AD9640's internal reference is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 53 shows the effect of load on the internal reference voltage.

An external reference may be required to improve the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 54 shows the typical drift characteristics of the internal reference in 1V mode.

When the sense pin is tied to AVDD, internal references are disabled, allowing external references to be used. The internal reference buffer loads the external reference with an equivalent 6 kΩ load (see Figure 15). Internal buffers generate positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1 V.

Clock Input Considerations

For best performance, the AD9640 sampling clock input CLK+, and CLK- should be clocked with differential signals. Signals are typically AC coupled to the CLK+ and CLK- pins through transformers or capacitors. These pins are internally biased (see Figure 55) and do not require external biasing.

Clock input options

The AD9640 has a very flexible clock input structure. The clock input can be CMOS, LVDS, LVPECL, or a sine wave signal. Regardless of the type of signal used, the jitter of the clock source is of greatest concern, as described in the Jitter Considerations section.

Figure 56 and Figure 57 show the two preferred methods for clocking the AD9640 (clocked at 625 MHz). Low-jitter clock sources use RF baluns or RF transformers to convert from single-ended to differential signals. For clock frequencies between 125 MHz and 625 MHz, an RF balun configuration is recommended; for clock frequencies between 10 MHz and 200 MHz, an RF transformer is recommended. Back-to-back Schottky diodes across the transformer/balun quadratic limit the clock skew to the AD9640 to a P-P differential of approximately 0.8 V.

This helps prevent large voltage fluctuations of the clock through the rest of the AD9640 while maintaining fast rise and fall times for signals that are critical for low jitter performance.

If a low-jitter clock source is not available, another option is to AC-couple the differential PECL signal to the sampling clock input pins, as shown in Figure 58. The AD9510/AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock drivers provide excellent jitter performance.

A third option is to AC couple the differential LVDS signal to the sample clock input pins, as shown in Figure 59. The AD9510/AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock drivers provide excellent jitter performance.

In some applications, it is acceptable to drive the sampling clock input with a single-ended CMOS signal. In this application, CLK+ should be driven directly from the CMOS gate, and the CLK- pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 60).

CLK+ can be driven directly from the CMOS gate. Although the CLK+ input circuit power supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.6 V, making the choice of drive logic voltage very flexible.

input clock divider

The AD9640 includes an input clock divider capable of dividing the input clock by an integer value between 1 and 8. If a distribution ratio other than 1 is selected, the duty cycle stabilizer will automatically be enabled.

The AD9640 clock divider can be synchronized using an external synchronization input. Bit 1 and Bit 2 of Register 0x100 allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after a register write. A valid synchronization causes the clock divider to reset to its initial state. This synchronization feature allows alignment of clock dividers in multiple sections to ensure simultaneous input sampling.

clock duty cycle

Typical high-speed ADCs use two clock edges to generate various internal timing signals, and the results can be sensitive to the clock duty cycle. Typically, a ±5% tolerance is required for the clock duty cycle to maintain dynamic performance characteristics.

The AD9640 contains a duty cycle stabilizer (DCS) that retimes the non-sampling (falling) edges to provide an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9640. With the DCS on, the noise and distortion performance is nearly flat over a wide range of duty cycles, as shown in Figure 43.

Jitter on the rising edge of the input is still the most important issue and is not easily reduced by the internal stabilization circuit. The duty cycle control loop is generally not suitable for clock frequencies less than 20 MHz. This loop has a time constant associated with it, which needs to be taken into account when the clock rate can change dynamically. This requires a 1.5µs to 5µs latency after the dynamic clock frequency is increased or decreased before the DCS loop relocks to the input signal. During this time period, the loop is not locked, the DCS loop is bypassed, and the internal device timing depends on the duty cycle of the input clock signal. In this application, the duty cycle stabilizer can be appropriately disabled. In all other applications, DCS circuits are recommended to maximize AC performance.

Jitter Considerations

High-speed, high-resolution ADCs are very sensitive to the quality of the clock input. At a given input frequency (f), the low-frequency signal-to-noise ratio (SNR) attenuation due to jitter (t) can be obtained by:

In the equation, rms aperture jitter represents the clock input jitter specification. If the undersampling application is particularly sensitive to jitter, as shown in Figure 62.

When aperture jitter may affect the dynamic range of the AD9640, the clock input should be treated as an analog signal. The power supply for the clock driver should be separated from the ADC output driver power supply to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators are the best clock source. If the clock is generated from another type of source (by gating, division, or other methods), it should be retimed by the original clock in the last step.

For more information on ADC-related jitter performance, see AN-501 Application Note and AN-756 Application Note.

Power Consumption and Standby Modes

As shown in Figure 63, the power consumption of the AD9640 is proportional to its sampling rate. In CMOS output mode, the digital power consumption depends primarily on the strength of the digital drivers and the load on each output bit.

The maximum DRVDD current (i) can be calculated as:

where N is the number of output bits (30 in the case of the AD9640 with the FD bit disabled). When each output bit toggles on each clock cycle, a complete square wave occurs at the Nyquist frequency of F/2. In practical applications, the DRVDD current is determined by the switching quantity of the average output bits, which is determined by the sampling rate and the characteristics of the analog input signal.

Reducing the capacitive loading of the output driver can minimize digital power consumption. The data in Figure 63 was acquired under the same operating conditions as the typical performance characteristics, with a 5 pF load on each output driver.

By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD9640 is placed in power-down mode. In this state, the ADC typically dissipates 2.5mW. When powered down, the output drivers are in a high impedance state. Asserting the PDWN pin low returns the AD9640 to its normal operating mode. Note that PDWN refers to the digital power supply (DRVDD), which should not be exceeded.

Low power consumption in shutdown mode is achieved by turning off the reference, reference buffer, bias network and clock. Internal capacitors are discharged when entering power-down mode and must then be recharged when normal operation is resumed. Therefore, the wake-up time is related to the time spent in power-down mode, and a shorter power-down period will reduce the wake-up time accordingly.

When using the SPI port interface, the user can place the ADC in power-down or standby mode. Standby mode allows the user to keep the internal reference circuit powered up when a faster wake-up time is required. See the Memory Mapped Register Descriptions section for details.

digital output

The AD9640 output driver can be configured to interface with 1.8 V to 3.3 V CMOS logic families by matching DRVDD to the digital supply of the interface logic. The AD9640 can also be configured as an LVDS output using a DRVDD supply voltage of 1.8V.

In CMOS output mode, the output drivers are sized to provide enough output current to drive various logic families. However, large drive currents tend to cause current glitches on the power supply, affecting converter performance.

Applications that require the ADC to drive large capacitive loads or large fanouts may require external buffers or latches.

When operating in external pin mode, the output data format can be selected for offset binary or two's complement by setting the SCLK/DFS pin (see Table 15).

As described in the AN-877 application note, through the SPI interface to the high-speed ADC, when using SPI control, the data format of offset binary, two's complement, or gray code can be selected.

Digital output enable function (OEB)

The AD9640 has the ability to have flexible three-state digital output pins. Tri-state mode is enabled using the SMI SDO/OEB pins or via the SPI interface. If the SMI SDO/OEB pin is low, the output data driver is enabled. If the SMI SDO/OEB pin is high, the output data driver is in a high impedance state. This OEB function is not intended for fast access to the data bus. Note that OEB refers to the digital power supply (DRVDD), which should not be exceeded.

When using the SPI interface, the data and fast detect outputs for each channel can be independently asserted three times by using the output enable bar bits in Register 0x14.

opportunity

The AD9640 provides latched data with a pipeline delay of 12 clock cycles. The data output is available one propagation delay (t) after the rising edge of the clock signal.

The length and loading of the output data lines should be minimized to reduce transients within the AD9640. These transients degrade the dynamic performance of the converter.

The minimum typical conversion rate of the AD9640 is 10msps.

Dynamic performance degrades when the clock rate is lower than 10ms/sec.

Data Clock Out (DCO)

The AD9640 provides two data clock output (DCO) signals for capturing data in external registers. The data output is valid on the rising edge of the DCO, unless the DCO clock polarity has been changed via the SPI.

ADC overrange and gain control

In receiver applications, it is desirable to have a mechanism to reliably determine when the converter will be clipped. The standard overflow indicator provides post-mortem information about the state of the analog input, but its usefulness is limited. Therefore, it is helpful to have a programmable threshold below full scale that allows the time to reduce the gain before clipping actually occurs. Furthermore, since the input signal can have a significant slew rate, the latency of this function is a major concern. Highly pipelined converters can have significant delays. A good compromise is to use the output bits of the first stage of the ADC for this function. The latency of these output bits is very low and the overall resolution is not high. Peak input signals are typically between 6dB and 10dB below full scale to full scale. A 3-bit or 4-bit output provides sufficient range and resolution for this function.

Using the SPI port, the user can provide a threshold above which the overrange output will be active. The output should remain low as long as the signal is below this threshold. The fast detect output can also be programmed through the SPI port so that one of the pins can act as a legacy overrange pin for customers currently using this feature. In this mode, all 14 bits of the converter are checked in the traditional way, and the output is high in what is usually defined as overflow. In either mode, the size of the data (but not the sign of the data) is considered when evaluating the condition. Threshold detection responds equally to positive and negative signals outside the expected range (amplitude).

Quick Test Overview

The AD9640 contains circuitry that facilitates fast overrange detection, allowing a very flexible implementation of external gain control. Each ADC has four fast detect (FD) output pins that output information about the current state of the ADC's input levels. The function of these pins is programmable through the fast detect mode select bits and fast detect enable bits in Register 0x104, allowing range information to be output from multiple points in the internal datapath. Based on programmable threshold levels, these output pins can also be set to indicate the presence of an overrange or overrange condition. Table 17 shows the six configurations available for fast detect pins.

ADC fast amplitude

When the fast detect output pin is configured to output ADC fast amplitude (ie, when the fast detect mode select bit is set to 0b000), the information presented is from a delay of only two clock cycles (in CMOS output mode) ADC levels of early converter stages. Using the fast detect output pin in this configuration provides the earliest indication of the liquid level. Since this information is provided early in the data path, there is significant uncertainty in the level indicated. Table 18 shows the nominal level and the uncertainty represented by the ADC fast amplitude.

A subset of the fast detect output pins are available when the fast detect mode select bits are set to 0b001, 0b010, or 0b011. In these modes, the fast detect output pins have a delay of 6 clock cycles. Table 19 shows the corresponding ADC input levels when the fast detect mode select bits are set to 0b001 (that is, when the ADC fast amplitude is displayed on the FD[3:1] pins).

When the fast detect mode select bits are set to 0b010 or 0b011 (ie, when ADC fast amplitude is present on the FD[3:2] pins), no LSB is provided. The input range for this mode is shown in Table 20.

ADC overrange (or)

The ADC overrange indicator is asserted when overrange is detected at the ADC input. The overrange condition is determined at the output of the ADC pipeline and, therefore, is affected by a delay of 12 ADC clock cycles. Overrange on the input is indicated within 12 clock cycles after this bit occurs.

Gain switch

The AD9640 includes circuitry suitable for applications with large dynamic range or where gain ranging converters are used. This circuit allows digital thresholds to be set so that upper and lower thresholds can be programmed. Fast detect mode select bits=010 to fast detect mode select bits=101 support various combinations of gain switching options.

One use is to detect when the ADC will reach full scale under certain input conditions. The result is an indicator that can be used to quickly insert the attenuator to prevent the ADC from overdriving.

Coarse Threshold (C_UT)

The coarse upper threshold indicator is asserted if the ADC fast amplitude input level is greater than the level programmed in the coarse upper threshold register (Address 0x105[2:0]). The coarse upper threshold output is output two clock cycles after the input exceeds the level, thus providing a quick indication of the input signal level. A rough upper threshold value is shown in Table 21. This indicator remains asserted for at least two ADC clock cycles, or until the signal falls below the threshold level.

Fine Upper Threshold (F_UT)

The fine upper threshold indicator is asserted if the input volume exceeds the value programmed in the fine upper threshold registers located in Register 0x106 and Register 0x107. Compare the 13-bit threshold register with the signal amplitude at the ADC output. This comparison is affected by the ADC clock delay, but is accurate in terms of converter resolution. The upper fine threshold is defined by the following equation:

Fine Lower Limit (F_LT)

The fine lower threshold indicator is asserted if the input amount is less than the value programmed in the fine lower threshold registers located at Register 0x108 and Register 0x109. The Fine Low Threshold Register is a 13-bit register that is compared to the amplitude of the signal output by the ADC. This comparison is affected by the ADC clock delay, but is accurate in terms of converter resolution. The fine lower threshold size is defined by the following equation:

The operation of the fine upper threshold indicator and the fine lower threshold indicator is shown in Figure 67.

Incremental Gain (IG) and Decrement Gain (DG)

Similarly, corresponding to the finer low threshold bits, except the incremental gain and decremented gain indicators are intended to be used together to provide information to enable external gain control. The Decrement Gain Indicator works with the Coarse Upper Threshold bit and is asserted when the input magnitude is greater than the 3-bit value in the Coarse Upper Threshold register (Address 0x105). Incremental Gain Indicator, which is only asserted when the input amplitude is less than the value programmed in the Fine Lower Threshold Register after the dwell time has elapsed. The dwell time is set by a 16-bit dwell time value located at Address 0x10A and Address 0x10B, and is set in units of 1 to 65535 ADC input clock cycles. The Fine Low Threshold Register is a 13-bit register that is compared to the amplitude of the ADC output. This comparison is affected by the ADC clock delay, but allows for a finer, more precise comparison. The upper fine threshold is defined by the following equation:

The decrement gain output operates from the ADC fast detect output pin, providing a quick indication of a potential overrange condition. Incremental gain uses a comparison at the ADC output, requiring the input amplitude to remain below a precisely programmable level for a predefined period of time before signaling an external circuit to increase the gain.

The operation of increasing and decreasing gain output is shown in Figure 67.

Signal monitor

The Signal Monitor block provides additional information about the signal digitized by the ADC. The signal monitor calculates the rms input amplitude, peak amplitude, and/or the number of samples whose amplitude exceeds a certain threshold. At the same time, these functions can be used to gain insight into signal characteristics and estimate the peak/average ratio of the input signal or even the shape of the complementary cumulative distribution function (CCDF) curve. This information can be used to drive the AGC loop to optimize the range of the ADC in the presence of a real signal.

The signal monitor result value can be obtained from the part by reading the internal register at address 0x116 back to address 0x11B using the SPI port or the signal monitor motion output. The output content of the SPI accessible signal monitor register is set by the two signal monitor mode bits in the signal monitor control register. Both ADC channels must be configured in the same signal monitor mode (Address 0x112). A separate SPI-accessible 20-bit Signal Monitoring Result (SMR) register is provided for each ADC channel. Any combination of signal monitor functions can also be output to the user via the serial motion interface. These outputs are enabled using the Peak Detector Output Enable bit, the rms/ms Amplitude Output Enable bit, and the Threshold Crossover Output Enable bit in the Signal Monitor Motion Control Register.

For each signal monitor measurement, the programmable signal monitor period register (SMPR) controls the duration of the measurement. This time period is programmed as the number of input clock cycles in the 24-bit Signal Monitor Period registers located at Address 0x113, Address 0x114, and Address 0x115. This register is programmable from 128 samples to 16.78 (2 million) samples.

Since the dc offset of a dc can be significantly larger than the signal of interest (affecting the results from the signal monitor), a dc correction circuit is included as part of the signal monitor block to make the dc offset zero before measuring the power .

Peak Detector Mode

The amplitude of the input port signal is monitored for a programmable time period (determined by SMPR) to give the detected peak. This feature is enabled by programming a logic 1 in the Signal Monitor Mode bit in the Signal Monitor Control Register or by setting the Peak Detector Output Enable bit in the Signal Monitor Motion Control Register. Before activating this mode, the 24-bit SMPR must be programmed.

When this mode is enabled, the value in the SMPR is loaded into the watchdog period timer and the countdown begins. The amplitude of the input signal is compared to the value in the internal peak level hold register (not accessible to the user), and the greater of the two is updated as the current peak level. The initial value of the peak hold register is set to the current ADC input signal amplitude. This comparison will continue until the watchdog period timer counts to 1.

When the watchdog period timer reaches count 1, the 13-bit peak level value is transferred to the signal watchdog holding register (not accessible to the user), which can be read through the SPI port or output through the motion serial interface. Reload the watchdog period timer with the value in SMPR and restart the countdown. In addition, the amplitude of the first input sample is updated in the peak level hold register, and the comparison and update process continues as previously described.

Figure 68 is a block diagram of the peak detector logic. The SMR register contains the absolute magnitude of the peak detected by the peak detector logic.

RMS/MS amplitude mode

In this mode, the root mean square (rms) or root mean square (ms) amplitude of the input port signal is integrated (by adding an accumulator) over a programmable time period (determined by the SMPR) to give the rms of the input signal or ms amplitude. This mode is set by programming a logic 0 in the Signal Monitor Mode bit in the Signal Monitor Control Register or by setting the rms/ms Amplitude Output Enable bit in the Signal Monitor Motion Control Register. Before activating this mode, the 24-bit SMPR representing the cycle in which integration is performed must be programmed.

When rms/ms amplitude mode is enabled, the value from SMPR is loaded into the watchdog period timer and the countdown begins immediately. Each input sample is converted to floating point format and squared. It is then converted to 11-bit fixed-point format and added to the contents of the 24-bit accumulator. Integration will continue until the watchdog period timer reaches a count of 1.

When the watchdog period timer reaches a count of 1, the square root of the value in the accumulator is taken and after some formatting transferred to the signal monitor holding register which can be read via the SPI port or via the SPORT serial port output. Reload the watchdog period timer with the value in SMPR and restart the countdown. Additionally, the first input sample signal power is updated in the accumulator, and the accumulator continues with subsequent input samples.

Figure 69 illustrates the RMS monitoring logic.

For RMS magnitude mode, the value in the Signal Monitor Result (SMR) register is a 20-bit fixed-point number. The following formula can be used to determine the rms value in dBFS from the MAG value in the register. Note that the second term in the equation becomes 0 if the Signal Monitoring Period (SMP) is a power of 2.

For ms-magnitude mode, the value in SMR is a 20-bit fixed point number. The following formula can be used to determine the size of ms in dBFS based on the MAG value in the register. Note that if SMP is a power of 2, the second term in the equation becomes 0.

overrun mode

In the threshold crossing mode of operation, the amplitude of the input port signal is monitored for a programmable time period (given by the SMPR) to count the number of times it crosses some programmable threshold. This mode is set by programming a logic 1x (where x is a don't care bit) in the Signal Monitor Mode bit of the Signal Monitor Control Register or by setting the Threshold Crossover Output Enable bit in the Signal Monitor Motion Control Register. Before activating this mode, the user needs to program the 24-bit SMPR and 13-bit high threshold registers for each individual input port. The same high threshold register is used for signal monitoring and gain control (see ADC Overrange and Gain Control section).

Once in this mode, the value from the SMPR is loaded into the watchdog period timer and the countdown begins. At each input clock cycle, the amplitude of the input signal is compared to the upper threshold register (previously programmed). If the amplitude of the input signal is greater than the upper threshold register, the internal count register is incremented by 1.

The initial value of the internal count register is set to 0. This comparison and increment of the internal count register continues until the watchdog period timer reaches a count of one.

When the watchdog period timer reaches a count of 1, the value in the internal count register is transferred to the signal watchdog holding register, which can be read through the SPI port or output through the motion serial port.

The watchdog period timer is reloaded with the value in the SMPR register and restarts the countdown. The internal count register is also cleared to the value 0. Figure 70 illustrates the threshold crossing logic. The value in the SMR register is the number of samples greater than the threshold register.

Additional control bits

To provide additional flexibility in the signal monitoring process, two control bits are provided in the signal monitor control register. They are the signal monitor enable bit and the complex power calculation mode enable bit.

Signal Monitor Enable Bit

The Signal Monitor Enable bit, Register 0x112, Bit 0, enables the operation of the Signal Monitor block. If the signal monitor function is not required in a specific application, this bit should be cleared (default) to save power.

Complex power calculation mode enable bit

When this bit is set, the part assumes that channel A is digitizing the I data and channel B is digitizing the Q data of the complex input signal (or vice versa). In this mode, the reported power is equal to the following values:

If the Signal Monitor Mode bits are set to 00, the result is displayed in the Signal Monitor DC Value Channel A register. The Signal Monitor DC Value Channel B register continues to calculate the Channel B value.

DC correction

Since the dc offset of a dc can be significantly larger than the signal being measured, a dc correction circuit is included to make the dc offset zero before measuring the power. The DC correction circuit can also switch to the main signal path, but this may not be appropriate if the a dc is digitizing a time-varying signal with significant DC content (eg GSM).

DC correction bandwidth

The DC correction circuit is a high-pass filter with a programmable bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 ms/sec). Bandwidth is controlled by writing to Bits[5:2] of the Signal Monitor DC Correction Control Register located at Address 0x10C.

The following formula can be used to calculate the bandwidth value of the DC correction circuit:

where: K is the 4-bit value programmed in Register 0x10C, Bits[5:2] (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13).

fCLK is the ADC sampling rate in Hertz (Hz).

DC Correction Readback

The current DC correction value can be read back to Register 0x10E for Channel A, Register 0x10F for Channel B, and Register 0x110 in Register 0x10D. The DC correction value is a 14-bit value that can span the entire input range of the ADC.

DC Correction Freeze

Setting Bit 6 of Register 0x10C freezes its current state of dc correction and continues to use the last updated value as the dc correction value. Clearing this bit will restart dc correction and add the current calculated value to the data.

DC Correction Enable Bit

Setting Bit 0 of Register 0x10C allows DC correction to be used in signal monitor calculations. The calculated DC correction value can be added to the output data signal path by setting Register 0x10C, Bit 1.

Motion Output Signal Monitor

SPORT is a serial interface with three output pins: SMI SCLK (Motion Clock), SMI SDF (Motion Frame Sync), and SMI SDO (Motion Data Out). Motion is the master, driving all three motion output pins on the chip.

SMI symptom self-rating scale

Data output and frame sync are driven on the positive edge of SMI SCLK. SMI SCLK has three possible baud rates: 1/2, 1/4 or 1/8 ADC clock rate, based on motion control. The SMI SCLK can also be turned off according to the SPORT SMI SCLK sleep bit when no data is being sent. Using this bit to disable the SMI SCLK when the SMI SCLK is not needed can reduce any coupling errors in the return signal path (if these prove to be a problem in the system). However, this has the disadvantage of propagating the frequency content of the clock. If desired, the SMI SCLK can be left running to simplify frequency planning.

SMI SDF

SMI SDFS is Serial Data Frame Sync, which defines the start of a frame. A motion frame contains data paths from two motion frames. Data in datapath A is sent after frame synchronization, followed by data in datapath B.

SMI SDO

SMI SDO is the serial data output of the block. Data is sent MSB first on the next positive edge after SMI SDFS. Each data output block includes one or more rms/ms amplitude, peak level, and threshold crossing values (in the specified order) from each data path. If enabled, data is sent, first rms, then peak and threshold, as shown in Figure 71.

Built-in Self-Test (BIST) and Output Test

The AD9640 includes built-in test functions that verify the integrity of each channel and facilitate board-level debugging. A built-in self-test (BIST) function is included to verify the integrity of the AD9640's digital datapath. Various output test options are also provided to place predictable values on the outputs of the AD9640.

Built-in Self-Test (BIST)

The built-in self-test is for selected AD9640 signal paths. When enabled, the test runs from the internal PN source through the digital datapath starting from the ADC block output. The BIST sequence runs for 512 cycles and stops. The BIST signature value for Channel A or Channel B is placed in Register 0x024 and Register 0x025. If a channel is selected, its BIST signature will be written to both registers. If both channels are selected, the result from the A channel will be placed into the BIST signature register.

During the test, the output is not disconnected, so the PN sequence can be observed at runtime. The PN sequence can continue from its last value or start from the beginning, based on the value programmed in Register 0x00E, Bit 2. BIST signature results vary by channel configuration.

output test mode

The output test options are shown in Table 25. When the output test mode is enabled, the analog portion of the ADC is disconnected from the digital backend block, and the test mode runs through the output formatting block. Some test patterns are bound by the output format, and some are not bound by the output format. The seed value for the PN sequence test can be forced if the PN reset bit is used to hold the generator in reset mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encoded clock. For more information, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

Channel/Chip Synchronization

The AD9640 has a synchronization input that allows the user flexible synchronization options to synchronize internal blocks. The clock divider synchronization feature helps ensure synchronized sampling clocks between multiple ADCs. The Signal Monitor block can also be synchronized using a sync input, which allows the characteristics of the input signal to be measured over a specific period of time. The input clock divider can synchronize at one occurrence or every occurrence of the synchronization signal. The signal monitor block synchronizes on each sync input signal.

The sync input is internally synchronized to the sampling clock; however, to ensure that there is no timing uncertainty between multiple sections, the sync input signal should be externally synchronized to the input clock signal to meet the setup and hold times shown in Table 8. The sync input should be driven with a single-ended CMOS type signal.

Serial Port Interface (SPI)

The AD9640 serial port interface (SPI) allows the user to configure the converter for a specific function or operation through the structured register space provided within the ADC. This adds flexibility and customization to the user depending on the application. The address is accessed through the serial port and can be written or read through the port. Memory is organized into bytes, which can be further divided into fields, which are recorded in the memory-mapped section. For detailed operational information, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

Configuration using SPI

There are three pins that define the SPI of this ADC. These are the SCLK/DFS pins, SDIO/DCS pins, and CSB pins (see Table 22). SCLK/DFS (serial clock) is used to synchronize the read and write data of the ADC. SDIO/DCS (Serial Data Input/Output) is a dual purpose pin that allows data to be sent and read from the internal ADC memory mapped registers. CSB (chip select bar) is an active low control that enables or disables read and write cycles.

The falling edge of CSB and the rising edge of SCLK together determine the start of the frame. Examples of sequence timings and their definitions can be found in Figure 73 and Table 8.

Other modes involving CSB are also available. CSB can be held low indefinitely, which will permanently enable the device; this is called streaming. CSB may hang high between bytes to allow for additional external timing. When CSB is tied high, the SPI function is put into high impedance mode. This mode enables any SPI pin auxiliary functions.

In the command phase, a 16-bit command is sent. The data follows the instruction phase and its length is determined by the W0 and W1 bits. All data consists of 8-bit words. The first bit of the first byte in a multibyte serial data transfer frame indicates whether to issue a read or write command. This allows the serial data input/output (SDIO) pins to change the input direction to the output direction.

In addition to word length, the instruction stage determines whether the serial frame is a read or write operation, allowing the serial port to be used to program the chip and read the contents of on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pins to change from input to output at the appropriate point in the serial frame.

Data can be sent in MSB first mode or LSB first mode. MSB first is the default value at power-on and can be changed through configuration registers. For more information on this and other features, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

hardware interface

The pins described in Table 22 comprise the physical interface between the user programming device and the AD9640 serial port. When using the SPI interface, the SCLK pin and the CSB pin are used as inputs. The SDIO pins are bidirectional and act as inputs during the write phase and as outputs during readback.

The SPI interface is flexible enough to be controlled by FPGAs or microcontrollers. An SPI configuration method is described in detail in the AN-812 application note, based on the serial port interface startup circuit of the microcontroller.

The SPI port should not be active during periods when full dynamic performance of the converter is required. Since the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise on these signals can degrade converter performance. If the onboard SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9640 to prevent these signals from transitioning at the converter inputs during critical sampling.

Some pins have dual functions when the SPI interface is not used. When pins are tied to AVDD or ground during device power-up, they are associated with specific functions. The Digital Outputs section describes the bundleable functions supported by the AD9640.

Configuration without SPI

In applications that do not interface with the SPI control registers, the SDIO/DCS pins, SCLK/DFS pins, SMI SDO/OEB pins, and SMI SCLK/PDWN pins serve as independent CMOScompatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for duty cycle stabilizer, output data format, output enable, and power-down feature control. In this mode, the CSB chip select should be tied to AVDD, which will disable the serial port interface.

SPI accessible functions

The following is a brief description of the general features accessible through the SPI. These features are described in detail in the AN-877 application note, which interfaces to high-speed ADCs via SPI.

memory map

read memory map

Each row in the memory-mapped table has eight bit positions. The memory map is roughly divided into four parts: chip configuration and ID register map (address 0x00 to address 0x02); ADC setup, control and test (address 0x08 to address 0x25); channel index and transfer register map (address 0x05 to address 0xFF) ;Digital Characteristic Control (Address 0x100 to Address 0x11B).

Starting from the right column, the memory-mapped register records in Table 25 record the default hex value for each hex address shown. Columns with header bit 7 (MSB) are the start of the given default hex value. For example, address 0x18, VREF select, has a hexadecimal default value of 0xC0. This means that bit 7=1, bit 6=1, and the remaining bits are 0. This setting is the default reference selection setting. The default value uses a 2.0 V peak reference. For more information on this and other features, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI. This document details Register 0x00 to Register 0xFF. The remaining registers, from Register 0x100 to Register 0x11B, are documented in the Memory Mapped Register Description section.

open location

All addresses and bit positions not included in Table 25 are not currently supported by this device. Unused bits in valid address locations should be written with 0. These locations only need to be written if part of the address location is open (for example, address 0x18). If the entire address location is open (for example, address 0x13), this address location should not be written.

Defaults

From reset, key registers are loaded with default values. The default values of the registers are given in Table 25 of Memory Mapped Registers.

logic level

Logic level terms are explained as follows:

(1), "Bit is set" is synonymous with "Bit is set to Logic 1", or "A logic 1 is being programmed for a bit."

(2) "Clear a bit" is synonymous with "bit is set to Logic 0", or "A logic 0 is being written to the bit."

transfer register map

Address 0x08 to address 0x18 are hidden. Writing to these addresses does not affect part of the operation until a transfer command is issued by writing 0x01 to address 0xFF and setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. Internal updates occur when the transfer bit is set and the bit is automatically cleared.

channel-specific registers

Certain channel setup functions, such as signal monitor thresholds, can be programmed differently for each channel. In these cases, the channel address location is repeated inside each channel. These registers are designated as local registers in the parameter name column of Table 25. These local registers can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, subsequent writes affect the registers of both channels. During a read cycle, only channel A or channel B should be set to read one of the two registers. The part returns the value of channel A if both bits are set during the SPI read cycle. Registers designated as global in the parameter name column of Table 25 affect the entire component or channel characteristics, where independent settings between channels are not allowed. The settings in Register 0x05 do not affect the global registers.

Memory Mapped Register Description

For more information on the functions of Register 0x00 controls to Register 0xFF, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

Synchronization Control (Register 0x100)

Bit 7 - Signal Monitor Sync Enable

Bit 7 enables the sync pulse from the external sync input to the Signal Monitor block. When bit 7 is high and bit 0 is high, the sync signal is passed. This is continuous sync mode.

Bits[6:3] - reserved

Bit 2 clock divider, next sync only

If the sync enable bit (Address 0x100[0]) is high and the clock divider sync enable (Address 0x100[1]) is high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and ignore the rest. Address 0x100[1] is reset after synchronization.

Bit 1 Clock Splitter Sync Enable

Bit 1 gates the sync pulse to the clock divider. When bit 1 is high and bit 0 is high, the sync signal is passed. This is continuous sync mode.

Bit 0 Master Sync Enable

Bit 0 must be high to enable any synchronization functions.

Fast Detect Control (Register 0x104) Bits[7:4] - Reserved

Bits[3:1] - fast detection mode selection

These bits set the mode of the fast detect output bits according to Table 17.

Bit 0 - Fast Detection Enable

Bit 0 is used to enable the fast detect bit. When the fast detect output is disabled, the output goes into a high impedance state. In LVDS mode, when the outputs are interleaved, the outputs will only go to high-Z when both channels are off (power down/standby/output disabled). If only one channel is turned off (power down/standby/output disabled), the fast detect output will repeatedly activate the channel's data.

Fine Upper Threshold (Register 0x106 and Register 0x107)

Register 0x106, Bits[7:0] - Fine Upper Threshold[7:0]

Register 0x107, Bits[7:5] - Reserved

Register 0x107, Bits[4:0] - Fine Upper Threshold[12:8]

These registers provide fine-grained upper thresholds. This 13-bit value is compared to the 13-bit amplitude from the ADC block, and if the ADC amplitude exceeds this threshold, the F_UT flag is set.

Fine Lower Threshold (Register 0x108 and Register 0x109)

Register 0x108, Bits[7:0] - Fine Lower Threshold[7:0]

Register 0x109, Bits[7:5] - Reserved

Register 0x109, Bits[4:0] - Fine Lower Threshold[12:8]

These registers provide a good lower threshold. This 13-bit value is compared to the 13-bit amplitude from the ADC block, and if the ADC amplitude is less than this threshold, the F_LT flag is set.

Signal Monitor DC Correction Control (Register 0x10C)

Bit 7—Reserved

Bit 6 - DC Correction Freeze

When bit 6 is set high, the dc correction is no longer updated to the signal monitor block. It holds the last dc value it calculated.

Bits[5:2] - DC Correction Bandwidth

These bits set the averaging time for the DC correction function of the signal monitor. It is a 4-bit word that sets the bandwidth of the correction block.

Bit 1—DC Correction for Signal Path Enable

Setting bit 1 high will add the output of the dc measurement block to the data in the signal path to remove the dc offset from the signal path.

Bit 0-DC correction for SM enable

Bit 0 enables the DC correction function in the signal monitoring block. DC correction is an averaging function that a signal monitor can use to remove DC offsets in a signal. Removing this direct current from the measurement results in a more accurate reading.

Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E)

Register 0x10D, Bits[7:0] - Channel A DC Value[7:0]

Register 0x10E, Bits[7:0] - Channel A DC Value[13:8]

These read-only registers hold the latest dc offset value calculated by the channel A's signal monitor.

Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110)

Register 0x10F Bits[7:0] - Channel B DC Value[7:0]

Register 0x110, Bits[7:0] - Channel B DC Value[13:8]

These read-only registers hold the latest dc offset value calculated by the channel B's signal monitor.

Signal Monitor Motion Control (Register 0x111) Bit 7 - Reserved

Bit 6 - RMS/MS amplitude output enable

These bits make 20-bit rms or ms measurements into motion outputs.

Bit 5 Peak Power Output Enable

Bit 5 makes the 13-bit peak measurement an output on motion.

Bit 4 - Threshold Crossover Output Enable

Bit 4 enables the 13-bit threshold measurement as an output on motion.

Bits[3:2] - Motion SMI SCLK division

The value of these bits sets the division ratio of the motion SMI SCLK to the input clock. The value 0x01 set is divided by 2 (the default), the value 0x10 set is divided by 4, and the value 0x11 set is divided by 8.

Bit 1 - Motion SMI SCLK Sleep

Setting bit 1 high will cause the SMI SCLK to remain low when the signal monitor block has no data to transfer.

Bit 0 - Signal Monitor Motion Output Enable

When set, bit 0 causes the signal monitor's motion output to begin shifting the resulting data out of the signal monitor block.

Signal Monitor Control (Register 0x112)

Bit 7 - Complex Power Calculation Mode Enable

This mode assumes that I data appears on one channel and Q data appears on the other. The reported result is the composite power, measured as:

Bits[6:4] - reserved

Bit 3 Signal Monitor RMS/MS Select

Setting Bit 3 low selects the rms power measurement mode. Set bit 3 high to select ms power measurement mode.

Bits[2:1] - Signal Monitor Mode

Bits 2 and 1 set the mode of the data output signal monitor to Register 0x116 to Register 0x11B. Set bits 2 and 1 to 0x00 to select the rms/ms power output; set these bits to 0x01 to select the peak power output; set 0x10 or 0x11 to the threshold crossing output.

Bit 0 - Signal Monitor Enable

Setting bit 0 high enables the signal monitor block.

Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits[7:0] - Signal Monitor Period[7:0]

Register 0x114, Bits[7:0] - Signal Monitor Period[15:8]

Register 0x115, Bits[7:0] - Signal Monitor Period[23:16]

This 24-bit value sets the number of clock cycles for the signal monitor to perform its operation. Although this register defaults to 64 (0x40), this register has a minimum value of 128 (0x80) cycles - writing a value less than 128 may result in inaccurate results.

Signal Monitor Results Channel A (Register 0x116 to Register 0x118)

Register 0x116, Bits[7:0] - Signal Monitor Result Channel A[7:0]

Register 0x117, Bits[7:0] - Signal Monitor Result

Channel A[15:8]

Register 0x118, Bits[7:4] - Reserved

Register 0x118, Bits[3:0] - Signal Monitor Result

Channel A[19:16]

This 20-bit value contains the result calculated by the Signal Monitor block for Channel A. The content depends on Settings[2:1] in Register 0x112.

Signal Monitor Result Channel B (Register 0x119 to Register 0x11B)

Register 0x119, Bits[7:0] - Signal Monitor Result Channel B[7:0]

Register 0x11A, Bits[7:0] - Signal Monitor Results

Channel B[15:8]

Register 0x11B, Bits[7:4] - Reserved

Register 0x11B, Bits[3:0] - Signal Monitor Results

Channel B[19:16]

This 20-bit value contains the result computed by Channel B's Signal Monitor block. The content depends on Settings[2:1] in Register 0x112.

application information

Design Guidelines

Before beginning the design and layout of the AD9640 as a system, designers are advised to familiarize themselves with these guidelines, which discuss the special circuit connections and layout requirements required for specific pins.

Power and Grounding Recommendations

When connecting power supplies to the AD9640, it is recommended to use two separate 1.8V supplies: one supply for the analog (AVDD) and digital (DVD), and one supply for the digital output (DRVDD). AVDD and DVDD power supplies, although from the same source, should be isolated using ferrite beads or filter chokes and separate decoupling capacitors. Users can use several different decoupling capacitors to cover high and low frequencies. These should be located close to the PC board level entry point and close to the part pins with the smallest trace length.

When using the AD9640, a single PCB ground plane should be sufficient. Optimum performance is easily achieved with proper decoupling and intelligent partitioning of the analog, digital and clock sections of the PCB.

LVDS operation

The AD9640 defaults to CMOS output mode at power-up. If LVDS operation is required, this mode must be programmed using the SPI configuration registers after power-up. When the AD9640 is powered up in CMOS mode with LVDS termination resistors (100Ω) on the output, the DRVDD current may be higher than typical until the part is placed in LVDS mode. This additional DRVDD current will not cause damage to the AD9640, but it should be taken into account when considering the maximum DRVDD current for this part.

To avoid this additional DRVDD current, the AD9640 output can be disabled at power-up by setting the OEB pin high. After placing the part in LVDS mode via the SPI port, the OEB pin can be brought low to enable the output.

Exposed Blade Hot Slug Recommendations

For best electrical and thermal performance, the exposed paddle on the bottom of the ADC must be connected to analog ground (AGND). A continuous, exposed (no solder mask) copper plane on the PCB should match the exposed paddle (pin 0) of the AD9640.

The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation through the bottom of the PCB. These vias should be filled or plugged with non-conductive epoxy.

To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen overlay should be applied to divide the continuous plane on the PCB into several uniform sections. This provides two connection points during reflow. Using a continuous plane with no partitions ensures that there is only one connection point between the ADC and the PCB. See the evaluation board for an example PCB layout. For more information on packaging and PCB layout for chip scale packages, see AN-772 Application Note, Design and Manufacturing Guidelines for Lead Frame Chip Scale Packages (LFCSP).

CML

The CML pin should be separated from ground using a 0.1µF capacitor, as shown in Figure 47.

RBIAS

The AD9640 requires a 10 kΩ resistor from the RBIAS pin to ground. This resistor sets the primary current reference for the ADC core and should have a tolerance of at least 1%.

Reference decoupling

The VREF pin should be externally decoupled to ground in parallel with a low ESR 1.0µF capacitor and a 0.1µF ceramic low ESR capacitor.

SPI port

The SPI port should not be active during periods when full dynamic performance of the converter is required. Since the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise on these signals can degrade converter performance. If the onboard SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9640 to prevent these signals from transitioning at the converter inputs during critical sampling.

Dimensions