feature

Single Supply +3.3V; High SNR: 70.7dBFS, fIN=5MHz; Total Power Consumption: Internal Reference: 321mW; External Reference: 285mW; Internal or External Reference; ±Low DNL: 0.3LSB; Flexible Input Range: 1.5 VPP to 2VPP; TQFP-64 package.

application

Communication intermediate frequency processing; communication base station; test equipment; medical imaging; video digitization; CCD digitization.

illustrate

The ADS5231 is a dual high speed high dynamic range 12-bit pipeline analog-to-digital converter (ADC). The converter includes a high bandwidth track-and-hold amplifier with excellent spurious performance up to or exceeding the Nyquist rate. The differential nature of the track-and-hold amplifier and ADC circuit minimizes even-order harmonics and provides excellent common-mode noise immunity.

The ADS5231 provides the ability to set the full-scale range of the converter without any external reference circuitry. The internal reference can be disabled, allowing the use of a low-drive, external reference to improve tracking in multi-channel systems.

The ADS5231 provides an out-of-range indicator to indicate an input signal that is outside the full-scale input range of the converter. This flag can be used to reduce the gain of the front-end gain control circuit. There is also an output enable pin for multiplexing and testing on a printed circuit board (PCB).

The ADS5231 uses digital error correction to provide excellent differential linearity for demanding imaging applications. The ADS5231 is available in the TQFP-64 software package.

canonical definition

analog bandwidth

Simulate the input frequency at which the spectral power of the fundamental frequency (determined by FFT analysis) is reduced by 3dB.

Aperture delay

Enter the time delay between the rising edge of the sample clock and the actual time the sampling occurs.

Aperture uncertainty (jitter)

Sample-to-sample variation of aperture delay.

clock duty cycle

Pulse width high is the minimum amount of time that an ADCLK pulse remains in a logic "1" state to achieve rated performance. Pulse width low is the minimum time that an ADCLK pulse should remain low (logic "0"). These specifications define acceptable clock duty cycles for a given clock rate.

Differential Nonlinearity (DNL)

An ideal ADC shows code transitions that are exactly 1 LSB apart. DNL is the deviation of any single LSB transition at the digital output from the analog input processing in 1lsb steps. If the device claims to have no missing codes, it means that all possible codes ( 4096 codes for a 12-bit converter) are present over the entire working range.

Effective Number of Bits (ENOB)

ENOB is a measure of converter performance compared to theoretical limits based on quantization noise.

Integral Nonlinearity (INL)

INL is the deviation of the transfer function from a reference line measured in fractions of 1 lsb using the best straight line or best fit determined by least squares curve fit. INL is independent of the effects of offset, gain or quantization errors.

maximum conversion rate

The encoding rate of the parametric test is performed. This is the maximum sample rate. Provides authentication operations.

Minimum conversion rate

This is the minimum sample rate at which the ADC will still work.

Signal to Noise and Distortion (SINAD)

SINAD is the ratio of the fundamental power (PS) to the power (but not dc) of all other spectral components including noise (PN) and distortion (PD).

When the absolute power of the fundamental is used as a reference, SINAD is given in dBc (dB to carrier); when the power of the fundamental is extrapolated to the full-scale range of the converter, SINAD is given in dBFS (dB to full-scale) ) is given in units.

signal to noise ratio

SNR is the ratio of fundamental power (PS) to noise floor power (PN), excluding DC power and the first eight harmonics.

When the absolute power of the fundamental is used as a reference, the signal-to-noise ratio is given in dBc (decibels to carrier); when the power of the fundamental is extrapolated to the full-scale range of the converter, the signal-to-noise ratio is given in dBFS (decibels). for full scale) are given in units.

Spurious free dynamic range

The ratio of fundamental power to the other highest spectral components (spurious or harmonics). SFDR is usually given in dBc (dB to carrier).

Two-tone third-order intermodulation distortion

Two-tone IMD3 is the ratio of the power of the fundamental frequency (at frequencies f1 and f2) to the power of the worst spectral component of third-order intermodulation distortion at frequencies 2f1-f2 or 2f2-f1. IMD3 is given in dBc (dB to carrier), when the absolute power of the fundamental is used as a reference, IMD3 is given in dBc; when the power of the fundamental is extrapolated to the full-scale range of the converter, IMD3 is given in dBFS (dB to full scale) is given in units.

The encoding rate when performing the parametric test. This is the maximum sample rate for a given operation.

Typical features

TMIN=-40°C, TMAX=+85°C. Typical values are TA=+25°C, clock frequency=40MSPS, 50% clock duty cycle, AVDD=3.3V, VDRV=3.3V, transformer coupled input, -1dBFS, ISET=56.2kΩ, internal voltage reference, unless otherwise There are instructions.

application information

theory of operation

The ADS5231 is a dual-channel, simultaneous sampling analog-to-digital converter (ADC). Its low power consumption and high sampling rate of 40MSPS are implemented in an advanced low-voltage CMOS process using a state-of-the-art switched capacitor pipeline structure. The ADS5231 operates from a +3.3V supply voltage from the analog and digital supply connections. The ADC core for each channel consists of multi-bit and single-unit internal pipeline stages. Each stage feeds its data into digital error correction logic, ensuring excellent differential linearity and no missing codes at the 12-bit level. The conversion process is initiated by the rising edge of the external clock. Once the signal is captured by the input sample-and-hold amplifier, the input samples are sequentially converted within the pipeline stage. This process results in a data delay of six clock cycles, after which the output data is available as a 12-bit parallel word, encoded in direct offset binary (SOB) or two's complement (BTC) format. Because a common clock controls the timing of both channels, the analog signals are sampled simultaneously. The data on the parallel port is also updated at the same time. Further processing can be timed using a single data valid output signal per channel. The ADS5231 features an internal reference trimmed to ensure a high level of accuracy and matching. Internal references can be disabled to allow external reference operations.

input configuration

The analog input of the ADS5231 consists of a differential sample-and-hold structure implemented using switched capacitor techniques; see Figure 18. The sampling circuit consists of a low-pass RC filter at the input to filter out noise components that may be differentially coupled at the input. The input is sampled on two 4pF capacitors. The RLC model is shown in Figure 18.

Enter driver configuration

Transformer coupled interface

If the application requires signal conversion from a single-ended source to drive the ADS5231 differentially, an RF transformer can be a good solution. The selected transformer must have a center tap to apply the common-mode DC voltage (VCMV) required to bias the converter input. The AC ground center tap will create a differential signal swing on the secondary winding. Consider a step-up transformer that utilizes signal amplification without introducing other sources of noise. Additionally, reduced signal swing from the source may lead to improved distortion performance. The differential input configuration offers significant advantages in achieving good SFDR performance over a wide input frequency range. In this mode, matched impedances are seen at the inputs of the ADS5231 (both input and input).

Figure 19 shows a schematic diagram of the proposed transformer-coupled interface circuit. The component values of the RC low-pass filter can be optimized according to the desired roll frequency.

DC-coupled input with difference amplifier

Applications that require a DC-coupled differential amplifier, such as the THS4503, can be used to drive the ADS5231; this design is shown in Figure 20. The THS4503 amplifier is easily single-ended to differential conversion to reduce component cost.

Additionally, the VOCM pin on the THS4503 can be connected directly to the common-mode pin (CM) of the ADS5231 to set the necessary bias voltage for the converter input. In the circuit example shown in Figure 20, the THS4503 is configured for unity gain. Higher gains can be easily achieved if desired by adding a small capacitor (like 10pF) in parallel with the feedback resistor to create a low pass filter. Since the THS4503 drives a capacitive load, a small series resistance at the output ensures stable operation. More details on this and the overall operation of the THS4503 can be found in its product data sheet. In general, differential amplifiers provide a high-performance driver solution for baseband applications, and other differential amplifier models can be selected based on system requirements.

Input overvoltage recovery

The differential full-scale input range supported by the ADS5231 is 2VPP. Input and input can swing from 1V to 2V for a nominal value of VCM (+1.5V). The ADS5231 is specifically designed to handle an overvoltage differential peak voltage of 4V (2.5V and 0.5V swing in and out). If the input common-mode voltage does not differ much from VCM during an overload (less than 300 mV), the time to recover from an overvoltage input condition is expected to be within three clock cycles. All amplifiers in the sample-and-hold stage and ADC core are specifically designed for excellent recovery from overloaded signals.

Reference circuit

internal reference

All bias currents required for proper operation of the ADS5231 are set using an external resistor at ISET (Pin 60), as shown in Figure 21. Use a 56.2kΩ resistor across ISET to generate an internal reference current of about 20µA. This current is mirrored internally to generate the bias current for the internal block. When a 5% resistance tolerance is sufficient, deviations from this resistance value can change and degrade device performance. For example, using a larger external resistor at ISET can reduce the reference bias current and thus reduce the operating power of the device.

As part of the internal reference circuit, the ADS5231 provides a common-mode voltage output at pin 52, CM. This common mode voltage is typically +1.5V. While this is similar to the common-mode voltage used inside the ADC pipeline core, the CM pin has a separate buffer amplifier that can deliver up to ±2mA to external circuitry for proper input signal level offset and bias . For best dynamic performance, the analog inputs should be biased towards the recommended common-mode voltage (1.5V). While good performance can be maintained within a certain CM range, larger deviations may impair device performance and may also negatively affect overload recovery behavior. Using the internal reference mode requires forcing the INT/EXT pin high, as shown in Figure 21.

The ADS5231 requires solid state high frequency bypassing on the reference pins REFT and REFB; see Figure 21. Use ceramic 0.1µF capacitors (size 0603 or smaller) as close to the pins as possible.

xref

The ADS5231 also supports the use of an external voltage reference. The external reference voltage mode consists of applying the external top reference voltage at REFT (Pin 53) and the bottom reference voltage at REFB (Pin 54). Setting the ADS5231 to external reference mode also requires setting the INT/EXT pin low. In this mode, the internal reference buffer is tri-stated. Since the switching currents for both ADC channels come from the external forced reference, the device performance may be slightly lower than when using the internal reference. It should be noted that in external reference mode, VCM and ISET continue to be generated by the internal bandgap voltage as they are in internal reference mode. Therefore, it is important to ensure that the common-mode voltage of the external forced reference voltage matches within 50mV (+1.5VDC) of VCM.

The external reference circuit must be designed to drive the internal reference impedance between the REFT and REFB pins. To determine the drive requirements, consider that the external reference circuit needs to provide at least 1 mA of average switching current. This dynamic switching current depends on the actual device sampling rate and signal level. The external reference voltage can vary as long as the external upper reference voltage value remains within the range of +1.875V to +2.0V and the external lower reference voltage remains within the range of +1.0V to +1.125V. Therefore, the full-scale input range can be set between 1.5VPP and 2VPP (FSR=2x[REFT–REFB]).

clock input

Maintain a good signal-to-noise ratio. This condition is especially important in IF sampling applications; for example, the sampling frequency is lower than the input frequency (undersampling). The following formula can be used to calculate the achievable signal-to-noise ratio for a given input frequency and clock jitter (tJA, psRMS):

If the sampling clock rate falls below the limit of about 2MSPS, the ADS523 will enter power-down mode. If the sample rate is above this threshold, the ADS5231 will automatically resume normal operation.

Phase Locked Loop Control

The ADS5231 has an internal PLL enabled by default. Phase-locked loops achieve a wide range of clock duty cycles. Good performance is obtained at duty cycles as high as 40%-60%, although the guaranteed electrical specifications assume a duty cycle between 45%-55%. The phase locked loop automatically limits the minimum operating frequency to 20MSPS. For operation below 20MSPS, the PLL can be disabled by programming the internal registers through the serial interface. With the PLL disabled, the clock speed can be reduced to 2MSPS. With the PLL disabled, the clock duty cycle needs to be limited to close to 50%.

output information

The ADS5231 provides two channels with 12 data outputs (D11 to D0, where D11 is the MSB and D0 is the LSB), data valid outputs (DVA, DVB, pin 26, and pin 22, respectively), and a separate overrange indicator Output pins (OVRA/OVRB, Pin 39 and Pin 9 respectively).

The output circuitry of the ADS5231 is designed to minimize noise caused by transients in data exchange, especially its coupling to the ADC analog circuitry.

Data Output Format (MSBI)

The ADS5231 offers two data output formats: straight offset binary (SOB) or two's complement (BTC). Selection of the output encoding is controlled by MSBI (pin 41). Since the MSBI pin has an internal pull-down menu, the ADS5231 will use the SOB code as the default setting. Forcing the MSBI pin high will enable BTC encoding. The two code structures are identical except that the MSB is reversed to BTC format; as shown in Table 1.

Output Enable (OE)

The digital outputs of the ADS5231 can be set to high impedance (tri-stated), implementing the output enable pins, OEA (pin 42), and OEB (pin 6). An internal drop-down menu configures the output to enable mode for proper operation. Applying a logic high voltage disables the output. Note that the OE function is not designed to operate dynamically (i.e. as a fast multiplexer) as it can lead to corrupt conversion results. Refer to the Electrical Characteristics table and observe the specified tri-state enable and disable times.

Over Range Indicator (OVR)

scope. Will go high if the applied signal exceeds the full scale range. It should be noted that each OVR output is updated with the data output corresponding to the particular sampled analog input voltage. Therefore, the OVR state is subject to the same pipeline delay (six clock cycles) as the digital data.

output load

It is recommended that the capacitive loading on the data output lines be as low as possible, preferably less than 15pF. Higher capacitive loads will result in higher dynamic currents as the digital output changes. This high current surge can feed back into the analog portion of the ADS5231 and adversely affect device performance. If necessary, use external buffers or latches close to the converter output pins to minimize capacitive loading.

serial interface

The ADS5231 has a serial interface that can be used to program the internal registers. If SEL is tied to 0, the serial interface is disabled.

The SEL functions as a reset signal when the serial interface is enabled. After the power supply stabilizes, it is necessary to give the device a low pulse on the SEL. This will cause all internal registers to reset to their default values of 0 (inactive). If not reset, the registers may be in a non-default state at power-up. This condition may cause equipment failure.

Power down mode

The ADS5231 has a power-down pin, STPD (pin 45). During normal operation, the device's internal pulldown is in default mode. Forcing the STPD pin high will cause the device to go into power-down mode. In power-down mode, the reference and clock circuits and all channels are powered down. Device power consumption drops below 90 megawatts. As previously mentioned, the ADS5231 also goes into power-down mode if the clock speed falls below 2MSPS (see the Clock Input section).

When STPD is pulled high, the internal buffers driving REFT and REFB are tri-stated and the outputs are forced to a voltage approximately equal to half the voltage on AVDD. The speed of recovery from power-down mode depends on the external capacitor values on the REFT and REFB pins.

For capacitors less than 1µF on REFT and REFB, the reference voltage settles to within 1% of its steady-state value in less than 500µs. When enabled, either of the two channels can also be selectively powered down through the serial interface.

The ADS5231 also has an internal circuit that monitors the status of the stopped clock. If ADCLK is stopped for more than 250ns, or if it is running at less than 2MHz, this monitoring circuit generates a logic signal that places the device in a partially powered-down state. As a result, the power consumption of the device is reduced when the CLK is stopped. Recovery from such a partial power outage takes about 100 μs. This limitation is described in Table 2.

Layout and Decoupling

Precautions

Proper grounding and bypassing, short lead lengths, and use of ground planes are especially important for high-frequency designs. Achieving optimum performance with fast sampling converters such as the ADS5231 requires careful attention to printed circuit board (PCB) layout to minimize the effects of board parasitics and optimize component placement. Often multi-layer boards ensure the best results and allow for easy component placement.

The ADS5231 should be considered an analog component and the power pins should be connected to a clean analog power supply. This layout ensures the most consistent performance results, as digital power supplies often carry high levels of switching noise, which can couple into converters and degrade device performance. As mentioned earlier, the output buffer supply pin (VDRV) should also be connected to a low noise supply. Power supplies to adjacent digital circuits may carry significant current transients. The supply voltage should be filtered before connecting to the VDRV pin of the converter. All ground pins should be connected directly to analog ground.

The high-frequency current transients and noise (clock feedthrough) generated by the ADS5231 due to its high sampling frequency are fed back to the power and reference lines. If not bypassed enough, this feedthrough adds to the noise transition process. All AVDD pins may bypass 0.1µF ceramic chip capacitors (size 0603 or smaller). A similar approach can also be used on the output buffer supply pins. To minimize lead and trace inductance capacitors should be placed as close as possible to the power supply pins. If double-sided assembly is allowed, it is best to place it directly under the package. Additionally, larger bipolar decoupling capacitors (2.2µF to 10µF) that are effective at lower frequencies can also be used on the main supply pins. They can be placed on the PCB near the ADC (<0.5).

If the analog inputs of the ADS5231 are driven differently, optimize toward a highly symmetrical layout. Small track length differences can introduce phase shifts that can affect good distortion performance. Therefore, using two single op amps instead of one dual amplifier allows for a more symmetrical layout and better parasitic capacitance matching. The pin orientation of the ADS5231 quad flat pack is a pass-through design, with the analog inputs on one side of the package and the digital outputs on the other side of the package. This design provides good physical isolation between analog and digital connections. When designing the layout, it is important to separate the analog signal traces from any digital lines to prevent noise coupling into the analog section. Single-ended clock lines must be short and should not cross any other signal lines.

Short circuit traces on the digital outputs will minimize capacitive loading. The trace length should be immediately adjacent to the receive gate (<2"), with only one CMOS gate connected to one digital output.