illustrate

The HCPL-314J series devices consist of AlGaAs LEDs optically coupled to an integrated circuit with a power output stage. These optocouplers are ideal for driving power igbt and mosfet applications for motor control inverters. The operating voltage range of the high output stage provides the drive voltage required for gated devices. The voltage and current provided by this optocoupler make it ideal for directly driving small or medium power IGBTs. For IGBTs with higher ratings HCPL-3150 (0.5A) or HCPL-3120 (2.0A) optocouplers can be used.

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feature

0.4 A minimum peak output current

High-speed response: Propagation delay of up to 0.7 microseconds over temperature. scope

Ultra-high CMR: minimum 25kv/microsecond when VCM=1.5kV

Bootstrap Supply Current: 3mA max

wide operating temperature. Range: -40°C to 100°C

Wide VCC operating range: 10 V to 30 V over temperature.

scope

Available in DIP8 (single) and SO16 (dual) packages

Safety Approvals: UL Recognized, 5000 Vrms for 1 minute. CSA approved. IEC/EN/DIN EN 60747-5-5 certified VIORM=1414 Vpeak

application

Isolated IGBT/Power MOSFET gate drive

AC and Brushless DC Motor Drivers

Inverter for electrical appliances

Industrial inverter

Switching Power Supplies (SMPS)

Uninterruptible Power Supply (UPS)

Packaging Features

For each channel unless otherwise specified

notes:

1. Linearly reduce the free air temperature above 70°C at a rate of 0.3 mA/°C.

2. Maximum pulse width = 10 s, maximum duty cycle = 0.2%. This value is intended to account for component tolerance peak min = 0.4 A for designs with IO. See the application section for more details on limiting IOL peaks.

3. Linear derating above 85°C, free air temperature is 4.0 mW/°C.

4. Input power consumption does not require derating.

5. Maximum pulse width = 50 s, maximum duty cycle = 0.5%.

6. In this test, VOH is measured with DC load current. When driving capacitive loads, VOH will approach VCC as IOH approaches zero amps.

7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.

8. According to UL 1577, each HCPL-314J optocoupler is verified by applying insulation test voltage ≥6000 Vrms for 1 second. If applicable, this test is performed before the partial discharge 100% production test (Method B) shown in the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics table.

9. The device is considered a two-terminal device: the pins on the inputs are shorted together and the pins on the output are shorted together.

10. PDD refers to the difference between tPHL and tPLH between any two components or channels under the same experimental conditions.

11. Pins 3 and 4 (HCPL-314J) need to be connected to the LED common.

12. The common mode transient immunity in the common mode pulsed VCM is the maximum tolerable dVCM/dt of the common mode pulsed VCM to guarantee that the output will remain high (ie Vo>6.0V).

13. Low-state common-mode transient immunity is the maximum withstand DVCM/dt of the common-mode pulsed VCM to guarantee that the output will remain in a low state (ie, Vo<1.0V).

14. This load condition approximates the gate load of a 1200V/25A IGBT.

15. For each channel. When the operating frequency and Qg of the driving IGBT increase, the power supply current increases.

16. The device is considered to be a double-ended device: channel one output side pins are shorted together, channel two output side pins are shorted together.

application information

Eliminate negative IGBT gate drive To maintain stable IGBT off, the HCPL-314J has a very low maximum VL specification of 1 V to minimize the lead inductance of the RG and HCPL-314J to the IGBT gate and the emitter (possibly by placing the HCPL-314J A small PC board mounted directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications, as shown in Figure 19. Be careful with such a PC board design to avoid trace-routing the IGBT collector or emitter close to the HCPL-314J's input which can cause unwanted transient signal coupling to the HCPL-314J's input to degrade performance. (If the IGBT drain must be routed near the input of the HCPL-314J, the LED should be reverse biased when turned off to prevent transients from opening the IGBT drain of the HCPL-314J.) An external clamping diode can be connected at the lead. Between pins 14 and 15 and pins 9 and 10 (as shown in Figure 19), it is used to protect the HCPL-314J in the event of IGBT switching inductive loads.

Select Gate Resistor (Rg)

Step 1: Calculate the Rg minimum according to the IOL peak specification. The IGBT and Rg in Figure 24 can be analyzed as a simple RC circuit with the voltage supplied by the HCPL-314J.

The VOL value of 5 V in the above formula is VOL0.6A at peak current (see Figure 6).

Step 2: Check the power consumption of the HCPL-314J and increase Rg if necessary. HCPL-314J total power consumption (PT) is equal to the sum of emitter power (PE) and output power (PO)

where KICC•Qg•f is the ICC increase due to switching and KICC is a constant of 0.001 mA/(nC*kHz). For the circuit in Figure 19 with IF (worst case) = 10 mA, Rg = 32Ω, max duty cycle = 80%, Qg = 100 nC, f = 20 kHz and TAMAX = 85 degrees Celsius:

In the previous formula, for ICC, the value of 3ma is the maximum operating temperature range for the entire ICC. Since PO in this case is less than PO(MAX), Rg = 32Ω is the correct dissipation for power.

Ultra's LED driver circuit considerations

High CMR performance without detector shielding, the main cause of optocoupler CMR failure is that the input of the capacitively coupled optocoupler, through the package, reaches the detector IC, as shown in Figure 21. The HCPL-314J diverts capacitively coupled currents away from sensitive ICs by using an optically transparent Faraday shield. However, this shield does not remove the coupling between the capacitive LED and optocoupler pins 5-8 as shown. This capacitive coupling causes the perturbation of the LED current to become a CMR fault that shields the optocoupler during common-mode transients. The main design goal of a high CMR LED driver circuit becomes to keep the LED in the normal state during common mode (on or off) transients. For example, the proposed application circuit (Figure 19) can achieve 10 kV/µs CMR while minimizing component complexity. Keeping the LEDs in their proper state is in the next two sections.

CMR with LED (CMRH)

High CMR LED driver circuits must keep the LEDs on during common-mode transients. This is done by making the LED current too large to exceed the input threshold, so it doesn't pull below the threshold instantaneously. A minimum LED current of 8 mA provides enough headroom over the maximum IFLH of 5 mA to achieve. 10 kV/µs CMR. High CMR (CMRL) when LED is off The CMR LED driver circuit must keep the LED off (VF ≤ VF(off) during common mode transients. For example, during the -dVCM/dt transient in Figure 23, current flows through CLEDP also flows through the RSAT and the VSAT of the logic gate. As long as the state voltage is low, LEDs less than VF(OFF) developed through the logic gate will remain off and no common mode fault will occur. The open collector drive circuit shown in Figure 24 can be used in Does not keep the LED off during +dVCM/dt transients as all current through the Clayton must be provided as indicated by the LED and is not recommended for CMR1 performance where ultra high performance is required. An alternative driver circuit like the recommended application circuit ( Figure 19) Indeed ultra-high CMR performance is achieved by shunting the LEDs in the off state.

IPM Dead Time and Propagation Delay Specifications HCPL-314J includes Propagation Delay Difference (PDD) designed to help designers minimize "dead time" in their power inverter designs. Dead time is the time when the high and low side power transistors are turned off. Any overlap in the conduction of Q1 and Q2 will cause the current flowing through the power supply to be high voltage to the low voltage motor rails. In a given design, the turn-on of LED2 should be delayed (relative to the turn-off of LED1) so that in the worst case, transistor Q1 is just turned on and transistor Q2 is turned off when it is turned on, as shown in Figure 26. The amount of delay required to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDD max, which is specified. 500 ns over operating temperature range - 40° to 100°C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it doesn't tell the designer what the maximum dead time will be. The maximum dead time is equal to the maximum and minimum propagation delay difference specifications, as shown in Figure 27. The maximum dead time of HCPL-314J is 1 s (= 0.5 s). - (-0.5 microseconds) over operating temperature range -40°C to 100°C. Note that the propagation delay used to calculate the PDD takes the dead time at the same temperature and tests the conditions after the optocouplers under consideration are usually installed close to each other. Switching the same igbt.

PDD = Propagation Delay Difference

NOTE: For dead time and PDD calculations, all propagations are delayed at the same temperature and test conditions.