AK8811/12 are low voltage, low power, small package digital video encoders Price & Stock

NTSC-M, PAL-B, D, G, H, I, M, N encoding; Simultaneous composite video signal and S-video signal output; Y/Cb/Cr component output (based on EIAJ guidelines); CCIR- 656 4:2 :2 8-bit parallel inputs; -EAV decode; master/slave operation; digital field sync I/O; digital vertical/horizontal sync I/O; Y filter 2x oversampling; C filter 4x oversampling; single 27MHz clock ( Polarity can be reversed by SYSINV pin); three 10-bit DACs; I2C interface (400kHz); closed caption encoding (NTSC: line 21284 - SMPTE PAL: line 21334 - CCIR); Macrovision copy protection version. 7.1* ( AK8812 only); VBID, CGMS (EIAJ CPR-1024); on-chip color bar generator; low power consumption; 3.3V only, CMOS monolithic; 48-pin LQFP package.

The AK8811 and AK8812 are low voltage, low power, small package digital video encoders. They are suitable for portable DVD or VCD players. They convert ITU-R.BT601/656 standard 8-bit parallel data to analog composite video, S-video or analog component signal Y/Cb/Cr-in NTSC and PAL formats.

The AK8812 and AK8811 support Macrovision copy protection version 7.1 (AK8812 only), closed captioning and video blanking ID (CGMS). These functions are controlled by the high-speed I2C bus interface.

When reset pin[/reset] is set to "L", AK8811/12 is in reset state. The AK8811/12 starts up with an internal initialization sequence on the trailing edge of the first system clock after the reset pin is "L". All internal registers are set to their default values by this initialization sequence. The AK8811/12 requires at least 10 SYSCLK clock counts to perform this reset operation. After a reset operation, the video output pins are in a high impedance state. AK8811/12 requires SYSCLK for reset operation.

The AK8811/12 requires a 27MHz clock to run on the SYSCLK pin. Video input data (ITU-R BT.656) is sampled at the trailing edge of 27MHz. SYSINV determines the direction of the edge. SYSINV=L Data is sampled on the rising edge of SYSCLK. SYSINV=H Data is sampled on the falling edge of SYSCLK.

The AK8811/12 can interface with video input data in the following 3 ways. The mode is set by the register [Interface Mode Register (00H)].

For the ITU-R BT.656 format that does not include EAV, there are master and slave modes. In this mode, the [Interface Mode Register (00H)] CCIR bit should be set to "0".

The AK8811/12 provides FID/VSYNC and HSYNC to external devices based on the AK8811/12 internal timing counter. The AK8811/12 starts sampling the input data at a fixed value on the internal pixel counter.

In this mode, the following settings should be made for [Interface Mode Register (00H)].

CCIR bit = 0;

MAS bit = 1.

FID/VSYNC and HSYNC are provided by external devices. The AK8811/12 samples the data in the same way as the master mode.

In this mode, the following settings should be made for [Interface Mode Register (00H)].

CCIR bit = 0;

MAS bit = 0.

video signal conversion

The video reconstruction module converts the multiplexed data (ITU-R.BT601 Y/Cb/Cr) into NTSC-M, PAL-M, PAL-B, D, G, H, I, N and other formats (such as NTSC- 4.43 and PAL60) interlaced format. The video reconstruction format, line number, color coding method (NTSC or PAL), and frequency of the color subcarrier are specified by [Video Processing 1 Register (01H)]. (See burst signal table) The frequency and phase of the color subcarrier can also be adjusted by [Sub C. Frequency Register (06H)] and [Sub C. Phase Register (07H)]. The subcarrier has a free running mode and a reset mode. In reset mode, the subcarrier is automatically reset to the initial phase every 4 fields (NTSC) or 8 fields (PAL).

Component video output

The video output mode is set by the [Video Processing 3 Register (03H)] VS bit.

AK8811/12 can output not only composite video signal and S video signal, but also component video signal (Y/Cb/Cr). Component video signals conform to EIAJ guidelines 1998/3 .

VS bit=0: composite video signal and S video signal output;

VS bit=1: Component video signal output.

Brightness filter

The luminance signal is passed through a 2x low-pass filter Figure 1 is a characteristic of the luminance filter.

Chroma filter

The chrominance signals (Cb, Cr) before subcarrier modulation pass through the 1.3mhz low-pass filter shown in Figure 2. The chrominance signal modulated by the subcarrier passes through the filter shown in FIG. 3 .

color burst

Color bursts are generated by a 24-bit digital frequency synthesizer. The default frequency of color burst is selected by [Video Processing 1 Register (0x01)].

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When PAL-M mode is selected, the allowed subcarrier frequency is 3.57561188MHz.

The burst frequency and initial phase resolution are as follows.

Frequency resolution 0.8046Hz; SCH phase resolution 360°/256.

Video DAC

The AK8811/12 features three current-driven 10-bit DACs operating at 27MHz. The full-scale voltage of the DAC is determined by the current output at the IREF pin. With a VREFIN of 1.235V between the IREF pin and ground (AVSS), 12KΩ, and a DAC load resistance of 390Ω, the typical output voltage is 1.28Vo-p. This full-scale voltage should be set in the range of 1.17V to 1.33V by adjusting the resistor that terminates the IREF pin. Each DAC output can be set to "active state" or "inactive state" via [DAC Mode Register (05H)]. When the DAC is "inactive", the output is high impedance. When all DACs are set to "inactive", the analog part of the AK8811/12 goes into sleep mode. In this case, the AK8811/12 stops outputting the reference voltage (VREF) output. When any DAC switches from sleep mode to "active state", the AK8811/12 starts to output the reference voltage. In this case, the AK8811/12 requires a VREF wake-up time of several milliseconds.

Using the internal VREF as the reference voltage, connect the [VREF OUT] pin to the [VREF IN] pin and the [VREF OUT] pin to a capacitor larger than 0.1uF.

Use an external reference voltage

To improve the accuracy of the DAC output, an external reference voltage can be used. In this case, the VREFOUT pin still needs to be terminated with a capacitor larger than 0.1uF.

Closed Captioning and Extended Data

The AK8811/12 supports closed captioning and extended data. They are controlled by [Video Processing 2 Register (02H)] "On" or "Off" respectively. Each data consists of 2 consecutive byte registers (Closed Caption R(16H, 17H)), when the second byte (17H register) is written to the register, it is recognized as the data is updated. After the data is updated, the AK8811/12 encodes the closed caption and extended data for the specified line. If the data is not updated, the AK8811/12 outputs the "ASCII-NULL" code. Data is considered parity and 7-bit usasii code. The host should provide a parity bit.

*In PAL encoding mode, the AK8811/12 outputs them with the same timing and mode as NTSC.

*Lines that encode closed captioning data are shown below.

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Video ID

AK8811/12 supports Video ID (EIAJ standard, CPR-1204) encoding for distinguishing aspect ratio, etc. This function is turned on/off when the VBID bit of [Video Processing 2 Register (02H)] is set or reset. Set the data by using [Video ID Data Register (1AH, 1BH)].

VBID data update timing.

VBID data layout

VBID consists of 20 bits and its format is shown below.

The AK8811/12 automatically generates a CRC code and appends it to the data. The initial value of the polynomial is 1.

VBID waveform

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AK8811/12 Interface Timing (Part 1) Main Mode and ITU-R BT.656 Mode

In ITU-R BT.656 decoding mode or master mode operation, the AK8811/12 outputs HSYNC and FID or VSYNC (selected by register).

When the AK8811/12 receives the ITU-R BT.656 signal, the AK8811/12 decodes the EAV code in the data for synchronization, and then outputs HSYNC. The AK8811/12 outputs HSYNC on the rising edge of SYSCLK at the timing of the 32nd/24th (NTSC/PAL) data time slot, which is counted from the [EAV] start point as shown below. (See also AC Characteristics 2-2 [Input Sync Signal]) When operating in master mode, the front device connected to the AK8811/12 (eg MPEG decoder) starts to set Cb on the 276/288 (NTSC/PAL) slot, Then start counting HSYNC falling edges for the 32nd/24th (NTSC/PAL) slot.

FID/VSYNC is output in sync with HSYNC at the solid line timing, as shown in the video field in Figure 10.

AK8811/12 Interface Timing (Part 2) Slave Mode

In slave mode operation, HSYNC and FID or VSYNC (selected by register) are input to the AK8811/12.

The AK8811/12 monitors the transition of HSYNC at the rising edge of SYSCLK. (Refer to AC Characteristics 2-1. [Input Sync Signal]) After the AK8811/12 recognizes that HSYNC is low logic, the AK8811/12 internally sets the slot number to the 32nd/24th (NTSC/PAL), and then the AK8811/ 12 starts sampling data as Cb on slot 276/288 (NTSC/PAL).

Video fields are identified by the transition timing between FID/VSYNC and HSYNC. (Fig. 10. Video field) As shown, there is a relative relationship of ±1/4H.