During the circuit design process, application engineers often overlook the layout of the printed circuit board (PCB). The problem often encountered is that the schematic of the circuit is correct, but it doesn't work, or just runs at low performance. In this article, I'll show you how to properly lay out an op amp's board to ensure its functionality, performance, and robustness.

Recently I was working with an intern with a gain of 2V/V and a load of 10k? , The power supply voltage is +/-15V non-inverting configuration OPA191 operational amplifier is designed. Figure 1 shows a schematic of the design.

How to Layout an Op Amp PCB

Figure 1: OPA191] OPA191 schematic in non-inverting configuration

I had the intern lay out the board for the design and gave him general instructions on PCB layout (eg: keep the trace paths on the board as short as possible, and keep the components as close as possible to reduce the footprint of the board space) and let him design it himself. How difficult is the design process? It's really just a few resistors and capacitors, isn't it? Figure 2 shows his first attempt at designing the layout. The red line is the path for the top layer of the board, while the blue line is the path for the bottom layer.

How to Layout an Op Amp PCB

Figure 2: First Layout Attempt Scenario

Seeing his first layout attempts, I realized that the board layout was not as intuitive as I thought; I should have at least made some more detailed instructions for him. He did exactly what I suggested in his design: he shortened the traces and packed the parts closely together. However, there is a lot of room for improvement in this layout in order to reduce board parasitic impedance and optimize its performance.

The next step is to improve the layout. The first improvement we made was to move resistors R1 and R2 next to the inverting pin (pin 2) of the OPA191; this helped reduce the stray capacitance on the inverting pin. The op amp's inverting pin is a high-impedance node and therefore has high sensitivity. Longer trace paths can act as wires, allowing high frequency noise to couple into the signal chain. PCB capacitance on the inverting pin can cause stability problems. Therefore, the contact on the inverting pin should be as small as possible.

Moving R1 and R2 next to pin 2 allows the load resistor R3 to be rotated 180 degrees, which brings decoupling capacitor C1 closer to the positive supply pin (pin 7) of the OPA191. It is extremely important to place the decoupling capacitors as close as possible to the supply pins. Longer trace paths between the decoupling capacitors and the supply pins increase the inductance of the supply pins, which reduces performance.

Another improvement we made is the second decoupling capacitor C2. The via connection of VCC to C2 should not be placed between the capacitor and the power supply pin, but should be routed where the supply voltage must pass through the capacitor to the power supply pin of the device. Figure 3 shows how to move each part and vias to improve the layout.

How to Layout an Op Amp PCB

Figure 3: Component placement for improved layout

After moving parts to new locations, some other improvements can still be made. You can widen the trace path to reduce the inductance, which is equivalent to the size of the pad the trace path connects to. It can also flood the ground planes on the top and bottom layers of the board, creating a solid, low-impedance path for return current. Figure 4 shows our final layout.

How to Layout an Op Amp PCB

Figure 4: Final layout

The next time you lay out a printed circuit board, it is recommended that you follow these layout conventions:

Keep the inverting pin connections as short as possible.

Place the decoupling capacitors as close to the power pins as possible.

If multiple decoupling capacitors are used, place the smallest decoupling capacitor closest to the power supply pins.

Do not place vias between decoupling capacitors and power pins.

Widen the trace path as much as possible.

Do not allow 90-degree angles in the trace path.

Pour at least one solid ground plane.

Don't sacrifice good layout in order to mark parts with silkscreen layers.

Above, we talked about the proper way to layout an instrumentation amplifier (op amp) PCB and provided a list of good layout practices to follow. Next, I will discuss common mistakes in laying out instrumentation amplifiers (INAs), and then show how to properly lay out an INA PCB.

INAs are used in applications that require amplification of differential voltages, such as measuring voltages across shunt resistors in high-side current sensing applications. Figure 5 shows a schematic of a typical single-supply high-side current-sensing circuit.

How to Layout an Op Amp PCB

Figure 5: High-Side Current Sensing Schematic

Figure 5 measures the differential voltage across RSHUNT, R1, R2, C1, C2 and C3 are used to provide common-mode and differential-mode filtering, R3 and C4 provide output filtering of the U1 INA, and U2 is used to buffer the reference pin of the INA. R4 and C5 are used to form a low-pass filter to minimize noise from the op amp to the INA reference pin.

Although the schematic layout in Figure 5 looks intuitive, it is very easy to make mistakes in the PCB layout, resulting in degraded circuit performance. Figure 6 shows three common mistakes workers make when checking INA layouts.

How to Layout an Op Amp PCB

Figure 6: INA common PCB layout

As you can see from the image above, the first error is in the way the differential voltage Rshunt is measured across the resistor. It can be seen that the line from Rshunt to R2 is shorter, so its resistance is smaller than the resistance of the line from Rshunt to R1. This difference in line impedance may introduce a differential voltage on the input side of U1 due to the input bias current introduced into the INA. Since the task of the INA is to amplify the differential voltage, errors can occur if the lines on the input side are unbalanced. Therefore, make sure that the INA input lines are balanced and as short as possible.

The second error is about the INA gain setting resistor Rgain. The trace from the U1 pin to the Rgain pad is longer than the actual required length, thus causing additional resistance and capacitance. Since the gain depends on the INA gain setting pin, the resistor between Pin 1 and Pin 8, additional resistors may give the wrong target gain. And since the gain setting pin of the INA is connected to the feedback section within the INA, the extra capacitance can cause stability problems. Therefore, make sure that the lines connecting the gain setting resistors are kept as short as possible.

Finally, the location of the reference pins of the buffer circuit may need to be improved. The reference pin buffer circuit is located far from the reference pin, which can increase the resistance connected to the reference pin and cause noise or other signals to couple into the line. Additional resistance on the reference pin may degrade the high common-mode rejection ratio (CMRR) offered by most INAs. Therefore, place the reference pin buffer circuit as close as possible to the INA reference pin.

How to Layout an Op Amp PCB

Figure 7: PCB layout after correcting three types of errors

In Figure 7, it can be seen that the R1 and R2 traces to the shunt resistor are the same length, with a Kelvin connection. The gain setting resistor to the INA pin trace is kept as short as possible, and the reference buffer circuit is kept as close to the reference pin as possible.