feature

Low power ( 250 μA@5V) single 16-bit nanoDAC; 12-bit accuracy guaranteed; tiny 8-lead SOT-23 /MSOP package; reduced to 480 mA at 5 V and 100 mA at 3 V; top Electrical reset to zero/midscale; 2.7 V to 5.5 V supply; 16-bit monotonicity guaranteed by design; 3 power-down functions; serial interface to Schmitt trigger input; rail-to-rail operation; synchronous interrupt facility; temperature Range -40°C to +125°C; suitable for automotive applications.

application

Process Control; Data Acquisition Systems; Portable Battery-Powered Instruments; Digital Gain and Offset Adjustment; Programmable Voltage and Current Sources; Programmable Attenuators.

General Instructions

The AD5662 , a member of the nanoDAC family, is a low power, single 16-bit buffered voltage output DAC that operates from a single 2.7 volts to 5.5 volts and is designed to be monotonic.

The AD5662 requires an external reference voltage to set the output range of the DAC. This section includes a power-on reset circuit that ensures that the DAC output powers up to 0v (AD5662x-1) or mid-scale (AD5662x-2) until a valid write occurs. This part includes a power-down function that reduces the current consumption of the device to 480Na at 5V and provides a software-selectable output load in power-down mode.

The low power consumption of this part during normal operation makes it ideal for portable battery-operated devices. Power consumption is 0.75mW at 5v, which reduces to 2.4µW in power-down mode.

The on-chip precision output amplifier of the AD5662 allows for track twist output swing. For remote sensing applications, the inverting input of the output amplifier is available to the user.

The AD5662 uses a versatile 3-wire serial interface, operates at clock frequencies up to 30 MHz, and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards.

Product Highlights

1. Guaranteed 16-bit DAC-12-bit precision.

2. Provide 8-lead SOT-23 and 8-lead MSOP packaging.

3. Low power. Typically consumes 0.42mW at 3V and 0.75mW at 5V.

4. Power on and reset to zero or mid-scale.

5. The maximum sedimentation time is 10μs.

Timing Characteristics

All input signals are specified with tr=tf=1 ns/V (10% to 90% V) and timed from a voltage level of (V+V)/2. See Figure 2. V=2.7 V to 5.5 V; all specifications T to T unless otherwise noted.

Absolute Maximum Ratings

T=25°C unless otherwise noted.

Stresses listed above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions listed in the operating section of this specification or any other conditions above is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Typical performance characteristics

the term

Relative Accuracy or Integral Nonlinearity (INL) For DACs, relative accuracy or integral nonlinearity is the maximum deviation measured from a straight line in the LSBs through the endpoints of the DAC transfer function. A typical INL and code diagram is shown in Figure 4.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured variation and the ideal 1lsb variation of any two adjacent codes. The specified differential nonlinearity ±1 LSB maximum guarantees monotonicity. The monotonicity of the DAC is guaranteed by design. A typical DNL and code diagram is shown in Figure 5.

Zero code error

A zero code error is a measure of the output error when a zero code (0x0000) is loaded into the DAC register. Ideally, the output should be 0 V. Since the output of the DAC cannot go below 0 V, the zero code error is always positive in the AD5662. This is due to a combination of offset errors in the DAC and output amplifier. Zero-code errors are expressed in millivolts. The relationship between zero code error and temperature is shown in Figure 11.

full scale error

Full-scale error is a measure of the output error when the full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be V-1 LSB. Full-scale error is expressed as a percentage of full-scale range. A plot of full-scale error versus temperature is shown in Figure 10. due diligence

gain error

This is a measure of the span error of the DAC. It is the slope deviation of the DAC transfer characteristic from ideal, expressed as a percentage of the full-scale range.

Total Unadjusted Error (TUE)

Total unadjusted error is a measure of output error that takes into account all of the various errors. A typical TUE and code diagram is shown in Figure 6.

Zero code error drift

This is a way to measure the zero code error as a function of temperature. Expressed in μV/°C.

Gain temperature coefficient

This is a measure of gain error as a function of temperature. Expressed in (ppm of full scale)/°C.

offset error

Offset error is the difference between V(actual) and V(ideal) in mV in the linear region of the measurement transfer function. The offset error is measured on the AD5662 and the DAC register is loaded with code 512. It can be negative or positive. out

DC Power Supply Rejection Ratio (PSRR)

This shows how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to the change in VDD for the full-scale output of the DAC. The unit is decibel. VREF remains at 2v and VDD varies by ±10%.

Output voltage settling time

This is the time required for the output of the DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change, measured from the 24th falling edge of SCLK.

Digital-to-analog fault pulse

A digital-to-analog fault pulse is a pulse injected into the analog output when the input code in the DAC register changes state. It is usually designated as a fault region in nV-s and is measured when the digital input code is changed by 1lsb at the major carry transition (0x7FFF to 0x8000). See Figures 25 and 26.

digital feedthrough

Digital feedthrough is a measurement of the pulses injected into the DAC's analog output from the DAC's digital input, but when the DAC output is not being updated. It is specified in nV-s and is measured by a full-scale code change on the data bus, i.e. from 0 to 1 and vice versa.

Total Harmonic Distortion (THD)

This is the difference between an ideal sine wave and a decaying sine wave using a DAC. The sine wave is used as a reference for the DAC, and THD is a measure of the harmonics of the DAC's output. The unit is decibel.

noise spectral density

This is a measure of internally generated random noise.

Random noise is characterized by spectral density (voltage per √Hz). It is measured by loading the DAC to midscale and measuring the noise at the output. The unit of measurement is nV/√Hz. The noise spectral density plot is shown in Figure 31.

theory of operation

DAC segment

The AD5662 DAC is fabricated in a CMOS process. The structure consists of a string DAC and an output buffer amplifier. Figure 32 shows a block diagram of the DAC architecture.

Since the input encoding of the DAC is straight binary, the ideal output voltage is given by:

where D is the decimal equivalent of the binary code loaded into the DAC register. The range is from 0 to 65535.

resistor string

The resistor string section is shown in Figure 33. It's just a string of resistors, each with a value of R. The code loaded into the DAC register determines at which node on the string the voltage is tapped into the output amplifier. The voltage is cut off by closing a switch to connect the string to the amplifier. Because it is a string of resistors, monotonicity is guaranteed.

output amplifier

The output buffer amplifier can generate rail-to-rail voltages at its output with an output range of 0v to V. The output buffer amplifier has a gain of 2 from a 50kΩ resistor divider network in the feedback path. The inverting input of the output amplifier is available to the user, allowing remote sensing. This V pin must be connected to V for proper operation. It can drive a 2 kΩ load in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier are shown in Figure 15. The slew rate is 1.5v/µs, and the full scale settling time from 1/4 to 3/4 is 10µs.

serial interface

The AD5662 has a 3-wire serial interface (Sync, SCLK, and it is compatible with SPI, QSPI, and MICROWIRE interface standards and most DSPs. See Figure 2 for a timing diagram for a typical write sequence.

Pull the sync line low at the beginning of the write sequence. Data from the data line is recorded into a 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5662 compatible with high-speed DSPs. On the falling edge of the 24 clock, the last data bit is clocked and the programming function is performed, ie, a change in the contents of the DAC register and/or a change in opera mode - the first action. During this phase, the sync line can be held low or high. In both cases, it must be turned up at least 33 ns before the next write sequence so that SYNC can initiate the next write sequence. Because the sync buffer draws more current at V=0.8 V at V=2.4V than at V=2.4V, the synchronization between write sequences should be low idle for lower power operation. However, as mentioned earlier, it must be turned up again before the next write sequence.

input shift register

The width of the input shift register is 24 bits (see Figure 34). The first six are not important. The next two are control bits that control the mode of operation of the part (normal mode or any of the three power-down modes). See the Power Down Modes section for a more complete description of the various modes. The next 16 bits are the data bits. They are transferred to the DAC register on the falling edge of SCLK 24.

Sync outage

In a normal write sequence, the sync line is held low for at least 24 falling edges of SCLK, and the DAC is updated on 24 falling edges. However, if sync is brought high before the falling edge of 24, this will act as an interruption to the write sequence. The shift register is reset and the write sequence is considered invalid. Neither an update of the DAC register contents nor a change in operating mode occurs (see Figure 35).

power-on reset

The AD5662 family includes a power-on reset circuit that controls the output voltage during power-up. The AD5662x-1 DAC outputs power up to 0 V, and the AD5662x-2 DAC outputs power up to midscale. The output remains there until a valid write sequence to the DAC. This is useful in applications where it is important to know the state of the DAC's output during power-up.

Power down mode

The AD5662 contains four independent modes of operation. These modes are software programmable by setting two bits in the control register (DB17 and DB16). Table 5 shows how the state of the bits corresponds to the operating mode of the device.

When both bits are set to 0, the part operates normally at 5V and its normal power consumption is 250µA. However, for the three power-down modes, the supply current drops to 480Na at 5V (100Na at 3V). Not only does the supply current drop, but the output stage also switches from inside the amplifier's output to a network of resistors of known value. The advantage of this is that the output impedance of the component is known when the component is in power down mode. The output can be internally connected to GND through a 1kΩ or 100kΩ resistor, or left open (tri-stated) (see Figure 36).

When the power-down mode is activated, the bias generator, output amplifier, resistor string and other associated linear circuits are turned off. However, when powered down, the contents of the DAC registers are not affected. The power-off time is typically 4 μs, V = 5 V, and V = 3 V (see Figure 24).

Microprocessor interface

AD5662 to Blackfin® ADSP-BF53x Interface

Figure 37 shows the serial interface between the AD5662 and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor family includes two dual-channel synchronous serial ports SPORT1 and SPORT0 for serial and multiprocessor communications. Use SPORT0 to connect to the AD5662 and the interface settings are as follows. DT0PRI drives the DIN pin of the AD5662, while TSCLK0 drives the part's SCLK. Synchronization is driven by TFS0.

AD5662 to 68HC11/68L11 interface

Figure 38 shows the serial interface between the AD5662 and the 68HC11/68L11 microcontroller. The SCK of the 68HC11/68L11 drives the SCLK of the AD5662, while the MOSI output drives the serial data line of the DAC.

The sync signal comes from the port line (PC7). The setup conditions for correct operation of this interface are as follows. The CPOL bit of the 68HC11/68L11 is configured as 0 and the CPHA bit is configured as 1. When data is transferred to the DAC, the sync line is low (PC7). When the 68HC11/68L11 is configured as described above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data for the 68HC11/68L11 is transferred in 8-bit bytes with only 8 falling clock edges during the transfer cycle. The data MSB is transferred first. To load data into the AD5662, after the first 8 bits have been transferred, PC7 is held low and a second serial write to the DAC is performed; at the end of the process, PC7 is taken high.

AD5662 to 80C51/80L51 interface AD5662 to MICROWIRE interface

Figure 39 shows the serial interface between the AD5662 and the 80C51/80L51 microcontroller. The interface settings are as follows. The 80C51/80L51's TxD drives the AD5662's SCLK, while the RxD drives the part's serial data lines. The sync signal again comes from the bit programmable pins on the port. In this case, use port line P3.3. When data is to be sent to AD5662, P3.3 is taken low. The 80C51/80L51 only transmits data in 8-bit bytes; therefore only 8 falling clock edges occur during the transmit cycle. To load data into the DAC, P3.3 is held low after the first 8 bits have been sent and a second write cycle is initiated to send the second byte of data. P3.3 rises after this cycle is completed. The 80C51/80L51 outputs serial data in a format with LSB first. The AD5662 must receive data with the MSB first. The 80C51/80L51 transfer routines should take this into account.

Figure 40 shows the interface between the AD5662 and any Microwire compatible device. Serial data is shifted on the falling edge of the serial clock and recorded into the AD5662 on the rising edge of SK.

application

Select Reference for AD5662

To get the best performance from the AD5662, consideration should be given to selecting an accurate voltage reference. The AD5662 has only one reference input, V. The voltage on the reference input is used to provide the positive input to the DAC. Therefore, any errors in the reference will be reflected in the DAC.

When choosing a voltage reference for a high-precision application, error sources are initial accuracy, ppm drift, long-term drift, and output voltage noise. The initial accuracy of the DAC's output voltage will result in the full-scale error of the DAC. To minimize these errors, benchmarks with high initial accuracy are preferred. In addition, selecting a reference with output trim adjustment, such as the ADR423, allows the system designer to trim system errors by setting the reference voltage to a voltage other than the nominal voltage. The trim adjustment can also be used to trim any errors at temperature.

Long-term drift is a measure of how much a reference drift changes over time. A reference with strict long-term drift specifications ensures that the entire solution remains relatively stable over its entire lifetime.

Temperature coefficient of reference output voltage effects, including L, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce the temperature dependence of the DAC output voltage under ambient conditions.

In high-precision applications with relatively low noise budgets, the reference output voltage noise needs to be considered. Choosing a reference voltage with as low an output noise voltage as possible is important for system noise resolution requirements. Precision voltage references such as the ADR425 produce low output noise in the 0.1Hz to 10Hz range. Table 6 gives examples of recommended accuracy references for the AD5662.

Use the reference as the power supply for the AD5662

Since the supply current required by the AD5662 is extremely low, another option is to use a voltage reference to supply the required voltage to the part (see Figure 41). This is especially useful if the power supply is noisy, or if the system supply voltage is not 5V or 3V, such as 15V. The voltage reference outputs the regulated supply voltage for the AD5662; see Table 6 for a suitable reference. If a low dropout REF195 is used, it must supply 250µA to the AD5662 with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply current to the load. The total current required (with a 5 kΩ load on the DAC output) is 250 μA + (5 V/5 kΩ) = 1.25 mA, the load regulation of the REF195 is typically 2ppm/mA, which results in a 1.25ma current drawn from it of 2.5 ppm (12.5µV) error. This corresponds to a 0.164 LSB error.

Bipolar Operation Using the AD5662

The AD5662 is designed for single-supply operation, but a bipolar output range can also be achieved using the circuit in Figure 42. The output voltage range of this circuit is ±5 V. Using the AD820 or OP295 as the output amplifier enables rail-to-rail operation at the output of the amplifier.

The output voltage of any input code can be calculated as follows:

where D represents the input code in decimal (0 to 65535). When V=5 V, R1=R2=10 kΩ,

This is an output voltage range of ±5 V, 0x0000 corresponds to -5 V output and 0xFFFF corresponds to +5 V output.

Using the AD5662 as an Isolated, Programmable, 4-20 mA Process Controller

In many process control system applications, two-wire current transmitters are used to transmit analog signals through noisy environments. These current transmitters use a zero-scale signal current of 4 mA to power the transmitter's signal conditioning circuitry. The full-scale output signal of these transmitters is 20 mA. Inverse process control methods can also be used; a low-power, programmable current source can be used to control remotely located sensors or devices in the loop.

A circuit to perform this function is shown in Figure 43. Using the AD5662 as the controller, the circuit provides a programmable output current of 4 to 20 mA, proportional to the DAC's digital code. Provide bias for the controller

There are two reasons why the ADR02 does not require external trimming: (1) the ADR02 has a small initial output voltage tolerance; and (2) the supply current consumption of the AD8627 and AD5662 is low. The entire circuit, including the optocoupler, consumes less than 3mA from a total budget of 4mA. The AD8627 regulates the output current to meet the sum of the currents at the non-spinning nodes of the AD8627.

IOUT = 1/R7 (VDAC × R3/R1 + VREF × R3/R2)

For the values shown in Figure 43, IOUT = 0.2435 μA × D + 4 mA.

Where D=0≤D≤65535, when the digital code of AD5662 is equal to 0xFFFF, a full-scale output current of 20 mA is given. Offset trimming at 4 mA is provided by P2, while P1 provides gain trimming of the circuit at 20 mA. Because the non-vertical input of the AD8627 is on the virtual ground, the two trims do not interact. Schottky diode D1 is required in this circuit to prevent loop supply transients from pulling the non-inverting input of the AD8627 below 300mV above its inverting input. Without this diode, this transient could cause phase reversal of the AD8627 and latch-up of the controller. The loop supply voltage compliance of the circuit is limited by the maximum applied voltage to the ADR02, from 12 V to 40 V.

Using AD5662 with Galvanically Isolated Interface

In process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the control circuit from any dangerous common-mode voltages that may be present in the area where the DAC operates. The isocoupler provides over 3 kV. The AD5662 uses a 3-wire serial logic interface, so the ADuM130x 3-channel digital isolators provide the required isolation (see Figure 44). The power supply to this part also needs to be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V required by the AD5662.

Power Bypass and Ground

When accuracy is important in a circuit, it is helpful to carefully consider the power and ground return layout on the board. A printed circuit board containing the AD5662 should have separate analog and digital sections, each with its own board area. If the AD5662 is in a system where other devices require an AGND to DGND connection, it should only be connected at one point. This ground point should be as close as possible to the AD5662.

The supply to the AD5662 should be bypassed with 10µF and 0.1µF capacitors. The capacitor should be as close to the device as possible, ideally the 0.1µF capacitor is facing the device. The 10µF capacitors are of the tantalum bead type. It is important that 0.1µF capacitors have low effective series resistance (ESR) and effective series inductance (ESI), for example, common ceramic capacitors. This 0.1µF capacitor provides a low impedance ground path for high frequencies caused by transient currents generated by the internal logic switches.

The power cord itself should have as large a trace as possible to provide a low impedance path and reduce the impact of faults on the power cord. Clocks and other fast switching digital signals should be shielded from the rest of the board by digital ground. Avoid crossover of digital and analog signals as much as possible. When the traces cross on opposite sides of the board, make sure they run at right angles to each other to reduce the effect of feedthrough through the board. The best board layout technique is microstrip, where the component side of the board is used only for the ground plane, and the signal traces are placed on the solder side. However, this is not always possible with two-layer boards.

Dimensions