The HIP4086 and HIP4086A (referred to as HIP4086/A) are three-phase N-channel MOSFET drivers. Both parts are dedicated to PWM motor control. These drivers have flexible input protocols to drive every possible switch combination. Users can even override protection through switched reluctance applications. The HIP4086/A have a wide range of programmable dead-time times (0.5µs to 4.5µs), which makes them ideal for low frequencies (up to 100kHz) typically used for motor drives. The only difference between HIP4086 and HIP4086A HIP4086A has the built-in priming pump disabled. This is useful in applications that require very quiet EMI performance (the charge pump operates at 10 MHz). The advantage of this HIP4086 is that the built-in priming pump allows for unlimited on-time for high-end drivers. Make sure the high-side driver start-up capacitor is fully charged before power-on, and the programmable start-up refresh pulse is activated when VDD is first applied. When activated, the refresh pulse turns on all three low-side bridge FETs while holding down the three high-side bridge FETs to charge the high-side start-up capacitors. After the refresh pulse is cleared, normal operation begins. Another useful feature of the HIP4086/A is the programmable undervoltage setpoint. Setpoints range from 6.6V to 8.5V.

feature

3-phase independent driving of 6 N-channel mosfet bridge structures

Bootstrap power supply up to 95VDC with bias power supply from 7V to 15V

1. 25A peak shutdown current

User programmable dead time (0.5µs to 4.5µs)

A bootstrap and optional charge pump maintain the high side driver bias voltage.

Programmable Boot Refresh Time

Drive 1000pF load, typical rise and fall time is 20ns10ns time

Programmable undervoltage setpoint

application

Brushless Motor (BLDC)

Three-phase AC motor

Switched Reluctance Motor Driver

battery powered vehicle

battery powered tools

AN9642, "HIP4086 Three-Phase Bridge Driver Configuration and Application"

AN1829, "HIP4086 Three-Phase Brushless DC Motor Driver Demo Board, User's Guide"

Note: X means the input can be "1" or "0"

DC Electrical Specifications VDD=VxHB=12V, VSS=VxHS=0V, RDEL=20k, RUV=, Gate Capacitance (CGATE)=1000pF, unless otherwise specified. Blackbody limits apply over the entire operating junction temperature range, -40°C to +150°C.

DC Electrical Specifications VDD=VxHB=12V, VSS=VxHS=0V, RDEL=20k, RUV=, Gate Capacitance (CGATE)=1000pF, unless otherwise specified. Blackbody limits apply over the operating junction temperature range, -40°C to +150°C. (continued)

notes:

1. The specified charge pump current is the total current driving the xHO and xHS external loads.

2. Ensure compliance with data sheet limits by one or more methods: production testing, characterization, and/or design.

AC Electrical Specifications VDD=VxHB=12V, VSS=VxHS=0V, CGATE=1000pF, RDEL=10k, unless otherwise specified. The boldface limits apply over the entire operating junction temperature range, -40°C to +150°C.

Function description

input logic

Note: For brevity, input and output pins will be prefixed with "x" instead of a, B, or C. For example, xHS means pins, BHS and CHS. The HIP4086/A is a specially designed three-phase bridge driver for motor drive applications. Three identical half-bridge sections, A, B and C, can be individually controlled by their input pins ALI, AHI, BLI, BHI and CLI, CHI (xLI, xHI) or 2 corresponding input pins of each section can be Connected together to form a PWM input (xLI connected to xHI = xPWM). When controlling individual time inputs, programmable dead time is optional, but then the penetration protection input signal must be added to the timing. If PWM mode is selected, a programmable dead-time penetration protection must be used internally. To prevent shoot-through, the dead time is achieved by delaying the steering of the high-side and low-side drivers. Delay timer if the voltage on the RDEL pin is greater than 100mV. The voltage on RDEL for any programmed resistance value within the specified range. If the voltage on RDEL is less than 100mV, the delay timer is disabled and no penetration protection is provided by the internal logic of the HIP4086/A. When dead time is disabled, RDEL should be shorted to VSS. The refresh pulse ensures that the boot capacitor is charged to the high-side driver before start-up, and the refresh pulse is triggered when DIS is low or when the UV comparator transitions low (VDD is greater than the programmed undervoltage threshold). Please refer to "Block Diagram" on page 2. When triggered, the refresh pulse turns on all low-side drivers (xLO=1) and turns off all high-side drivers (xHO=0) for the duration by a resistor connected between RDEL and VSS. When xLO=1, the low-side bridge FET charges the boot capacitor from VDD through the boot diode.

oil filling pump

The internal charge pump of the HIP4086/A is used to maintain the bias voltage on the starting capacitor at 100% duty cycle. There is no term limit for this period. The user must understand that this charge pump only provides current for statically biasing the high-side driver and the high-side bridge FET. It can't be delivered in a reasonable amount of time, most of the charge on the startup capacitor is dissipated when the xHO driver turns the gate charge on the viaduct. Start capacitors are sized so they don't over-discharge charge at the gate. See Application Information for adjusting the start-up capacitor. The charge pump has enough capacity to generate a worst case external load of at least 40µA. The gate leakage current is around 100nA for most power MOSFETs, so there is enough current to keep the boot capacitor charged. The use of resistors on the high-side bridge FET is not recommended because the charge pump current is small. when? Calculate the leakage load at the output of xHS, also including the leakage current of the startup capacitor. This is rarely a problem but it can be a problem with electrolytic capacitor temperature. Application Information Selecting the Startup Capacitor Value The choice of the startup capacitor value is not only to provide the bias current for the internal high-side driver. It is worth noting that providing gate charge to drive the FET results in an excessive drop in the startup voltage. In practice, the total charge of the boot capacitor should be about 5% of the gate charge driving the power FET drop from the voltage capacitance to gate capacitance after transferring charge from startup. The following parameters shown in Table 2 are the values to calculate the voltage drop when using the HIP4086/A (no charge pump) for a specific number of startup capacitors. In Table 2, the values used are arbitrary. Should be changed to match the actual application.

Equation 1 calculates the total cost duration required for the period. This equation assumes that all parameters remain constant over the period. If the ripple is small.

If the gate-to-source resistor is removed (RGS is usually not required or recommended), then:

These Cboot values will be in cycles with only a small amount of ripple. But in HIP4086, the charge pump reduces the value of Cboot even more. The specified charge pump current is at least 40 microamps, which is enough to cause leakage. Also, because the specified charge pump current exceeds that required for the IHB, the total cost capacitor provided by boot is required as shown in Equation 2.

The starting capacitor required is not only small in value, but also has no limit on the duration.

The picture shows that the HIP4086 and HIP4086A three-phase drivers can be used to drive three-phase motors. Depending on the application, the switching speed of the bridge can be reduced by increasing the series resistance of the FET between the xHO output and the FET gate. Source Gate recommends installing a resistor on the low side FET to prevent if the bridge voltage is applied before VDD. Gate-source resistance on the high side If the gate-source resistance on the high side is low, the FET is usually not used. If using relatively small gate-source resistance high-side FETs, note that they will load the charge pump. The HIP4086 negates the charge pump keeping the high-side driver biased for long periods of time. An important operating condition that is often overlooked by the designer is the negative transient that occurs on the xHS pin when the high-side bridge FET is turned off. The absolute maximum allowed transient voltage on the xHS pin is -6V, but it is best to reduce the amplitude. This transient is the parasitic inductance of the low-side drain-source conductors of the printed circuit board. Even the parasitic inductance of the low-side FET contributes to this instant.

When the high-side bridge FET is turned off, due to the nature of the induction motor load, the current flowing into the high-side FET (blue) must quickly commutate the low-side FET (red). The impression of negative transient amplitude at the xHS node is (di/dt x L), where L is the total number of low-side FET drain-source parasitic inductance di/dt is the rate at which the high-side FET turns off. With increasing power levels for next-generation motor drives, clamping this transient is essential for proper operation of the HIP4086/A. There are several ways to reduce this amplitude briefly. If the bridge FET is turned off more slowly di/dt, the amplitude will be reduced, but at the expense of FET switching losses. Careful printed circuit board design will also reduce the value of parasitic inductance. However, these two solutions alone may not be enough. The figure illustrates a simple method of suppressing negative transients. Two series, fast PN junction, 1A diodes are connected between xHS and VSS as shown. It is important that the components be placed as close as possible to the pins of xHS and VSS to minimize the parasitic inductance of the current path. Two series diodes are needed because they are located in parallel with the body diode of the low-side FET. If only one diode was used for the clamp, it would conduct some of the current flowing in the negatively loaded low side FET. In severe cases as shown, a small value resistor in series with the xHS pin will further reduce the amplitude of the negative transient. Note that a similar positive-polarity transient occurs when the low-side FET is turned off. This is not a common problem because the xHS node is floated towards the bridge bias. The absolute maximum voltage rating of the XHS node needs to be observed when positive transients occur.

Printed Circuit Board General Layout Guidelines

The AC performance of the HIP4086/A is highly dependent on the PC board design. The following layout design recommendations follow these guidelines for best performance: Place the driver as close as possible to the drive power FET. Understand the flow of switching power supply current. Amplitude di/dt currents of high drive power FETs will cause significant voltage transients on the associated traces. by paralleling the source and return traces. Use flat surfaces where feasible; they are usually more efficient than parallel traces. Avoid paralleling signal lines with low-level, high-amplitude di/dt traces. High di/dt will cause current and, therefore, noise voltages in low level signal lines. Minimize impedance in low-level signal circuits where practical. The noise generated by magnetic induction on a 10kΩ resistor is 10 times greater than the noise on a 1kΩ resistor. Pay attention to the magnetic fields generated by the motors, transformers and inductors. Gaps in these magnetic structures are particularly detrimental to emitting flux. If there must be traces close to magnetic equipment, keep them parallel to the flux lines to minimize coupling. Using low inductance components, such as chip resistors, chip capacitors are recommended. Use decoupling capacitors to reduce parasitic effects of inductance in the VDD and GND leads.

To be effective, these capacitors must also have the shortest possible conductivity paths. If using vias, connect several parallel vias to reduce the inductance of the vias. It may be necessary to add resistance to suppress resonant parasitic circuits, especially those on xHO and xLO. If the external gate resistance is unacceptable, the layout must be improved to minimize lead inductance. Keep high-dv/dt nodes away from low-level circuits. Guard strips can be used to shunt dv/dt injection currents from sensitive circuits. This is especially true of the control circuit that sends the input signal to the HIP4086/A. Avoid signal ground plane dv/dt circuits at high amplitudes. This will inject di/dt current into the ground path of the signal. Perform power loss and voltage drop calculations for power traces. Many PCB/CAD programs have built-in trace resistance calculations. High-power components (power FETs, electrolytic capacitors, power resistors, etc.) will have internal parasitic inductances that cannot be eliminated. This must be done in printed circuit board layout and circuit design. If you simulate your circuit, consider including parasitic circuit components, especially parasitic lead inductance.