feature

High performance 24-bit Σ-∏ ADC; 115 dB dynamic range at 78 kHz output data rate; 109 dB dynamic range at 312 kHz output data rate; 312 kHz maximum fully filtered output word rate; pin-selectable oversampling rate (64 ×, 128×, 256 ×); low power mode; flexible SPI; fully differential modulator input; on-chip differential amplifier for signal buffering; on-chip reference buffer; full-band low-pass finite impulse response (FIR) filter; ultra Range alarm pin; digital gain correction register; power down mode; synchronization of multiple devices via SYNC pin; daisy chain.

application

Data Acquisition Systems; Vibration Analysis; Instrumentation.

General Instructions

The AD7764 is a high performance 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). It combines the performance of wide input bandwidth, high speed and 109dB dynamic range at 312kHz output data rate. The converter has excellent DC characteristics and is ideal for high-speed data acquisition of AC signals that require DC data.

Using the AD7764 simplifies the front-end antialiasing filtering requirements and greatly simplifies the design process. The AD7764 is available in 64×, 128×, and 256×. Additional features include an integrated buffer to drive the reference, and a fully differential amplifier to buffer and level shift the modulator input.

When the input signal is outside the acceptable range, the overrange alarm pin will display. The addition of internal gain and internal overrange registers make the AD7764 a compact, highly integrated data acquisition device that requires minimal peripheral components.

The AD7764 also offers a low-power mode that significantly reduces power consumption without reducing the output data rate or available input bandwidth.

The differential input is sampled by an analog modulator at speeds up to 40 MSPS. The modulator output is processed by a series of low pass filters. The external clock frequency applied to the AD7764 determines the sample rate, filter corner frequency, and output word rate.

The AD7764 device has a full-band onboard FIR filter. The full stopband attenuation of the filter is achieved at the Nyquist frequency. This feature provides increased protection against signals above the Nyquist frequency from being aliased back into the input signal bandwidth.

The reference voltage supplied to the AD7764 determines the input range. With a 4V reference, the analog input range is ±3.2768V differential, biased around a common mode of 2.048V. This common-mode biasing can be achieved using an on-chip differential amplifier, further reducing external signal conditioning requirements.

The AD7764 is available in a 28-lead TSSOP package and is specified over the industrial temperature range of -40°C to +85°C.

Typical performance characteristics

AV1=DV=2.5V, AV2=AV3=AV4=5V, V+=4.096V, MCLK amplitude=5V, T=25°C. Linear curve measured to 16-bit precision. Input signal is reduced to avoid modulator overload and digital clipping; in normal power mode, fast Fourier transforms (FFTs) of -0.5db tone are generated from 262144 samples. All other ffts are generated from 8192 samples.

the term

signal to noise ratio

The ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and DC. The signal-to-noise ratio is expressed in decibels (dB).

Total Harmonic Distortion (THD)

The ratio of the rms sum of the harmonics to the fundamental. For the AD7764, it is defined as:

where: V1 is the rms amplitude of the fundamental wave. V2, V3, V4, V5 and V6 are the second sixth harmonic.

Nonharmonic Spurious Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral components, excluding harmonics.

Dynamic Range

The ratio of the full-scale rms value to the rms noise measured with the input shorted. Dynamic range values are expressed in decibels.

Intermodulation Distortion

When the input consists of sine waves of two frequencies (fa and fb), any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2 , 3, etc. Intermodulation distortion terms refer to terms where neither m nor n equals 0. For example, second-order terms include (fa+fb) and (fa-fb), while third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

The AD7764 is tested using the CCIF standard, which uses two input frequencies near the top of the input bandwidth. In this case, the second-order term is usually at a distance from the original sine wave in frequency, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second- and third-order terms are specified separately. Intermodulation distortion is calculated according to the THD specification, where it is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental sum expressed in decibels.

Integral Nonlinearity (INL)

Maximum deviation from a straight line through the endpoints of the ADC transfer function.

Differential Nonlinearity (DNL)

The difference between the measured value and the ideal 1 LSB between any two adjacent codes in the ADC changes.

zero error

The difference between the ideal midscale input voltage (when the two inputs are shorted together) and the actual voltage that produces the midscale output code.

Zero error drift

The change in the actual zero error value due to a 1°C change in temperature. Expressed as a percentage of full scale at room temperature.

gain error

The first transition (from 100…000 to 100…001) should occur at nominally negative full scale above 1/2 LSB of the analog voltage. The last transition (from 011...110 to 011...111) should occur at an analog voltage 1 1/2 LSB below the rated full scale. Gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition and the difference between the ideal level.

Gain Error Drift

Change in actual gain error value due to a 1°C change in temperature. Expressed as a percentage of full scale at room temperature.

theory of operation

The AD7764 has an on-chip fully differential amplifier that feeds the sigma-delta modulator pins, an on-chip reference buffer, and an FIR filter block to perform the required digital filtering of the sigma-delta modulator output. Using this sigma-delta conversion technique, coupled with digital filtering, converts the analog input into an equivalent digital word.

Sigma-Delta Modulation and Digital Filtering

The input waveform applied to the modulator is sampled and the equivalent digital word is output to the digital filter at a rate equal to ICLK. By employing oversampling, the quantization noise spreads over a wide bandwidth from 0 to f. This means that the noise energy contained in the signal band of interest is reduced (see Figure 29). To further reduce quantization noise, high-order modulators are used to shape the noise spectrum so that most of the noise energy is shifted out of the signal band (see Figure 30).

The digital filtering following the modulator removes the large out-of-band quantization noise (see Figure 31), while also reducing the data rate at the filter input from f to f/64 at the filter output, depending on the decimation rate used or lower.

The AD7764 employs three FIR filters in series. By using different combinations of decimation rates, data can be obtained from the AD7764 at three data rates.

The first filter receives data from the modulator at ICLK MHz and decimates 4× at ICLK MHz to output the data at (ICLK/4) MHz. The second filter allows the decimation rate to be selected between 8× and 32×.

The third filter has a fixed decimation rate of 2×. Table 6 shows some characteristics of digital filtering, where ICLK=MCLK/2. The group delay of a filter is defined as the delay in the center of the impulse response, equal to the amount of computation plus the filter delay. The delay until valid data is available (the filter set status bit is set) is approximately twice the filter delay plus the computational delay. This is listed in Table 6 for the MCLK period.

AD7764 Antialiasing Protection

The decimation of the AD7764 and its counterparts in the AD776x family (ie AD7760, AD7762, AD7763, and AD7765) provides top-level antialiasing protection.

The decimation filter of the AD7764 has more than 115dB of attenuation across the entire stopband, ranging from the Nyquist frequency (that is, ODR/2) to ICLK–ODR/2 (where ODR is the output data rate). Starting the stop band at the Nyquist frequency prevents any signal components above Nyquist (and up to ICLK–ODR/2) from aliasing into the desired signal bandwidth.

Figure 32 shows the frequency response of the decimation filter when the AD7764 operates in decimation × 128 mode with 40MHz MCLK. Note that the first stopband frequency occurs at Nyquist. The frequency response of the filter and the selection of the decimation rate and the application of the MCLK frequency. In low-power mode, the modulator sample rate is MCLK/4. Taking the AD7764 as an example, in normal power and decimal × 128 mode, the first possible alias is the ICLK frequency minus the passband of the digital filter (see Figure 33).

AD7764 Input Structure

The AD7764 requires a 4.096 V input to the reference pin, V+, provided by a high precision reference such as the ADR444. Since the input to the device's sigma-delta modulator is fully differential, the effective differential reference range is 8.192 V.

As is inherent in sigma-delta modulators, only a subset of them can use the full reference. Using the AD7764, an 80% differential reference can be applied to the differential inputs of the modulator:

This means that a maximum of ±3.2768 VPP full scale can be applied to each of the AD7764 modulator inputs (pins 5 and 6), and the AD7764 input is -0.5 decibels (-0.5 decibels) below full scale. The AD7764 modulator input must have a common-mode input of 2.048 V.

Figure 34 shows the relative scale between the differential voltage applied to the modulator pins and the corresponding 24-bit double complement digital output.

On-chip differential amplifier

The AD7764 contains an on-board differential amplifier recommended for driving the modulator input pins. Pin 1, Pin 2, Pin 3, and Pin 4 on the AD7764 are the differential input and output pins of the amplifier. External components R, R, C, C, and R are placed around pins 1 to 6 to create the proposed configuration.

To achieve the specified performance, the differential amplifier should be configured as a first-order antialiasing filter, as shown in Figure 35, using the component values listed in Table 7. The inputs of the differential amplifier are then routed through a net of external components before being applied to the modulator inputs V- and V+ (pins 5 and 6). Taking the best value in the table as an example, produces 25db of attenuation at the first alias point of 19.6mhz.

The common-mode input range of each differential amplifier input (pins VA+ and VA-) is -0.5 V dc to 2.2 V dc. The constant output common-mode voltage of the amplifier is 2.048 V, which is V/2, the common-mode voltage (V+ and V-) required by the modulator input pins.

Figure 36 shows signal conditioning using the differential amplifier configuration detailed in Table 7 with an input signal of ±2.5V. The amplifiers in this example are biased around ground and scaled to provide ±3.168 V pp (–0.5 dBFS) on each 2.048 V common-mode modulator input.

To get the maximum performance from the AD7764, it is recommended to drive the ADC with differential signals. Figure 37 shows how a bipolar, single-ended signal biased at ground can be used to drive the AD7764 using an external op amp, such as the AD8021.

Modulator Input Structure

The AD7764 uses a double sampling front end, as shown in Figure 38. For simplicity, only the equivalent input circuit of V+ is shown. The equivalent circuit of V- is the same.

The SS1 and SS3 sampling switches are driven by ICLK, while the SS2 and SS4 sampling switches are driven by ICLK. When ICLK is high, the analog input voltage is connected to CS1. On the falling edge of ICLK, the SS1 and SS3 switches open and the analog input is sampled on CS1. Similarly, when ICLK is low, the analog input voltage is connected to CS2. On the rising edge of ICLK, the SS2 and SS4 switches open and the analog input is sampled on CS2.

The CPA, CPB1 and CPB2 capacitors represent parasitic capacitances including the junction capacitances associated with the MOS switches.

Direct drive modulator input

The AD7765 can be configured to disable the on-board differential amplifier, and the discrete amplifier can be used to directly drive the modulator. This allows the user to reduce power consumption.

To power down the on-board differential amplifier, the user issues a write to set the AMP shutdown bit in the control register to logic high (see Figure 39).

The AD7764 modulator inputs must have a common-mode voltage of 2.048 V and meet the amplitudes described in the AD7764 Input Structure section.

Figure 40 shows an example of a typical circuit driving the AD7764 for applications requiring excellent ac and dc performance. The AD8606 or AD8656 can be used to directly drive the AD7764 modulator input.

Best practice is to short the differential amplifier input to ground with typical input resistance and leave the typical feedback resistance.

AD7764 interface

read data

The AD7764 uses an SPI-compatible serial interface. The timing diagram in Figure 2 shows how the AD7764 transmits its con-version results.

The data read from the AD7764 is clocked using the serial clock output (SCO). The SCO frequency is half the frequency of the MCLK input to the AD7764.

The conversion result output on the serial data output (SDO) line consists of the frame synchronization output (FSO), which is sent logic low for 32 SCO cycles. Each bit of the new conversion result is recorded on the SDO line on rising SCO edges and is valid on falling SCO edges. The 32-bit result consists of 24 data bits, 5 status bits, and 3 zeros. The five status bits are listed in Table 9 and described in the following table.

(1) The FILTER-SETTLE bit indicates whether the data output from the AD7764 is valid. After resetting the device (using the reset pin) or clearing the digital filter (using the SYNC pin), the FILTER-SETTLE bit goes logic low, indicating that the FILTER's full settling time has not elapsed and the data is not yet valid. The FILTER-SETTLE bit will also go to zero when the part's input has asserted an out-of-range alarm.

(2) The OVR (overrange) bit is described in the Overrange Alerts section.

(3) When the AD7764 is operating in low power mode, the LPWR bit is set to logic high. See the Power Modes section for more details.

(4) The DEC_RATE 1 and DEC_RATE 0 bits indicate the decimation rate used. Table 10 is the truth table for the decimation rate bits.

Read status and other registers

The AD7764 has a gain correction register, an overrange register, and a read-only status register. To read the contents of these registers, the user must first write to the device's control register and set the bit corresponding to the register to be read. The next read operation outputs the contents of the selected register (on the SDO pin), not the conversion result.

To ensure that the next read cycle contains the contents of the written register, a write to this register must complete at least 8 × t before the falling edge of FSO, which indicates the start of the next read cycle. See Figure 4 for more details. The AD7764 Registers section provides more information on the relevant bits in the control registers.

Write to AD7764

A write operation to the AD7764 is shown in Figure 3. Serial write operations are synchronized with the SCO signal. Check the status of the frame sync input FSI on the falling edge of the SCO signal. If the FSI line is low, the first data bit on the Serial Data Input (SDI) line is latched on the next SCO falling edge.

The active edge of the FSI signal is set to occur when the SCO signal is high or low to allow the setup and hold times of the falling edge of the SCO to be met. The width of the FSI signal can be set from 1 to 32 SCO cycle widths. The second or subsequent falling edge that occurs before 32 SCO cycles have elapsed is ignored.

Figure 3 details the format of the serial data written to the AD7764 through the SDI pin. Write operations require 32 bits. The first 16 bits are used to select the register address of the data to be read. The second 16 bits contain the data for the selected register.

The AD7764 is allowed to be written to at any time, even while the conversion result is being read. Note that after writing to the device, no valid data will be output until the set time of the filter has elapsed. At this point, the FILTER-SETTLE status bit is asserted to indicate that the filter is set and valid data is available at the output.

AD7764 Features

Synchronize

The sync input of the AD7764 provides a sync function that allows the user to begin collecting samples of the analog front end input from a known point in time.

The synchronization feature allows operation of multiple AD7764 devices from the same master clock using a common sync and reset signal so that each ADC updates its output registers simultaneously. Note that all devices being synchronized must operate in the same power mode and at the same decimation rate.

For systems with multiple AD7764s, connect the common MCLK, sync, and reset signals to each AD7764.

The AD7764 sync pin is polled by the falling edge of MCLK. The AD7764 device enters the sync state when the sync input signal is detected logic low on the falling edge of MCLK. At this point, the digital filter sequencer is reset to 0. The filter remains in reset (sync mode) until the first MCLK falling edge senses a sync logic high where possible, ensures that all transitions that are synced occur in sync with the rising edge of MCLK (i.e., as far away as possible from the falling edge of MCLK or decision edge). Otherwise, follow the timing specified in Figure 41, which does not include the synchronous rising edge that occurs in the 10ns window around the falling edge of MCLK.

Hold synchronous logic low for at least four MCLK cycles. When the falling edge of MCLK detects that sync has returned to logic high, the AD7764 filter begins collecting input samples at the same time. The falling edge of FSO is also synchronized, allowing conversion data to be output simultaneously.

After synchronization, the digital filter needs time to stabilize before valid data can be read from the AD7764. The user knows that there is a valid data result on the SDO line by checking the FILTER-SETTLE status bits (see D7 in Table 9) that are output at each conversion. The time from the rising edge of SYNC to the assertion of the FILTER-SETTLE bit depends on the filter configuration used. See the Theory of Operation section and the values listed in Table 6 for details on calculating the time until the filter settles the asset. Note that the FILTER_SETTLE bit is designed to be an inverted flag to indicate when the converted data output is valid.

Out of range alert

The AD7764 provides overrange functionality on the pins and status bit outputs. When the voltage applied to the AD7764 modulator input pin exceeds the limit set in the overrange register, the overrange alarm indicates that the applied voltage is close to the level at which the modulator will overrange. To set this limit, the user must program the registers. The default overrange limit is set to 80% of the V voltage (see AD7764 Registers section).

The overrange pin outputs a logic high to alert the user that the modulator has sampled an input voltage whose magnitude is greater than the overrange limit set in the overrange register. The overrange pin is set to logic high when the modulator samples an input above the overrange limit. The overrange pin returns to zero when the input returns below the limit. The overrange pin is updated after the first FIR filter stage. Its output varies at ICLK/4 frequency.

During a data conversion, the OVR status bit is output as Bit D6 on SDO and can be checked in the AD7764 status register. This bit is not as dynamic as the overrange pin output. It is updated each time the conversion result is output; that is, the bits vary with the output data rate. The OVR bit is set to logic high if, during sampling for a particular conversion result output, the modulator samples a voltage input that exceeds the overrange limit.

The output points from FIR Filter 1 in Figure 42 are not plotted to scale relative to the output data rate points. The FIR Filter 1 output is updated 16×32× or 64× faster than the output data rate depending on the decimation rate in the operation.

power mode

low power mode

During power-up, the AD7764 operates in normal power mode by default. No register writes are required. The AD7764 also offers a low power mode. To operate the device in low power mode, the user sets the LPWR bit in the control register to logic high (see Figure 43). Operating the AD7764 in low power modes does not affect the output data rate or available bandwidth.

reset/PWRDWN mode

The AD7764 has a reset/PWRDWN pin. Holding the input to this pin logic low puts the AD7764 in power-down mode. All internal circuits are reset. After the device is initially powered up, a reset pulse is applied to the AD7764. The AD7764 reset pin is polled by the rising edge of MCLK. The AD7764 device enters the reset state when the reset input signal is detected as a logic low by rising MCLK. The AD7764 comes out of reset on the first MCLK rising edge that feels reset to a logic high.

It is a best practice to ensure that all transitions of reset occur in synchronization with the falling edge of MCLK; otherwise, follow the timing requirements shown in Figure 44.

Reset should be held logic low for at least one MCLK cycle for a valid reset to occur.

Using a sync pulse in situations where multiple AD7764 devices are synchronizing, in daisy-chaining multiple AD7764 devices, must be used in addition to the normal sync and MCLK signals.

decimation rate PIN

The decimation rate of the AD7764 is selected using the DEC_rate pin. Table 11 shows the required voltage input settings for the three decimation rates.

Daisy chain

Daisy chaining allows many devices to use the same digital interface line. This feature is especially useful for reducing component count and wiring connections, such as in isolated multi-converter applications or for systems with limited interface capacity. Data readback is similar to a shift register. When daisy-chaining is used, the chains must operate at a common power mode and a common extraction rate.

The block diagram in Figure 45 shows how to connect the devices for a daisy-chain function. Figure 45 shows four AD7764 devices daisy-chained together with the application's common MCLK signal. Only works in 128× or 256× mode.

Read data in daisy-chain mode

Referring to Figure 45, note that the SDO line of the AD7764(A) provides the output data from the AD7764 converter chain. Also, note that for the last device in the chain, the AD7764 (D), the SDI pin is grounded. All devices in the chain must use a common MCLK and sync signal. To enable the daisy-chain conversion process, apply a common sync pulse to all devices (see the sync section).

When the sync pulse is applied to all devices, the filter positioning time must elapse before asserting filter positioning, which represents valid transition data at the output of the device chain. As shown in Figure 46, the first conversion result is output from the device labeled AD7764(A). This 32-bit conversion result is then followed by conversion results from the AD7764(B), AD7764(C), and AD7764(D) devices, all output MSB first. The signal output from the daisy chain is the SDO pin from the AD7764(A) and the FSO signal from the first device in the chain, the AD7764(A).

The falling edge of FSO signals the MSB of the output of the first conversion in the chain. FSO remains logic low for the 32 SCO clock cycles required to output the AD7764(A) result, then goes logic during the output of the conversion result from the AD7764(B), AD7764(C), and AD7764(D device) high level.

The maximum number of devices that can be daisy-chained depends on the decimation rate chosen. The maximum number of devices that can be daisy-chained is calculated by simply dividing the chosen decimation rate by 32 (calculating the number of bits that must be recorded per transition). Table 12 provides the maximum number of chained devices per decimation rate.

Write data in daisy-chain mode

Writing to AD7764 devices in daisy-chain mode is similar to writing to a single device. Serial write operations are synchronized with the SCO signal. Check the status of the frame sync input FSI on the falling edge of the SCO signal. If the FSI line is low, the first data bit of serial data on the SDI line is latched on the next falling edge of SCO.

Writing data to the AD7764 in daisy-chain mode has the same timing structure as writing to a single device (see Figure 3). The difference between writing to a single device and writing to multiple daisy-chained devices is the enhancement of the -FSI signal. The number of devices in the daisy chain determines the period for which the FSI signal must remain logic low. To write to n devices in a daisy chain, the falling edge of FSI and the rising edge of FSI must be between 32×n-1 and 32×n SCO cycles. For example, if writing data to three AD7764 devices in daisy-chain mode, FSI is logic low between 32×3-1 and 32×3 SCO pulses. This means that the rising edge of the FSI must appear between the 64 and 96 SCO periods.

The AD7764 device can be written to at any time. The edge of the falling FSI covers all attempts to read data from the SDO pin. In the case of a daisy chain, the FSI signal remains logic low for more than 32 SCO cycles to indicate to the AD7764 device that there are more devices in the chain. This means that the AD7764 directs the data input on the SDI pin to its SDO pin. This ensures that the data is passed to the next device in the chain.

Timing AD7764

The AD7764 requires an external low jitter clock source. This signal is applied to the MCLK pin. The internal clock signal (ICLK) is derived from the MCLK input signal. ICLK controls the internal operation of the AD7764. The maximum ICLK frequency is 20 MHz. To generate ICLK, ICLK = MCLK/2, an ICLK frequency of 12.288mhz can be used for an output data rate equal to that used in an audio system. As shown in Table 6, output data rates of 96 kHz and 48 kHz can be achieved using this ICLK frequency.

MCLK Jitter Requirements

MCLK jitter requirements depend on many factors, as follows:

Where: OSR=oversampling rate=fICLK/ODR. maximum input frequency. SNR (dB) = target SNR.

Example 1, this example can be obtained from Table 6, where: ODR = 312.5 kHz. fICLK = 20 MHz. fIN (max) = 156.25 kHz. Signal-to-noise ratio = 104 dB.

This is the maximum allowable clock jitter for a full-scale, 156.25 kHz input tone, with a given ICLK and output data rate.

Example 2, the second example can also be obtained from Table 6, where: ODR = 48 kHz. fICLK = 12.288 MHz. fIN (max) = 19.2 kHz. SNR = 109 dB.

The input amplitude also has an effect on these jitter numbers. For example, if the input level is 3db below full scale, the allowable jitter is increased by a factor of √2, increasing the first example to 144.65ps rms. This happens when the maximum slew rate is reduced by a reduction in amplitude.

Figures 49 and 50 illustrate this, showing the maximum slew rate for sine waves of the same frequency but with different amplitudes.

Decoupling and Layout Information

Power decoupling

Decoupling of the power supplies applied to the AD7764 is important to achieve maximum performance. Each power pin must be disconnected from the correct ground pin with a 100 nF, 0603 case size capacitor.

Take special care to separate pin 7 (AV2) directly from the nearest ground pin (pin 8). The digital ground pin AGND2 (pin 20) is directly connected to ground. Also, connect REFGND (pin 26) directly to ground.

The DV (pin 17) and AV3 (pin 28) supplies should be disconnected from the ground plane at a point away from the device. It is recommended that the power connected to the following power pins be disconnected from the star ground connected to pin 23 (AGND1) via a 0603 size 100 nF capacitor: V+ (Pin 27); AV4 (Pin 25); AV1 ( pin 24); AV2 (pin 21).

Figure 51 shows the layout decoupling scheme for these supplies connected to the right side of the AD7764. Note the star point ground created at pin 23.

Reference voltage filtering

A low noise reference source, such as the ADR444 or ADR434 (4.096 V), is suitable for use with the AD7764. The reference voltage provided to the AD7764 should be decoupled and filtered as shown in Figure 52.

The recommended solution for the voltage reference supply is a 200Ω series resistor to a 100µF tantalum capacitor, followed by a 10 nF decoupling capacitor very close to the V+ pin.

Differential Amplifier Components

Table 7 details the recommended components around the on-chip differential amplifier. Matching the components on both sides of the differential amplifier is important to minimize signal distortion applied to the amplifier. These parts require a tolerance of 0.1% or higher. The symmetrical routing of the rails on both sides of the differential amplifier also contributes to this performance. Figure 53 shows a typical layout of components around a difference amplifier. Note that the traces for the two differential paths are as symmetrical as possible, and the feedback resistors and capacitors are placed on the bottom of the PCB for easiest routing.

Layout Considerations

While using the right components is critical for optimal performance, the right layout is equally important. The AD7764 product page on the AD7764 contains the Gerber files for the AD7764 evaluation board. The Gerber file should be used as a reference when designing any system using the AD7764.

The use of ground planes should be carefully considered. To ensure that the return flow through the decoupling capacitor goes to the correct ground pin, the ground side of the capacitor should be as close as possible to the ground pin associated with that power supply, as recommended in the "Power Supply Decoupling" section.

Using AD7764

Steps 1 through 5 detail the sequence for powering up and using the AD7764.

1. Power on the device.

2. Apply the MCLK signal.

3. Use a low reset for at least one MCLK cycle, preferably synchronous to a falling MCLK edge. If you want to sync multiple parts, apply a common reset to all devices.

4. After releasing reset, wait at least two MCLK cycles.

5. If multiple sections are being synchronized, a sync pulse must be applied to these sections, preferably in synchronization with the rising edge of MCLK. In the case where the devices are not in sync, no sync pulse is required; a logic high signal should simply be applied to the sync pins. When a sync pulse is applied,

(1) Sending a sync pulse to the device must not occur at the same time as writing a sync pulse to the device.

(2) Ensure that the sync pulse is low for at least four MCLK cycles.

Data can then be read from the device using the default gain and overrange thresholds. However, the converted data read is invalid until the set time of the filter has elapsed. Once this happens, the FILTER-SETTLE status bit is set, indicating that the data is valid.

The gain and overrange threshold values can be written or read from the corresponding registers at this stage.

Bias Resistor Selection

The AD7764 requires a resistor connected between the R and AGNDx pins. Resistor values should be chosen to provide 25 microamps of current through the resistor to ground. For a 4.096 V reference, the correct resistor value is 160 kΩ.

AD7764 registers

The AD7764 has many user programmable registers. The control registers are used to set the functions of the on-chip buffers and differential amplifiers, and provide the option to turn off the AD7764. There are also digital gain and overrange threshold registers. Writing to these registers consists of writing the register address followed by a 16-bit data word. This section provides register addresses, individual bit details and default values.

Gain Register Address 0x0004

Not bitmapped, default 0xA000

The gain registers are scaled so that 0x8000 corresponds to a gain of 1.0. The default value of this register is 1.25 (0xA000). This produces a full-scale digital output when the input is 80% of V+, with a maximum analog input range of ±80% of V+PP.

Overrange register address 0x0005

Not bitmapped, default 0xCCCC

The overrange register value is compared to the output of the first decimation filter to obtain an overload indication with minimal propagation delay. This is before any gain scaling. The default value is 0xccCC, which corresponds to 80% of V+ (maximum allowed analog input voltage). Assuming V+ = 4.096 V, the bit is set when the input voltage exceeds the differential by approximately 6.55 VPP. The overrange bit is set immediately if the analog input voltage exceeds 100% of V+ for more than four consecutive samples at the modulator rate.

Dimensions