Low-side gate driver ICs are specialized amplifiers commonly used in power supply designs that switch ground-referenced MOSFETs and IGBTs based on an input signal from a PWM controller. For low power converters below 100 ~ 200W, these drivers can be successfully integrated into PWM controllers to reduce component count, as long as certain conditions are met. These conditions include: MOSFET switching speed is fast enough to keep switching losses within acceptable limits; noise from higher drive current pulses does not interfere with control functions; and on-board heat dissipation from the PWM IC is manageable. On the other hand, in higher power converters, separate driver ICs are typically employed to provide more drive power or to manage noise and heat dissipation more easily. Additionally, power efficiency can be improved by using lower supply voltages for the controller and higher voltages to drive the power switches, and gate driver ICs do this level shifting well.

To save cost, discrete components are sometimes used to build simple gate drive circuits, which is feasible when a driver IC with advanced functionality and performance is not required. However, this approach has many limitations. For example, if the output stage of an NPN/PNP emitter follower is chosen, the design of the bias circuit must be careful, and the output voltage swing will be reduced when the output saturation voltage of the transistor is high to the fast switching voltage. If a PMOS/NMOS inverter is used instead at the output, the control logic must accommodate this logic transition, and there is usually a partial breakdown when the driver changes state. With either technique, such a low gain stage requires input fast edges to produce fast switching, requires more circuitry to perform functions such as voltage level switching, and the increased component count has a negative impact on space, assembly time and reliability has adverse effects.

Gate driver ICs can solve most of the above problems. They integrate features such as enable and undervoltage lockout (UVLO) to easily control power switches under the toughest operating conditions such as startup, shutdown and fault. Very small logic gates can easily drive high-impedance inputs, and because the driver IC contains high-gain circuitry with positive feedback, the output always switches quickly whenever the input voltage exceeds the threshold. When the IC needs to be designed to prevent the threshold voltage from fluctuating with overheating, it is easy to insert a fixed delay by adding a simple RC circuit to the input.

Drive Size Decisions

Two common types of switches that use low-side drivers are clamp-inductive switches featuring the primary-side switching characteristics of a hard-switching topology, and synchronous rectification. Criteria for determining drive size vary, so here's a review.

Figure 1 shows the ideal turn-on waveform of a clamped inductive switch, characterized by no overlap between the rise in drain-source current and the fall in drain-source voltage. This yields worst-case switching losses, usually expressed as the average power dissipation over the entire converter switching time TS, even though the actual power dissipation only occurs at t2 and t3 in the figure.

The length of (t2+t3) depends on the average gate drive current IG and the amount of charge necessary for the MOSFET gate to traverse these time intervals, both of which can be found in the MOSFET specifications or read from the total gate charge curve .

The turn-off waveform is the mirror image of Figure 1, and a similar method can be used to calculate the turn-off switching loss and substitute it into Equation (1) to obtain the total switching loss of the power switch. It is evident from these equations that the switching losses are inversely proportional to the gate drive current during the loss time interval. For clamp-inductive switching, switching losses are the primary metric for sizing the gate driver. In fact, when its output voltage is near the middle of its operating range, the most important driver characteristic is its output current

Using the steady-state current at the mid-point of the output voltage range as the rated current, Table 1 is a guideline showing how quickly a unit size driver can provide or remove a certain amount of gate charge when there is no external resistor in the driver path. This table is calculated by equation (2), but multiplied by an empirical coefficient of 1.5 to account for the non-idealization of laboratory test conditions. However, this factor is still too conservative because the internal gate impedance of the power switch can slow down the switch even when the series gate resistor is not used. When the gate driver is used with a synchronous rectifier (SR), the sizing criteria are completely different, and since the body diode conducts before and after the MOSFET channel conducts, the switching losses are negligible. In this case, the required driver current depends on timing and prevention of turn-on due to dv/dt.

To prevent shoot-through from causing unnecessary power dissipation, the SR must be turned off completely before applying the voltage, typically by turning on one or more primary switches. To ensure this condition is met while keeping the SR on for as long as possible to maximize efficiency, it is necessary to know how long it takes to turn off the SR. From the MOSFET model in Figure 2, the off-time can be calculated.

Here, CGS=CISS-CRSS is the linear gate-source capacitance of the MOSFET, and CGD_SR is the low-voltage nonlinear gate-drain capacitance or "Miller" capacitance CGD=CRSS. The latter choice preferably corresponds to the midpoint of the voltage swing during the SR turn-off period, VDD/2. This value can be read from the CRSS versus voltage curve (if provided), or it can be calculated from the CRSS_SPEC value given in the manual for some higher voltage VDS_SPEC as follows:

Once the SR is completely turned off, the main switch in the power converter can be turned on, causing the drain-source voltage of the SR to rise rapidly. Figure 2 shows this, where the capacitive divider formed by CGD and CGS causes the internal drain voltage to increase—the MOSFET is briefly reverse-conducting—unless the driver draws enough current to keep the internal gate node at the MOSFET’s threshold voltage under. This is often the main criterion for sizing SR drives. At the beginning of the drain voltage rise, CGD is at its maximum, and the required sink current is approximately:

If a larger driver cannot be used and it has been placed close to the SR, the last resort to avoid turn-on due to dv/dt is to reduce dv/dt by slowing the turn-on of the main switch, but this also increases Switching losses of the main switch.

Feature selection

When choosing a driver IC, in addition to the current rating, designers are also faced with the problem of function selection, that is, the choice of input logic and configuration, input thresholds and packaging. For single-channel drivers, input forms include options such as inverting, non-inverting, dual input, and enable input. Correctly setting the polarity of each MOSFET gate control signal usually requires a choice between inverting and non-inverting, sometimes different for different switches when driven by a single control output. If both polarities are required, the dual-input driver requires fewer different components and can be configured either way because it has one inverting input and one non-inverting input. The enable input is useful if additional control is required when the MOSFET switches, such as setting a higher UVLO threshold or disabling the SR for one second during startup.

Drivers can have TTL or CMOS input levels. The TTL "low" input is defined as below 0.8V and the "high" input is defined as above 2.0V, independent of the power supply, so the TTL threshold is approximately constant and always stays between these two upper and lower limits. Conversely, CMOS input thresholds are approximately 40% and 60% of the supply voltage. TTL thresholds are more common and are especially useful when the input signal (such as from a low voltage PWM controller) has a low amplitude. However, CMOS has better noise tolerance and is therefore the first choice for noisy environments. And with CMOS, the RC delay can be set more precisely because its threshold is closer to half the supply voltage. Temperature stability of input thresholds and propagation delays is also important when precise timing is required.

Compensation element

When designing with driver ICs, two compensation components are important: bypass capacitors and series gate resistors. Since the driver produces short current pulses, a very low impedance supply is required to provide maximum current, which is usually achieved by placing a pair of bypass capacitors in close proximity to the driver, and the driver itself should be placed as close to the power switch as possible to minimize this Stray inductance of a current loop. This larger capacitor is generally an electrolytic capacitor or another capacitor with a lower ESR value, and its capacitance value is 2 to 10 times the effective load capacitance, which can be obtained by using the total gate charge by the following formula:

Second, ceramic bypass capacitors are typically one-tenth of this value. When using the same voltage source to power sensitive control circuits, it is a good practice to connect a resistor of several ohms in series with the power supply line to isolate the driver part from the control part

When driving a synchronous rectifier, the series gate resistance between the driver and the power switch is often ignored, but such a resistor of 2 to 20 ohms is often used in practice for three reasons: first, it suppresses the power switch gate capacitance and The ringing current between the gate drive loop leakage inductance, as shown in Figure 3, because excessive ringing current increases EMI and increases losses due to fast switching. Second, the switching speed can be slowed down, thereby reducing EMI, but at the cost of higher switching losses. A third possible reason is that the use of a series gate drive resistor transfers the gate drive losses of the driver to the external resistor while the total gate drive losses remain the same.

For driver ICs with well-controlled input thresholds, a fixed delay can be inserted in the control path using a series resistor plus a small ground capacitance at the driver input. As shown in Figure 4, with the addition of a gate drive transformer and several other components, the low-side driver can also be used to drive the high-side (floating) switch as an alternative to a high-voltage driver IC. The main reason for this is to cross the isolation boundary to reduce the propagation delay and achieve a more robust driver circuit.

thermal design

Since the power dissipation of the driver IC is quite significant, thermal design issues should be concerned. This is a two-step process: first estimate the power dissipation of the driver, then calculate the junction temperature to ensure it is within design constraints. For the simple gate drive circuit discussed here (controlled drive and non-resonant), the total gate drive losses associated with turning on/off the power MOSFET or IGBT per cycle can be derived from the total gate charge curve given in the switch's data sheet , that is, read the total gate charge Qg corresponding to the selected gate drive voltage VDD, and then calculate it as follows:

This power dissipation is independent of the value of the series gate drive resistor, but affects the power dissipated by the driver IC compared to other series resistors in the drive circuit. In fact, the proportion of driver IC power dissipation is exactly the ratio of its effective output impedance to the sum of all impedances in the drive loop, which differs during turn-on and turn-off. To do the calculation, the easiest way to estimate the effective output impedance of the driver is to divide the output clamped current at half the supply voltage by the steady-state source or half the supply voltage. Other loop resistances that should be factored in are the external and internal series gate resistors of the switch, and the ESR of the bulk bypass capacitors. Because some of these resistances cannot be accurately known, the total gate drive power consumption obtained according to (7) can be used as the upper limit of the power consumption of the driver IC, or the calculated value can use part of the empirical value.

Once the power dissipation of the driver IC is determined, whatever thermal parameters provided in the data sheet should be used to estimate the maximum junction temperature. Junction-to-loop thermal resistance θJA is the most commonly used parameter, but unfortunately it is only accurate in certain specified thermal designs, such as PCB construction, heat dissipation, and airflow. In low airflow without a top heatsink, most of the power dissipation is concentrated in the PCB. At this time, if the thermal resistance from the junction to the pin or the junction to the circuit board is given, and if the design limits the maximum operating temperature of the PCB, assuming that the pin temperature is equal to the maximum board temperature, the upper limit of the operating junction temperature can be obtained:

If the junction temperature is too high, re-select to improve the estimate, provide cooler or select a lower-impedance driver. For drive suppliers to get better results (and some thermal parameters from the data sheet), a finite element analysis of the package and thermal environment is a good way to go.