feature

2-channel 256 -position potentiometer; end-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ; compact 10-lead MSOP (3 mm x 4.9 mm) package; fast settling time: typically tS = 5 microns at power up seconds; full read/write of wiper registers; power on preset to midscale; factory replaces microcontroller with computer software; programming application; single supply: 2.7 V to 5.5 V; low temperature coefficient: 35ppm/°C; low power consumption: IDD = 6µA max; wide operating temperature: –40°C to +125°C; evaluation board available; suitable for automotive applications.

application

System calibration; electronic level setup; mechanical trimmer replacement in new designs; permanent factory PCB setup; sensor adjustments for pressure, temperature, position, chemical and optical sensors; RF amplifier biasing; automotive electronics tuning; gain control and biasing shift adjustment.

General Instructions

The AD5162 provides a compact 3mm x 4.9mm package solution for dual 256 position adjustment applications. The unit performs the same electronic adjustment function as a 3-terminal mechanical potentiometer. Available in four end-to-end resistance values (2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ), this low temperature coefficient device is ideal for high precision and stable variable resistance adjustment. The wiper settings can be controlled via the SPI digital interface. The resistance across the wiper and the fixed resistor varies linearly with the digital code transmitted into the RDAC latch.

Operating from a 2.7 volt to 5.5 volt supply, it consumes less than 6 microamps, allowing the AD5162 to be used in portable battery-operated applications.

For applications that program the AD5162 at the factory, Analog Devices provides device programming software that runs on Windows® NT/2000/XP operating systems. This software effectively replaces the need for an external SPI controller, improving the system's time-to-market. AD5162 evaluation kits and software are available. The kit includes cables and manual.

Absolute Maximum Ratings

Stresses listed above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions described in the operating section of this specification or any other conditions above is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Typical performance characteristics

test circuit

Figures 27 through 32 illustrate the test circuits that define the test conditions used in the product specification sheets (see Table 1 and Table 2).

theory of operation

The AD5162 is a 256-bit digitally controlled variable resistor (VR) device. A built-in power-up preset places the wipers at mid-scale when powered up, which simplifies recovery from fault conditions at power-up.

for variable resistors and

Voltage

Rheostat operation

The nominal resistance of the RDAC between Terminal A and Terminal B is 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal resistance (R) of VR has 256 contact points, which are contacted by the wiper terminal and the B terminal. The 8-bit data in the RDAC latch is decoded to select one of 256 possible settings.

Assuming a 10 kΩ part is used, the first wiper connection for data 0x00 starts at the B terminal. Since there is a wiper contact resistance of 50Ω, this connection creates a minimum resistance of 100Ω (2 x 50Ω) between terminals W and B. The second connection is the first tap point, corresponding to 139Ω for data 0x01 (R=R/256+2×R=39Ω+2×50Ω). The third connection is the next tap point, representing 178Ω for data 0x02 (2×39Ω+2×50Ω), and so on. For each additional LSB data value, the wiper moves up the resistor ladder until the last tap point reaches 10100Ω (R+2×R).

The general formula for determining the digitally programmed output resistance between W and B is:

where: D is loaded in the 8-bit RDAC register. RAB is end-to-end resistance. RW is powered by an internal switch.

In summary, if RAB is 10 kΩ and the A terminal is open circuited, the output resistance RWB latches the code according to the RDAC, as shown in Table 6.

Note that there is a finite wiper resistance of 100Ω at zero-scale conditions. It should be noted that in this state, the current between W and B is limited to a maximum pulse current of no more than 20 mA. Failure to do so may result in degradation or damage to the internal switch contacts.

Similar to the mechanical potentiometer, the RDAC resistor between wiper W and terminal A also produces a digitally controlled complementary resistor R. When using these terminals, the B terminal can be opened. Setting the resistance value of R starts at the maximum value of the resistance and decreases as the value of the data loaded in the latch increases. The general equation for this operation is:

When R is 10 kΩ and the B terminal is open, the output resistance R is set according to the RDAC latch code, as shown in Table 7.

Typical equipment-to-equipment matching is process batch dependent and can vary by as much as ±30%. Since the resistive element is processed with thin film technology, R has a very low temperature coefficient of 35ppm/°C as a function of temperature.

Program the Potentiometer Divider

Voltage output operation

A digital potentiometer easily creates a voltage divider at wiper to B and wiper to a proportional to the input voltage at a to B. Unlike the polarity of V to GND, which must be positive, the voltages from a to B, W to a, and W to B can be of any polarity.

If the effect of the wiper resistance approximation is ignored, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at wiper B that starts at 0 V and is less than 1 LSB of 5 V. The voltage of each LSB is equal to the voltage applied to the A and B terminals divided by the 256 positions of the potentiometer divider. The general equation that defines the V output voltage relative to ground for any effective input voltage applied to Terminal A and Terminal B is:

A more precise calculation includes the effect of the wiper resistance V:

The operation of the digital potentiometer in voltage divider mode allows for more precise operation when the temperature is too high. Unlike the rheostat mode, the output voltage is mainly determined by the ratio of the internal resistances R and R, not the absolute value. Therefore, the temperature drift was reduced to 15ppm/°C.

ESD protection

All digital inputs have a series of input resistance protection and parallel Zener ESD structures as shown in Figure 36 and Figure 37. This applies to the SDI, CLK and CS digital input pins.

Terminal voltage operating range

AD5162 The V and GND supplies define the boundary conditions for proper operation of the 3-terminal digital potentiometer. Supply signals above V or GND on the A, B, and W terminals are clamped by internal forward-biased diodes (see Figure 38).

power-on sequence

Since the ESD protection diodes limit the voltage compliance at the A, B, and W terminals (see Figure 38), it is important to power V/GND before applying voltage to the A, B, and W terminals; otherwise, the diodes are positive biased, allowing V to inadvertently energize and potentially affect the rest of the user circuit. The ideal power-up sequence is as follows: GND, V, digital input, then V, V, V. The relative order of V, V, V, and the digital inputs does not matter as long as power is applied after V/GND.

Layout and Power Bypass

A compact, minimal lead length layout design is best. Wires to the input should be as direct as possible with minimal wire length. The ground path should have low resistance and low inductance.

Also, for best stability, it is a good practice to bypass the power supply with a high quality capacitor. A 0.01µF to 0.1µF chip or chip ceramic capacitor should be used to bypass the device's power supply lines. A low ESR 1µF to 10µF tantalum or electrolytic capacitor should also be used at the power supply to minimize any transients and low frequency ripple (see Figure 39). Also, note that the digital ground should be remotely connected to a point on the analog ground to minimize ground bounce.

Maintains constant deviation of resistance settings

For users who need non-volatile but cannot justify the additional cost of EEMEM, the AD5162 can maintain the wiper setting by maintaining a constant bias voltage and is considered a low-cost alternative. The AD5162 is designed for low power applications, enabling low power consumption even in battery operating systems. The graph in Figure 40 shows the power consumption of a 3.4V, 450mAhr Li-Ion cell phone battery connected to the AD5162. Measurements over time show that the device draws about 1.3 μA with negligible power consumption. Over 30 days, the battery was less than 2% charged, most of which was due to leakage currents inherent in the battery itself.

This shows that continuously biasing a potentiometer can be a practical approach. Most portable devices do not require battery removal for charging. Although the AD5162's resistor setting is lost when the battery needs to be replaced, such events are fairly infrequent, so the lower cost and small size offered by the AD5162 justify this inconvenience. If total power is lost, the user should be provided with a means to adjust the settings accordingly.

Evaluation Committee

The evaluation board and all necessary software can be used to program the AD5162 from any PC running Windows® 98/2000/XP. As shown in Figure 41, the GUI is simple and easy to use. More detailed information can be found in the user manual, which is provided with the board.

The AD5162 starts at midscale after power-up. To increase or decrease resistance, simply move the scroll bar on the left side of the software window (see Figure 41). To write a specific value, use the SDI write bit control (click to run) the bit pattern in the upper part of the box, then click to run. The format of writing data to the device is shown in Table 8.

SPI interface

SPI compatible 3-wire serial bus

The AD5162 contains a 3-wire, SPI-compatible digital interface (SDI, CS, and CLK). The 9-bit serial word MSB must be loaded first. The format of the words is shown in Table 8.

The positive edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work fine. If a mechanical switch is used for product evaluation, it should be by trigger or other suitable method. When CS is low, the clock loads data into the serial register on each positive clock edge (see Figure 42).

The data setup and data hold times in Table 3 determine the effective timing requirements. The AD5162 uses a 9-bit serial input data register word transferred to the internal RDAC to register when the CS line returns logic high. The extra MSB bits are ignored.

AD5162 Outline Dimensions