In the high-speed design process, stack-up design and impedance calculation are the first steps in the long march. The impedance calculation method is very mature, so the difference between different software calculations is very small. This article uses Si9000 as an example.

The calculation of impedance is relatively cumbersome, but we can summarize some empirical values to help improve calculation efficiency. For the commonly used FR4, 50ohm microstrip line, the line width is generally equal to 2 times the thickness of the dielectric; for 50ohm stripline, the line width is equal to one-half of the total thickness of the dielectric between the two planes, which can help us quickly lock the line width range, note that the calculated line width is generally smaller than this value.

In addition to improving computational efficiency, we also need to improve computational accuracy. Do you often encounter inconsistencies between the impedance calculated by yourself and the calculation by the board factory? Some people will say that this has nothing to do with it, and let the board factory adjust it directly. But will there be a situation where the board factory can't adjust and let you relax the impedance control? It is better to make a good product or to have everything under your own control.

The following points are put forward for your reference when designing the stack to calculate the impedance:

1, the line width would rather be wide, not thin. What does this mean? Because we know that there is a thin limit in the process, and there is no limit to the width. If the line width is narrowed in order to adjust the impedance and the limit is reached, it will be troublesome, either increase the cost or relax the impedance control. Therefore, the relatively wide range in the calculation means that the target impedance is slightly lower. For example, the single-line impedance is 50ohm, we can calculate it to 49ohm, and try not to calculate it to 51ohm.

2. There is a trend as a whole. There may be multiple impedance control targets in our design, so the overall size is too large or too small, not 100ohm is too large, and 90ohm is too small.

3. Consider the residual copper rate and the amount of glue flowing. When one or both sides of the prepreg are etched lines, the glue will fill the etched gap during the lamination process, so that the glue thickness time between the two layers will be reduced, the smaller the residual copper rate, the more filling, and the more the rest will be. few. So if the thickness of the prepreg you need between two layers is 5mil, you should choose a thicker prepreg according to the residual copper rate.

4. Specify the glass cloth and glue content. Engineers who have read the sheet datasheet know that the dielectric coefficients of different glass cloths and prepregs or core boards with different glue contents are different. Even the same height may be the difference between 3.5 and 4. This difference can cause a single line. Impedance changes around 3ohm. In addition, the glass fiber effect is closely related to the size of the glass cloth window. If you are designing at 10Gbps or higher, and your stackup does not specify a material, the board factory uses a single sheet of 1080 material, then signal integrity may occur. question.

Of course, the calculation of the residual copper rate and the amount of glue flow is not accurate. The dielectric coefficient of the new material is sometimes inconsistent with the nominal value, and some glass cloth board factories have no material preparation, etc., which will cause the designed stack to fail to be realized or the delivery time to be delayed. What should we do? The best way is to let the board factory design a stack according to our requirements and their experience at the beginning of the design, so that at most a few rounds can get an ideal and achievable stack.

Last time I talked about some "arts of trade-offs" between impedance calculation and process, mainly to achieve our impedance control purpose, but also to ensure the convenience of process processing and minimize processing costs. Next, let's talk about the specific process of using SI9000 to calculate impedance.

How to Calculate Impedance

For impedance calculation, the stacking setting is a prerequisite. First, you must set the specific stacking information of the single board. The following is the stacking information of a common eight-layer board. Take this as an example to see some precautions for impedance calculation.

Figure 1

For the signal line, the form implemented on the board is divided into microstrip line and stripline. The difference between the two makes the structure of impedance calculation selection inconsistent. The following two common impedance calculation situations are discussed separately.

a. Microstrip line The characteristic of microstrip line is that there is only one reference layer, which is covered with green oil. The following are the specific parameter settings for single line (50Ω) and differential line (100Ω).

Precautions:

1. H1 is the dielectric thickness from the surface layer to the reference layer, excluding the copper thickness of the reference layer;

2. C1, C2, C3 are the thickness of green oil. Generally, the thickness of green oil is about 0.5mil~1mil, so keep the default value. The thickness has a slight influence on the impedance. The reason is on the impedance line.

3. The thickness of T1 is generally the thickness of surface copper and electroplating, and 1.8mil is the result of 0.5OZ+Plating.

4. Generally, W1 is the width of the traces on the board. Since the processed lines are trapezoidal, W2

b. Strip line

A stripline is a wire that lies between two reference planes. The following are the specific parameter settings for single line (50Ω) and differential line (100Ω).
Precautions:
1. H1 is the thickness of the CORE between the wire and the reference layer, H2 is the thickness of the PP between the wire and the reference layer (considering the pp flow glue situation); stacking as shown in Figure 1, if the impedance line is on the ART03 layer, then H1 is The dielectric thickness between GND02 and ART03, and H2 is the dielectric thickness between GND04 and ART03 plus the copper thickness.
2. When the medium between Er1 and Er2 is different, you can fill in the corresponding dielectric constant.
3. The thickness of T1 is general