illustrate

The HCPL-315X consists of an optically coupled LED as the output stage of the integrated circuit. This optocoupler is perfect for driving power igbt and mosfet for motor control inverter. The high operating voltage range of the output stage provides the drive voltage devices required for gate control. The voltage and current provided by this optocoupler make it ideal for directly driving igbt ratings up to 1200 V/50 A. For higher rated IGBTs, the HCPL-3150/ 315J can be used to drive the power stage driving the gate of the IGBT.

application

Isolated IGBT/MOSFET gate drive

AC and Brushless DC Motor Drivers

Industrial inverter

Switching Power Supplies (SMPS)

Uninterruptible Power Supply (UPS)

feature

0.6A maximum peak output current

0.5 A minimum peak output current

15kV/µs Minimum Common Mode Rejection (CMR) 1.0V Maximum Low Level Output Voltage (VOL) at VCM=1500 V No Negative Gate Drive Required

CC = 5mA maximum supply current under voltage lockout protection (UVLO) hysteresis

Wide operating voltage control range: 15 to 30 volts 0.5 maximum propagation delay +/- 0.35 μs maximum delay between devices

Industrial temperature range: -40°C to 100°C

HCPL-315J: Channel 1 to Channel 2 output isolation = 1500 Vrms/1 minute.

Safety and Regulatory Approvals: UL Listed (UL1577), 3750 Vrms/1min (HCPL-3150) 5000 Vrms/1min (HCPL-315J) Approved IEC/EN/DIN EN 60747-5-5VIORM=630 V peak (only HCPL-3150 option 060 only) VIORM=1414 Vpeak (HCPL-315J) CSA certified

Selection Guide: Inverted Gate Drive Opto-Isolators

To sort, select a part number from the Part Number column and combine the columns with the desired option in that option to form an order entry.

Example 1: HCPL-3150-560E ordered 300 mil dipped trench surface mount packaging tape and reel packaging product is RoHS compliant IEC/EN/DIN EN 60747-5-5 safety certified.

Example 2: The HCPL-3150 is ordered in a 300 mil tube dip package and a non-RoHS compliant product. An option data sheet is available. Please contact your Avago sales representative or authorized reseller for information. Note: The symbol "xxx" is used for existing products, while (new) products have been introduced since July 15, 2001. RoHS compliant options will use '-XXXE'.

Electrical Specifications (DC)

Over recommended operating conditions (TA=-40 to 100°C, IF(ON)=7 to 16mA, VF(OFF)=-3.6 to 0.8V, VCC=15 to 30V, VEE=ground, each channel) unless otherwise specified.

All typical values at TA=25°C and VCC-VEE=30 V unless otherwise noted

Switching Specifications (AC) over recommended operating conditions (TA = -40 to 100°C, IF (On) = 7 to 16 mA, VF (Off) = -3.6 to 0.8 Volts, VCC = 15 to 30 Volts, VEE = ground, per channel) unless otherwise specified.

Packaging Characteristics (per channel, unless otherwise specified)

All typical values at TA=25°C and VCC-VEE=30 V unless otherwise noted.

I/O instantaneous withstand voltage is a dielectric voltage rating and should not be interpreted as an I/O continuous voltage rating. For continuous voltage ratings, see Equipment Level Safety Specifications or Avago Application Note 1074 titled "Optocoupler Input Output Continuous Voltage".

notes:

1. Linearly reduce the free air temperature above 70°C at a rate of 0.3 mA/°C.

2. Maximum pulse width = 10 s, maximum duty cycle = 0.2%. This value is intended to account for component tolerance peak min = 0.5 A for designs with IO. See the application section for more details on limiting IOH peaks.

3. Linearly reduce the free air temperature above 70°C at a rate of 4.8 mW/°C.

Free air temperature above 4.70°C is 5.4 mW/°C and maximum LED junction temperature does not exceed 125°C.

5. Maximum pulse width = 50 s, maximum duty cycle = 0.5%.

6. In this test, VOH is measured with DC load current. When driving capacitive loads, VOH will approach VCC as IOH approaches zero amps.

7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.

8. According to UL1577, each HCPL-3150 optocoupler is tested by applying insulation test voltage ≥4500 Vrms (≥6000 Vrms HCPL-315J) for 1 second. This test is performed prior to the partial discharge 100% production test (method b) shown in IEC/EN/Insulation Characteristics Table (if applicable).

9. The device is considered a two-terminal device: the pins on the inputs are shorted together and the pins on the output are shorted together.

10. Difference between tPHL and tPLH between any two components or channels under the same experimental conditions.

11. Pins 1 and 4 (HCPL-3150) and pins 3 and 4 (HCPL-315J) need to be connected to the LED common.

12. High immunity to common mode transient pulses is the maximum tolerance dVCM/dt of the common mode pulse VCM to guarantee that the output will remain high (ie VO>15.0V).

13. Common Mode Transient Immunity in Common Mode Pulse (VCM) is the maximum tolerable DVCM/dt of the Common Mode Pulse (VCM) to keep the output low (ie VO < 1.0V).

14. This load condition approximates the gate load of a 1200V/25A IGBT.

15. For any given device, pulse width distortion (PWD) is defined as |tPHL-tPLH|.

16. Every channel.

17. The device is considered to be a double-ended device: the output side pins of channel one are shorted together and the output side pins of channel two are shorted together.

18. See thermal model for HCPL-315J in the application section of this data sheet.

application information

Elimination of Negative IGBT Gate Drive For firm IGBT turn-off, the HCPL-3150/315J has a very low maximum VoL specification of 1.0V. The 3150/315J implements this very low volume pull-down transistor circuit with a 4Ω (typ) resistance by using DMOS. When the HCPL-3150/315J is in the low state, the IGBT gate is shorted to the emitter by Rg+4Ω. The minimization of Rg and lead inductance in the HCPL-3150/315J to the IGBT gate and emitter (possibly by installing the HCPL-3150/315J, at the IGBT) can eliminate the need for negative IGBT gate drive in many applications such as as shown in the figure. Note that this PC board design should be used to avoid routing IGBT collector or emitter traces close to the HCPL-3150/315J input, as this may cause unwanted coupling into the HCPL-3150/315J with transient signals and degrade performance. (If the IGBT drain must be routed near the input of the HCPL-3150/315J, the LEDs should be reverse biased in the off state to prevent transients from the IGBT drain from diverting on the HCPL-3150/315J.)

The gate resistance (Rg) is chosen to minimize IGBT switching losses.

Step 1: Calculate the Rg minimum according to the IOL peak specification. The IGBT and Rg in this figure can be analyzed as a simple RC circuit with voltage supplied by the HCPL-3150/315J.

The VOL value of 2V in the above formula is a conservative value of VOL at a peak current of 0.6A (see figure). The HCPL-3150/315J are not ideal voltage steps at lower Rg values. This results in a lower peak current (greater margin) for this analysis. The preceding equation equals zero volts when no negative gate drive is used.

Step 2: Check the power consumption of the HCPL-3150/315J, increase Rg if necessary. The HCPL-3150/315J total power consumption (lbs)) is equal to the sum of transmit power (PE) and output power (PO):

For the circuit shown with IF (worst case) = 16mA, Rg = 30.5Ω, max duty cycle = 80%, Qg = 500 nC, f = 20kHz and TAmax = 90°C:

The 4.25ma value for ICC in the above equation is obtained by reducing the ICC maximum value by 5 mA (occurring at -40°C) to the maximum ICC at 90°C (see Figure 7). Since PO in this case is greater than PO(MAX), Rg must be increased to reduce the power consumption of the HCPL-3150.

For Qg=500 nC, from the figure, the ESW value=3.45μJ gives an Rg=41Ω.

Thermal Model (HCPL-3150) The steady-state thermal model of HCPL-3150 is shown in Figure 28a. The given thermal resistance values can be used in this model to calculate the temperature at each node under given operating conditions. As shown in this model, all the heat generated increases the case temperature TC correspondingly through θCA. The value θCA depends on board design conditions and, therefore, is determined by the designer. The value θC a = 83°C/W was obtained from thermal measurements using a 2.5 x 2.5" PC board with small traces (no ground plane), a HCPL-3150 soldered to the center of the board and still air. The absolute maximum power dissipation specification assumes a theta cavity of 83°C/W.

From the thermal pattern in Figure 28a, the junction temperature of the LED and detector IC can be expressed as:

TJEs and TJDs should be limited to 125°C according to the board's application-specific layout and part placement (θCA).

Thermal Model Dual Channel (SOIC-16) HCPL-315J Photomultiplier Tube

definition

θ1, θ2, θ3, θ4, θ5, θ6, θ7, θ8, θ9, Th 10: Thermal impedance between nodes, as shown in Figure 28B. Ambient temperature: Measure about 1.25 cm above the optocoupler without forced air.

illustrate

This thermal model assumes a 16-pin dual channel (SOIC-16) optocoupler soldered into an 8.5cm x 8.1cm printed circuit board (PCB). These optocouplers are hybrid devices with four chips: two LEDs and two detectors. The formula for calculating the temperature optocoupler for the LED and detector is below.

ΔTE1A = temperature difference between ambient and LED 1

ΔTE2A = temperature difference between ambient and LED 2

ΔTD1A = temperature difference between ambient temperature and detector 1

ΔTD2A = temperature difference between ambient and detector 2

PE1=Power consumption of LED 1;

PE2=Power consumption of LED 2;

PD1 = power consumption of detector 1;

PD2 = power consumption of detector 2

Axial thermal coefficient (in °C/W) as a function of thermal impedance θ1 through θ10

The LED driver circuit with ultra-high CMR performance considers that in the absence of detector shielding, the main reason for the failure of the optocoupler CMR is from the input side of the optocoupler through the package to the detector IC as shown in Figure 29. The HCPL-3150/315J uses detector ICs to improve CMR performance. Transparent Faraday shields are capacitively coupled current ICs away from sensitive components. In any case, this shield does not eliminate the capacitive coupling between the LED and the optocoupler at pins 5-8 as shown in Figure 30. This capacitive coupling causes LED current transients in common mode and becomes a major source of CMR shielding optocoupler failures. The main design goal of a high CMR LED driver circuit is that during normal operation, the LED is in the normal state (on or off) mode transients. For example, the recommended application circuit (Figure 25) can achieve 15kV/µs CMR while minimizing component complexity. In the next two parts, we'll discuss techniques for keeping LEDs in the correct state.

CMR with LED (CMRH)

High CMR LED driver circuits must keep the LEDs on during common-mode transients. This is done by making the LED current too large to exceed the input threshold, so it doesn't pull below the threshold instantaneously. A minimum LED current of 10mA provides enough headroom over the maximum IFLH of 5mA to achieve. 15kV/µs CMR.

CMR (CMRL) when LED is off

The high CMR LED driver circuit must keep the LED off during common mode transients (VF≤VF(off)). For example, during the -dVCM/dt transient in Figure 31, current flows through CLEDP as well as through the RSAT and VSAT logic gates. As long as the low state voltage generated through the logic gate is less than VF(off), the LED will remain off and no common mode fault will occur. The open collector drive circuit shown in Figure 32 cannot keep the LED off during +dVCM/dt transients, since all current through the Clayton must be provided to be indicated by the LED and is not recommended for performances requiring very high CMRL. Figure 33 is an alternative driver circuit such as the recommended application circuit (Figure 25) that does achieve ultra-high CMR performance of the shunt LED in the off state. Under-Voltage Lockout Feature The HCPL-3150/315J includes an under-voltage lockout (UVLO) feature that protects the IGBT causing the fault condition voltage of the HCPL-3150/315J power supply (equivalent to a fully charged IGBT gate voltage) to drop to keep the IGBT in a low resistance state . When the HCPL-3150/315J output is in a high state, the supply voltage drops below the HCPL-3150/315J VUVLO threshold (9.5

IPM Dead Time and Propagation Delay Specification The HCPL-3150/315J includes a Propagation Delay Difference (PDD) specification designed to help designers minimize "dead time" in their power inverter designs. Dead time is when the low-side power transistors (Q1 and Q2 in Figure 25) are turned off. Any overlap of Q1 and Q2 conduction will result in motor rails going from high voltage to low voltage in the large current flowing through the power device. To minimize dead time in a given design, turning on LED2 should be delayed (relative to turning off LED1) so in the worst case transistor Q1 just turns off when transistor Q2 is on, as shown in Figure 34. The amount of delay required to achieve this condition is equal to the maximum value of the propagation delay difference specification PDPDMAX, which is specified for 350ns above operating temperature in the range of -40°C to 100°C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it doesn't tell the designer what the maximum dead time will be. The maximum dead time is equal to the maximum and minimum propagation delay difference specifications, as shown in Figure 35. The HCPL-315/315J has a maximum dead time of 700 nanoseconds. The range is -40°C to 100°C at operating temperature (=350ns - (-350ns). Note that the propagation delay used to calculate the PDD takes the dead time at the same temperature and tests the optocoupler under consideration The post conditions are usually installed close to each other. The same igbt is being switched.