feature

Low power, small footprint, pin-compatible octal digital-to-analog converter; AD5668 : 16-bit; AD5648: 14-bit; AD5628: 12-bit; 14-lead/16-lead TSSOP, 16-lead LFCSP, and 16-lead WLCSP; on-chip 1.25 V/2.5 V, 5 ppm/°C reference; power supply drops to 400 mA at 5 V and 200 mA at 3 V; 2.7 V to 5.5 V power supply is designed to be monotonic; power-on reset to zero scale or mid-scale; 3 power down function; hardware LDAC and LDAC override function; CLR function to programmable code rail-to-rail operation.

application

Process Control; Data Acquisition Systems; Digital Gain and Offset Adjustment for Portable Battery-Powered Instruments; Programmable Attenuators for Programmable Voltage and Current Sources.

General Instructions

The AD5628/AD5648/AD5668 devices are low power, octal, 12-/14-/16-bit, buffered voltage output DACs. All devices operate from a single 2.7 V to 5.5 V supply and are guaranteed monotonic by design. The AD5668 and AD5628 are available for 4mm x 4mm LFCSPs and 16-lead TSSOPs, while the AD5648 is available for 14-lead and 16-lead TSSOPs.

The AD5628/AD5648/AD5668 have an on-chip reference with an internal gain of 2. The AD5628-1/AD5648-1/AD5668-1 have a 1.25 V 5 ppm/°C reference with a full-scale output range of 2.5 V; the AD5628-2/AD5648-2/AD5668-2 and AD5668-3 have a 2.5 reference V 5 ppm/°C, full-scale output range is 5 V. On power-up, the on-board voltage reference is turned off, allowing the use of an external voltage reference. Internal references are enabled by software writing.

Selectable output load in power-down mode for any or all DAC channels. The outputs of all DACs can be updated simultaneously using the LDAC function, and additional functions of user-selectable DAC channels can be updated simultaneously. There is also an asynchronous CLR which updates all DACs to user programmable code zero, mid or full scale.

The AD5628/AD5648/AD5668 feature a versatile 3-wire serial interface that operates at clock frequencies up to 50 MHz and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards. On-chip precision output amplifiers achieve rail-to-rail output swing.

Product Highlights

1. Octal, 12-/14-/16-bit DAC.

2. On-chip 1.25 V/2.5 V, 5 ppm/℃ benchmark.

3. Provide 14-lead/16-lead TSSOP, 16-lead LFCSP and 16-lead WLCSP.

4. Power-on reset to 0 V or midscale.

5. Power-off capability. When powered down, the DAC typically consumes 200na at 3v and 400na at 5v.

the term

Relative accuracy

For a DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation in the LSBS from a straight line through the endpoints of the DAC transfer function. Figure 7 to Figure 9, Figure 13 to Figure 15, Figure 19 to Figure 21 show typical INL versus code diagrams.

Differential nonlinearity

Differential Nonlinearity (DNL) is the difference between the measured variation of any two adjacent codes and the ideal 1lsb variation. The specified differential nonlinearity ±1 LSB maximum guarantees monotonicity. The monotonicity of the DAC is guaranteed by design. Figures 10-12, 16-18, and 22-24 show typical DNL versus code plots.

offset error

Offset error is the difference between the measured actual voltage and the ideal voltage, expressed in millivolts in the linear region of the transfer function. The offset error is measured on the AD5668 and the code 512 is loaded into the DAC register. It can be negative or positive and is expressed in millivolts.

Zero code error

A zero code error is a measure of the output error when a zero code (0x0000) is loaded into the DAC register. Ideally, the output should be 0 V. Since the output of the DAC cannot go below 0 V, the zero code error is always positive in the AD5628/AD5648/AD5668. This is due to a combination of offset errors in the DAC and output amplifier. Zero code errors are expressed in millivolts. Figure 28 shows a plot of typical zero code errors versus temperature.

gain error

Gain error is a measure of DAC span error. It is the slope deviation of the DAC transfer characteristic from ideal, expressed as a percentage of the full-scale range.

Zero code error drift

Zero-code error drift is a measure of zero-code error as a function of temperature. Expressed in microvolts/degree Celsius.

Gain Error Drift

Gain error drift is a measure of gain error over temperature. Expressed in (ppm of full scale)/°C.

full scale error

Full-scale error is a measure of the output error when the full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be V–1lsb. Full-scale error is expressed as a percentage of full-scale range. Figure 25 shows a typical plot of full-scale error versus temperature.

Digital-to-analog fault pulse

A digital-to-analog fault pulse is a pulse injected into the analog output when the input code in the DAC register changes state. It is usually designated as a fault region in nV-s and is measured when the digital input code is changed by 1lsb at the major carry transition (0x7FFF to 0x8000). See Figure 42.

DC Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to the change in VDD for the full-scale output of the DAC. It is measured in decibels. VREF remains at 2v and VDD varies by ±10%.

DC crosstalk

DC crosstalk is the DC change in the output level of one DAC as the output of another DAC changes. It is measured by the full-scale output change of one DAC (or soft power off and on) while monitoring the other DAC held at mid-scale. It is expressed in microvolts.

DC crosstalk caused by load current changes is a way to measure the effect of a change in load current on one DAC on another DAC held at midscale. It is expressed in microvolts per milliampere.

reference feedthrough

Reference feedthrough is the ratio of the signal amplitude at the DAC output to the reference input when the DAC output is not being updated (ie, LDAC is high). It is expressed in decibels.

digital feedthrough

Digital feedthrough is a measurement of the pulses injected into the DAC's analog output from the device's digital input pins, but when the DAC is not being written (sync is held high). It is specified in nV-s and is measured by a full-scale change on the digital input pins, i.e. from 0 to 1 or from 0 to 1.

digital crosstalk

Digital crosstalk is a glitch pulse that is mid-scale transferred to the output of one DAC in response to a full-scale code change (all 0s to all 1s, and vice versa) in the input register of the other DAC. It is measured in standalone mode and expressed in nV-s.

Analog crosstalk

Analog crosstalk is a glitch pulse transferred to the output of one DAC due to a change in the output of another DAC. With LDAC held, measure high by loading an input register with a full-scale code change (all 0s to all 1s and vice versa), then pulse LDAC low and monitor the output of the DAC whose digital code has not changed. The fault area is denoted by nV-s.

DAC-to-DAC crosstalk

DAC-to-DAC crosstalk is a glitch pulse transferred to the output of one DAC due to a change in the digital code of one DAC and a subsequent change in the output of the other DAC. This includes digital and analog crosstalk. It is measured by loading a DAC with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of the other DAC. The fault energy is expressed in nV-s.

Double the bandwidth

Amplifiers within a DAC have limited bandwidth. Multiplying bandwidth is one measure. A sine wave on the reference appears in the output (loading the full-scale code to the DAC). The octave bandwidth is the frequency at which the output amplitude drops 3db below the input.

Total Harmonic Distortion (THD)

Total Harmonic Distortion is the difference between an ideal sine wave and an attenuated sine wave using a DAC. The sine wave is used as a reference for the DAC, and THD is a measure of the harmonics of the DAC's output. It is measured in decibels.

theory of operation

Section D/A

The AD5628/AD5648/AD5668 digital-to-analog converters are fabricated using a CMOS process. The structure consists of a series of DACs and an output buffer amplifier. Each section includes an internal 1.25 V/2.5 V, 5 ppm/degree Celsius reference with an internal gain of 2. Figure 55 shows a block diagram of the DAC architecture.

Because the input encoding of the DAC is straight binary, the ideal output voltage when using an external reference is given by:

The ideal output voltage when using the internal reference is given by:

Where: D = Load into DAC register. 0 to 4095 (12 bits) for AD5628. 0 to 16383 (14 bits) for AD5648. 0 to 65535 (16 bits) for AD5668. N=DAC resolution.

resistor string

The resistor string section is shown in Figure 56. It's just a string of resistors, each with a value of R. The code loaded into the DAC register determines from which node on the string the voltage is tapped into the output amplifier. The voltage is cut off by closing a switch to connect the string to the amplifier. Because it is a string of resistors, monotonicity is guaranteed.

internal reference

The AD5628/AD5648/AD5668 have an on-chip reference with an internal gain of 2. AD5628/AD5648/AD5668-1 have a reference voltage of 1.25 V, 5 ppm/°C, full scale output is 2.5 V; AD5628/AD5648/AD5668-2, -3 have a reference voltage of 2.5 V, 5 ppm/°C, full scale The output is 5V. On power-up, the on-board voltage reference is turned off, allowing the use of an external voltage reference. Internal references are enabled by writing to the control register (see Table 8).

An internal reference associated with each part is available at the V pin. A buffer is required if the reference output is used to drive an external load. When using the internal reference, it is recommended to place a 100 nF capacitor between the reference output and GND to maintain reference stability. Single channel power down is not supported when using internal references.

output amplifier

The output buffer amplifier can generate rail-to-rail voltages at its output, allowing the output to range from 0v to VDD. The amplifier is capable of driving 2 kΩ loads in parallel with 200 pF to GND. The source and sink capabilities of the output amplifier are shown in Figure 32 and Figure 33. The slew rate was 1.5 V/µs and the scale settling time was 7 µs.

serial interface

The AD5628/AD5648/AD5668 have a 3-wire serial interface (SYNC, SCLK, and DIN) compatible with SPI, QSPI, and MICROWIRE interface standards and most DSPs. A timing diagram of a typical write sequence is shown in Figure 2.

Pull the sync line low at the beginning of the write sequence. Data from the data line is recorded into a 32-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50MHz, making the AD5628/AD5648/AD5668 compatible with high-speed DSPs. On the 32 falling clock edge, the last data bit is clocked and performs the programming function, ie, a change in the contents of the DAC register and/or a change in operating mode. During this phase, the sync line can be held low or high. In both cases, it must be brought up at least 15 ns before the next write sequence, so that the falling edge of synchronization can initiate the next write sequence. Synchronization between write sequences should be in a low idle state for lower power operation of the part. However, as mentioned earlier, synchronization must be improved again before the next write sequence.

Input shift register synchronization interrupt

The input shift register is 32 bits wide. The first four bits are a normal write sequence, the sync line is held low, no worries. The next 4 bits are the command bits, C3 to C0 32 falling edge of SCLK, DAC is updated on 32 (see Table 8), followed by the 4-bit DAC address, A3 to A0 (see falling and rising edges of SYNC) . However, if SYNC is brought to Table 9), the end is a 16-/14-/12-bit data word. The high bit of data before the falling edge of 32, which acts as an interrupt word, consists of the 16-/14-/12-bit input code, followed by four write sequences. The shift register is reset and the write sequence 6 or 8 doesn't care about the bits of the AD5668, AD5648 and is treated as invalid. None of the updates to the DAC registers include the AD5628, respectively (see Figure 57 to Figure 59). It also does not change the operating mode (see Figure 60).

The data bits are transferred to the DAC register on the falling edge of SCLK 32.

Internal reference register

By default, on-board reference is turned off at power on. This allows external references to be used when needed by the application. The on-board reference can be turned on or off by a user-programmable internal reference register by setting bit DB0 high or low (see Table 10). Command 1000 is reserved for setting the internal REF register (see Table 8). Table 12 shows how the state of the bits in the input shift register corresponds to the operating mode of the device.

power-on reset

The AD5628/AD5648/AD5668 family includes a power-on reset circuit that controls the output voltage during power-up. AD5628/AD5648/AD5668-1, -2 DAC output power up to 0 V, AD5668-3 DAC output power up to midscale. The output will remain powered on at this level until a valid write sequence is issued to the DAC. This is useful in applications where it is important to know the state of the DAC's output during power-up. There is also a software executable reset function that resets the DAC to a power-on reset code. Command 0111 is reserved for this reset function (see Table 8). During power-on reset, any events on the LDAC or CLR are ignored.

Power down mode

The AD5628/AD5648/AD5668 contain four independent modes of operation. Command 0100 is reserved for the power down function (see Table 8). These modes are software programmed by setting two bits DB9 and DB8 in the control register.

Table 12 shows how the state of the bits corresponds to the operating mode of the device. Any or all DACs (DAC H to DAC A) can be powered down to the selected mode by setting the corresponding 8 bits (DB7 to DB0) to 1. The contents of the input shift register during power-down/power-up operations are shown in Table 13. When using the internal reference, only all channel power down to the selected mode is supported.

When both bits are set to 0, the part operates normally at 5 V and its normal power consumption is 1.3 mA. However, the supply current drops to 0.4 µA at 5 V (0.2 µA at 3 V) for the three power-down modes. Not only does the supply current drop, but the output stage also switches from inside the amplifier's output to a network of resistors of known value. The advantage of this is that the output impedance of the component is known when the component is in power down mode. There are three different options. The output is internally connected to ground through a 1 kΩ or 100 kΩ resistor, or left open (three states). The output stage is shown in Figure 61.

When the power-down mode is activated, the bias generator, output amplifier, resistor string, and other associated linear circuits of the selected DAC are turned off. The internal reference will only be powered down when all channels are powered down. However, when powered down, the contents of the DAC registers are not affected. The power-off time is typically 4 V, V=5 V, and VDD=3 V. See the diagram of FIG. 41 .

Any combination of DACs can be powered up by setting PD1 and PD0 to 0 (normal operation). The output powers up to the value in the input register (LDAC low) or the value in the DAC register before power down (LDAC high).

clear code register

The AD5628/AD5648/AD5668 have a hardware CLR pin with an asynchronous clear input. The CLR input is falling edge sensitive. Turning the CLR line low will clear the contents of the input and DAC registers contained in the user-configurable CLR register and set the analog output accordingly. This function can be used for system calibration to load zero, mid or full scale into all channels. These clear code values are user programmable by setting two bits in the CLR Control Register, Bit DB1 and Bit DB0 (see Table 14). The default setting clears the 0 V output. Command 0101 is reserved for loading the clear code register (see Table 8).

The section exits clear code mode on the falling edge of 32 of the next write section. If the CLR is activated during a write sequence, the write will abort.

When the output begins to change, the CLR pulse activation time for the falling edge of CLR is typically 280ns. However, outside the DAC linear region, it typically takes 520ns to start changing the output after performing CLR (see Figure 51).

During a load clear code register operation, the contents of the input shift register are shown in Table 15.

LDAC function

The outputs of all DACs can be updated simultaneously using the hardware LDAC pins. Synchronous LDAC: After reading new data, the DAC register is updated on the falling edge of 32 SCLK pulses. As shown in Figure 2, LDAC can be permanently low or pulsed.

Asynchronous LDAC: Output not updated at the same time

Time to write to the input register. When LDAC goes low, the DAC register is updated with the contents of the input register. Alternatively, the software LDAC function can be used to simultaneously update the output register n of all DACs and update all DAC registers by writing to the input. Command 0011 is reserved for this software LDAC function.

The LDAC register gives the user additional flexibility and control over the hardware LDAC pins. This register allows the user to select a combination of channels to be updated simultaneously when implementing the hardware LDAC pins. Setting the LDAC bit register for a DAC channel to 0 means that the update of that channel is controlled by the LDAC pin. If this bit is set to 1, the channel will be updated synchronously; that is, the DAC register will be updated after new data is read, regardless of the state of the LDAC pin. It effectively holds the LDAC pin low. (See Table 16 of LDAC Register Operating Modes) This flexibility is useful in applications where the user wishes to update the selected channel simultaneously, while the remaining channels are updated synchronously.

Write to the DAC using command 0110 to load the 8-bit LDAC registers (DB7 to DB0). The default value for each channel is 0, i.e., the LDAC pin is functioning properly. Setting the bit to 1 means that the DAC channel is updated regardless of the state of the LDAC pin. The contents of the input shift register during the load LDAC register mode of operation are shown in Table 17.

Power Bypass and Ground

When accuracy is important in a circuit, it is helpful to carefully consider the power and ground return layout on the board. The printed circuit board/AD5668 containing the AD5628/AD5648 should have separate analog and digital sections. If the AD5628/AD5648/AD5668 are in a system where other devices require an AGND to DGND connection, the connection should be made at only one point. This base point should be connected to the AD5628/AD5648/AD5668 as much as possible.

The power supplies to the AD5628/AD5648/AD5668 should be bypassed with 10µF and 0.1µF capacitors. The capacitor should be physically located as close to the device as possible, ideally, the 0.1µF capacitor should be right across from the device. The 10µF capacitors are of the tantalum bead type. Importantly, 0.1µF capacitors have low effective series resistance (ESR) and low effective series inductance (ESI), typical of common ceramic capacitors. This 0.1µF capacitor provides a low impedance ground path for high frequencies caused by transient currents generated by the internal logic switches.

Power lines should have as large a trace as possible to provide a low impedance path and reduce the impact of faults on the power line. Clocks and other fast switching digital signals should be shielded from the rest of the board by digital ground. Avoid crossover of digital and analog signals as much as possible. When traces cross on opposite sides of the board, make sure they run at right angles to each other to reduce the effect of feedthrough through the board. The best board layout technique is microstrip, where the component side of the board is used only for the ground plane, and the signal traces are placed on the solder side. However, this is not always possible with 2-layer boards.

Dimensions