feature

SNR = 77.6 dBFS at 70 MHz, 125 MSPS SFDR = 88 dBc at 70 MHz, 125 MSPS; Low Power: 750 mW @ 125 ms/s; 1.8V analog supply operation; 1.8V CMOS or LVDS output supply integer 1 to 8 input clock divider; if sampling frequency up to 300 MHz; -152.8 dBm/Hz small signal input noise, input impedance 200 Ω @ 70 MHz and 125 MSPS; selectable on-chip dithering; programmable internal ADC voltage reference; integrated ADC sample and hold input; flexible analog input range: 1 VP to 2 VPP; differential analog input with 650 MHz bandwidth; ADC clock duty cycle stabilizer; 95 dB channel isolation/crosstalk; serial port control; user configurable The built-in self-test (BIST) feature saves power in power-down mode.

application

Communication; Diversity Radio System; Multimode Digital Receiver (3G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA; I/Q Demodulation System; Smart Antenna System; General Software Radio; Wideband Data Application ; Ultrasonic equipment.

Product Highlights

1. On-chip dithering option to improve SFDR performance of low-power analog inputs.

2. Proprietary differential input, maintains good signal-to-noise performance at input frequencies up to 300 MHz.

3. Operation of a 1.8V power supply and a separate digital output driver power supply that can accommodate 1.8V CMOS or LVDS outputs.

4. Standard Serial Port Interface (SPI) that supports various product features and functions, such as data formatting (offset binary, duplex or gray coding), enabling clock DCS, power down, test mode and voltage reference mode .

5. Pin compatible with AD9268, allowing easy migration from 14-bit to 16-bit. The AD9258 is also pin-compatible with the AD9251, AD9231, and AD9204 families for low sample rate, low power applications.

General Instructions

The AD9258 is a dual 14-bit 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC). The AD9258 is designed to support communications applications that require high performance, low cost, small size, and versatility.

The dual ADC core adopts a multi-stage differential pipeline structure and integrates output error correction logic. Each ADC features a wideband differential sample-and-hold analog input amplifier that supports multiple user-selectable input ranges. An integrated voltage reference simplifies design considerations. A duty cycle stabilizer is provided to compensate for changes in the ADC clock duty cycle, allowing the converter to maintain excellent performance.

ADC output data can be routed directly to two external 14-bit output ports. These outputs can be set to 1.8V CMOS or LVD. Flexible power-down options allow large power savings when needed. Programming for setup and control is done using a 3-wire SPI-compatible serial interface.

The AD9258 is available in a 64-lead LFCSP and is specified over the industrial temperature range of -40°C to +85°C.

Switch Specifications

Unless otherwise noted, AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1 dBFs differential input, 1 V internal reference, and DCS enabled.

Stresses listed above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions described in the operating section of this specification or any other conditions above is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Thermal characteristics

The exposed blades must be soldered to the ground plane of the LFCSP package. Soldering exposed paddles to the PCB increases solder joint reliability and maximizes thermal performance of the package.

Typical θ is specified for a 4-layer PCB with a solid ground plane. As shown in Table 7, airflow improves heat dissipation, which reduces θ. Additionally, metal in direct contact with the package is drawn from metal traces, vias, ground and power planes, reducing θ.

theory of operation

The AD9258 dual-core analog-to-digital converter (ADC) design can be used for signal diversity reception, where the ADC operates on the same carrier, but from two separate antennas. ADCs can also be operated with separate analog inputs. The user can use appropriate low-pass or band-pass filtering at the ADC input to sample any f/2 frequency band from dc to 200mhz with little loss of ADC performance. Operation on 300 MHz analog inputs is allowed, but at the expense of increased ADC noise and distortion.

In non-dispersive applications, the AD9258 can be used as a baseband or direct downconversion receiver with one ADC for I input data and the other for Q input data. Synchronization is provided to allow synchronized timing between multiple devices.

Programming and control of the AD9258 is done using a 3-wire SPI compatible serial interface.

ADC Architecture

The AD9258 architecture consists of a dual front-end sample-and-hold circuit and a pipelined switched-capacitor ADC. In the digital correction logic, the quantized outputs from each stage are combined into a final 14-bit result. The pipelined architecture allows the first stage to operate on new input samples and the remaining stages to operate on previous samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last stage, consists of a low-resolution flash ADC connected to a switched-capacitor digital-to-analog converter (DAC) and an interstage residual amplifier (MDAC). The MDAC amplifies the difference between the reconstructed DAC output and the flash input for use in the next stage. One bit redundancy is used per stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC.

The input stage of each channel contains a differential sampling circuit that can be coupled ac or dc in differential or single-ended mode. The output scratch block aligns the data, corrects errors, and passes the data to the output buffer. The output buffer is powered by a separate power supply, allowing the digital output noise to be separated from the analog core. During power down, the output buffers go into a high impedance state.

Analog Input Considerations

The analog input to the AD9258 is a differential switched capacitor circuit designed for optimum performance when processing differential input signals.

The clock signal alternately switches the input between sample mode and hold mode (see Figure 64). When the input switches to sampling mode, the signal source must be able to charge the sampling capacitor and settle within 1/2 of the clock period.

Small resistors in series with each input help reduce the peak transient current required to drive the source output stage. A parallel capacitor can be placed at the input to provide dynamic charging current. This passive network creates a low-pass filter at the ADC input; therefore, the exact value depends on the application.

In IF undersampling applications, any parallel capacitors should be reduced. Combined with the drive source impedance, the shunt capacitor limits the input bandwidth. Refer to AN-742 Application Note, Frequency Domain Response of Switched Capacitor ADCs; AN-827

Application Note, Resonant Methods for Interfacing Amplifiers with Switched Capacitor ADCs; and the Analog Dialogue Article, "Transformer-Coupled Front Ends for Wideband A/D Converters," for more information on this topic (see ).

For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched and the inputs should be differentially balanced. An internal differential reference buffer generates positive and negative reference voltages that define the input range of the ADC core. This buffer sets the span of the ADC core to 2×VREF.

Input common mode

The analog inputs of the AD9258 have no internal DC bias. In AC-coupled applications, the user must provide this bias externally. Setting the device to VCM = 0.5 × AVDD (or 0.9 V) is recommended for best performance, but the device has a wider range of functions and reasonable performance (see Figure 54). An on-board common-mode voltage reference is included in the design, available from the VCM pin. Best performance is obtained when the common-mode voltage of the analog inputs is set by the VCM pin voltage (typically 0.5 × AVDD). The VCM pin must be separated from ground by a 0.1µF capacitor, as described in the Applications Information section.

Common Mode Voltage Servo

In applications where there may be a voltage loss between the VCM output and the analog input of the AD9258, a common-mode voltage servo can be enabled. When the input is AC coupled and the resistance between the VCM output and the analog input is greater than 100Ω, there will be a significant voltage drop, and the common mode voltage servo should be enabled. Setting Bit 0 in Register 0x0F to logic high enables VCM servo mode. In this mode, the AD9258 monitors the common-mode input level at the analog input and adjusts the VCM output level to maintain the common-mode input voltage at the optimum level. If both channels are operational, channel A is monitored. However, if channel A is in power down or standby mode, the input to channel B will be monitored.

jitter

The AD9258 has a selectable dither mode that can be selected for one or both channels. Dithering is the act of injecting a known but random amount of white noise (often called dithering) into the input of an ADC. Dithering can improve local linearity at various points in the ADC transfer function. Dithering can significantly improve SFDR when quantizing small-signal inputs, typically at input levels below -6dbfs.

As shown in Figure 65, the jitter added to the ADC input by the dither DAC is precisely digitally subtracted to minimize SNR degradation. When dithering is enabled, the dithering DAC is driven by a pseudo-random number generator (PN-gen). In the AD9258, the dither DAC is precisely calibrated to cause only very little degradation in SNR and SINAD. With dither enabled, typical SNR and SINAD attenuation values are only 1db and 0.8db, respectively.

Large Signal FFT

In most cases, dithering will not improve SFDR for large signal inputs close to full scale, such as with -1 dBFS inputs. For large signal inputs, SFDR is usually limited by front-end sampling distortion, and jitter cannot be improved. However, even for such large signal inputs, dithering may be useful for some applications because it makes the noise floor whiter. As is often the case in pipelined ADCs, the AD9258 contains small DNL errors caused by random component mismatches that produce pops or tones that randomly color parts of the noise floor. Although these tones are usually at very low levels, and when the ADC is quantizing large signal inputs, dithering converts these tones into noise and produces a whiter noise floor.

Small Signal FFT

For small-signal inputs, the front-end sampling circuit typically contributes very little distortion, so SFDR is likely to be limited by tones due to DNL errors due to random component mismatches. So for small signal inputs (typically below -6dbfs) dithering can significantly improve SFDR by converting these DNL tones to white noise.

static linearity

Dithering also removes sharp local discontinuities in the ADC's INL transfer function and reduces the overall peak-to-peak INL.

In receiver applications, utilizing dither can help reduce DNL errors that contribute to small-signal gain errors. Typically, this problem is overcome by setting the input noise to be 5dB to 10dB higher than the converter noise. Correcting DNL errors with dither inside the converter reduces input noise requirements.

Best performance is obtained when driving the AD9258 in a differential input configuration. For baseband applications, the AD8138, ADA493-2, and ADA4938-2 differential drivers provide excellent performance and a flexible ADC interface.

The output common-mode voltage of the ADA4938-2 is easily set using the VCM pin of the AD9258 (see Figure 66), and the driver can be configured in a Sallen key filter topology to provide band limiting of the input signal.

For baseband applications where signal-to-noise ratio is a critical parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 67. To bias the analog input, the VCM voltage can be connected to the center tap of the transformer secondary winding.

Signal characteristics must be considered when selecting a transformer. Most RF transformers have saturation frequencies below a few megahertz (MHz). Excessive signal power can also cause the core to saturate, resulting in distortion.

1. In this configuration, R1 is a ferrite bead with a value of 10Ω@100 MHz.

An alternative to using a transformer coupled input, the second Nyquist zone frequency is to use an AD8352 differential driver. An example is shown in Figure 69. See the AD8352 data sheet for more information.

voltage reference

The AD9258 has a built-in stable and accurate voltage reference. The input range can be adjusted by changing the reference voltage applied to the AD9258 using the internal reference voltage or an externally applied reference voltage. The input range of the ADC tracks the linear variation of the reference voltage. The following sections summarize the various reference modes. The Reference Decoupling section describes the reference PCB layout best practices.

Internal reference connection

The comparator in the AD9258 senses the potential at the sense pin and configures the reference into four possible modes, as shown in Table 11. If the sensor is grounded, the reference amplifier switch is connected to an internal resistor divider (see Figure 70) to set VREF to 1.0 V for the 2.0 V pp full-scale input. In this mode, the full scale can also be adjusted through the SPI port by adjusting Bit 6 and Bit 7 of Register 0x18 with the sensor grounded. These bits can be used to change the full scale to 1.25 V pp, 1.5 V pp, 1.75 V pp, or the default value of 2.0 V pp.

Connect the sense pin to the VREF pin, switch the reference amplifier output to the sense pin, complete the loop, and provide a 0.5 V reference output for a 1 V pp full-scale input.

As shown in Figure 71, if the resistor divider is externally connected to the chip, the switch is again set to the sense pin. This puts the reference amplifier in a non-vertical mode with a VREF output, defined as:

The input range of the ADC is always equal to twice the internal or external reference (VREF) pin voltage.

If the AD9258's internal reference is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 72 shows the effect of load on the internal reference voltage.

Xref Operations

An external reference may be required to improve the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 73 shows the typical drift characteristics of the internal reference in 1.0V mode.

When the sense pin is tied to AVDD, internal references are disabled, allowing external references to be used. The internal reference buffer loads the external reference with an equivalent 6 kΩ load (see Figure 62). Internal buffers generate positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1 V.

Clock Input Considerations

For best performance, the AD9258 sample clock inputs (CLK+ and CLK-) should be clocked with differential signals. Signals are typically AC coupled to the CLK+ and CLK- pins through transformers or capacitors. These pins are internally biased (see Figure 74) and do not require external biasing. If the input is floating, the CLK pin is pulled low to prevent false clocks.

Clock input options

The AD9258 has a very flexible clock input structure. The clock input can be CMOS, LVDS, LVPECL, or a sine wave signal. Regardless of the type of signal used, clock source jitter is of greatest concern, as described in the Jitter Considerations section.

Figure 75 and Figure 76 show the two preferred methods for clocking the AD9258 (clock frequencies up to 625 MHz). Low-jitter clock sources use RF baluns or RF transformers to convert from single-ended to differential signals.

For clock frequencies between 125 MHz and 625 MHz, an RF balun configuration is recommended; for clock frequencies between 10 MHz and 200 MHz, an RF transformer is recommended. Back-to-back Schottky diodes across the transformer/balun quadratic limit the clock skew to the AD9258 to a P-P differential of approximately 0.8 V.

This limit helps prevent large voltage fluctuations of the clock from being fed through other parts of the AD9258, while maintaining fast rise and fall times for signals that are critical for low jitter performance.

If a low-jitter clock source is not available, another option is to AC-couple the differential PECL signal to the sampling clock input pins, as shown in Figure 77. The AD9510/AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/AD9518 clock drivers have excellent jitter performance.

A third option is to AC couple the differential LVDS signal to the sample clock input pins, as shown in Figure 78. The AD9510/AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/AD9518 clock drivers provide excellent jitter performance.

In some applications, it is acceptable to drive the sampling clock input with a single-ended CMOS signal. In this application, the CLK+ pin should be driven directly from the CMOS gate and the CLK- pin should be bypassed to ground with a 0.1µF capacitor (see Figure 79).

input clock divider

The AD9258 includes an input clock divider capable of dividing the input clock by an integer value between 1 and 8. For split ratios of 1, 2 or 4, a duty cycle stabilizer (DCS) is optional. For other split ratios, divide by 3, 5, 6, 7, and 8, the duty cycle stabilizer must be enabled for proper operation.

The AD9258 clock divider can be synchronized using an external synchronization input. Bit 1 and Bit 2 of Register 0x100 allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after a register write. A valid synchronization causes the clock divider to reset to its initial state. This synchronization feature allows alignment of clock dividers in multiple sections to ensure simultaneous input sampling.

clock duty cycle

Typical high-speed ADCs use two clock edges to generate various internal timing signals, and the results can be sensitive to the clock duty cycle. The AD9258 requires tight tolerances on the clock duty cycle to maintain dynamic performance characteristics.

The AD9258 contains a duty cycle stabilizer (DCS) that retimes the non-sampling (falling) edges to provide an internal clock signal with a 50% nominal duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9258. With DCS enabled, the noise and distortion performance is nearly flat over a wide range of duty cycles.

Jitter on the rising edge of the input is still the most important issue and is not easily reduced by the internal stabilization circuit. The duty cycle control loop is not nominally suitable for clock frequencies less than 20 MHz. In applications where the clock rate can vary dynamically, the time constant associated with the loop must be considered. After the dynamic clock frequency is increased or decreased, a latency of 1.5 μs to 5 μs is required before the DCS loop relocks to the input signal. During the time period when the loop is not locked, the DCS loop is bypassed and the internal device timing depends on the duty cycle of the input clock signal. In this application, the duty cycle stabilizer can be appropriately disabled. In all other applications, DCS circuits are recommended to maximize AC performance.

Jitter Considerations

High-speed, high-resolution ADCs are very sensitive to the quality of the clock input. For inputs near full scale, the SNR attenuation at low frequency signal-to-noise ratio (SNR) due to jitter (t) at a given input frequency (f) can be given by:

In the equation, rms aperture jitter represents the clock input jitter specification. If the undersampling application is particularly sensitive to jitter, as shown in Figure 80. The measurement curves in Figure 80 were made with an ADC clock source of approximately 65 fs jitter, which combined with the 70 fs jitter inherent in the AD9258, produced the results shown.

In cases where aperture jitter may affect the dynamic range of the AD9258, the clock input should be treated as an analog signal. The power supply for the clock driver should be separated from the ADC output driver power supply to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators are the best clock source. If the clock is generated from another type of source (by gating, division, or other methods), it should be retimed by the original clock in the last step.

For more information on ADC jitter performance, see the AN-501 application note and AN-756 application note (visit).

Channel/Chip Synchronization

The AD9258 has a synchronization input that provides the user with flexible synchronization options for synchronous clock dividers. The clock divider synchronization feature is useful for ensuring synchronized sampling clocks between multiple ADCs. The input clock divider can synchronize at one occurrence or every occurrence of the synchronization signal.

The sync input is internally synchronized to the sample clock; however, to ensure that there is no timing uncertainty between the multiple parts, the sync input signal should be externally synchronized to the input clock signal for the setup and hold times shown in Table 5. The sync input should be driven with a single-ended CMOS type signal.

Power Consumption and Standby Modes

As shown in Figure 81, the power consumed by the AD9258 varies with its sampling rate. In CMOS output mode, the digital power consumption depends primarily on the strength of the digital drivers and the load on each output bit.

The maximum DRVDD current (IDRVDD) can be calculated as: IDRVDD = VDRVDD × CLOAD × fCLK × N, where N is the number of output bits (28 plus two DCO outputs in the case of the AD9258).

This maximum current occurs when each output bit toggles on every clock cycle, i.e. a full-scale square wave at the Nyquist frequency of F/2. In practical applications, the DRVDD current is determined by the switching quantity of the average output bits, which is determined by the sampling rate and the characteristics of the analog input signal.

Reducing the capacitive loading of the output driver reduces digital power consumption. The data in Figure 81 was acquired in LVDS output mode using the same operating conditions as those used in the Typical Performance Characteristics section.

By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD9258 is placed in power down mode. In this state, the ADC typically dissipates 2.5mW. When powered down, the output drivers are in a high impedance state. Asserting the PDWN pin low will return the AD9258 to its normal operating mode.

Low power consumption in shutdown mode is achieved by turning off the reference, reference buffer, bias network and clock. Internal capacitors are discharged when entering power-down mode and must then be recharged when normal operation is resumed.

When using the SPI port interface, the user can place the ADC in power-down or standby mode. Standby mode allows the user to keep the internal reference circuit powered up when a faster wake-up time is required.

digital output

The AD9258 output driver can be configured to interface with 1.8V CMOS logic families. The AD9258 can also be configured as an LVDS output (standard ANSI or reduced output swing mode) using a DRVDD supply voltage of 1.8V.

In CMOS output mode, the output drivers are sized to provide enough output current to drive various logic families. However, large drive currents tend to cause current glitches on the power supply, affecting converter performance. Applications that require the ADC to drive large capacitive loads or large sectorized outputs may require external buffers or latches.

The default output mode is CMOS, with each channel output on a separate bus, as shown in Figure 2. The output can also be configured for interleaved CMOS through the SPI port. In interleaved CMOS mode, the data from both channels is output via the channel A output bit and the channel B output is placed in high impedance mode. The timing diagram for the interleaved CMOS output mode is shown in Figure 3.

When operating in external pin mode, the output data format can be selected for offset binary or two's complement by setting the SCLK/DFS pin.

As described in the AN-877 application note, through the SPI interface to the high-speed ADC, when using SPI control, the data format of offset binary, two's complement, or gray code can be selected.

Digital output enable function (OEB)

The AD9258 has the ability to have flexible three-state digital output pins. Tri-state mode is enabled using the OEB pin or via SPI. If the OEB pin is low, the output data driver and dco are enabled. If the OEB pin is high, the output data driver and dco are in a high impedance state. This OEB function is not intended for fast access to the data bus. Note that OEB refers to the digital output driver supply (DRVDD) and should not exceed this supply voltage.

When using SPI, the data output and DCO for each channel can be independently asserted up to three by using the output enable bar bit (bit 4) in Register 0x14.

opportunity

The AD9258 provides latched data with a pipeline delay of 12 clock cycles. The data output is available one propagation delay (t) after the rising edge of the clock signal.

The length and loading of the output data lines should be minimized to reduce transients within the AD9258. These transients degrade the dynamic performance of the converter.

The minimum typical conversion rate of the AD9258 is 10 msec/sec. Dynamic performance degrades when the clock rate is lower than 10ms/sec.

Data Clock Out (DCO)

The AD9258 provides two data clock output (DCO) signals for capturing data in external registers. In CMOS output mode, the data output is valid on the rising edge of the DCO, unless the DCO clock polarity has been changed via the SPI. In LVDS output mode, the DCO and data output swap edges are tightly aligned. Additional delay can be added to the DCO output to increase the data setup time using SPI Register 0x17. In this case, channel A output data is valid on the rising edge of the DCO, and channel B output data is valid on the falling edge of the DCO. See Figure 2, Figure 3, and Figure 4 for graphical timing descriptions of output modes.

Built-in Self-Test (BIST) and Output Test

The AD9258 includes built-in test functions designed to verify the integrity of each channel and facilitate board-level debugging. A BIST (Built-In Self-Test) function is included to verify the integrity of the AD9258's digital datapath. Various output test options are also provided to place predictable values on the outputs of the AD9258.

Built-in Self-Test (BIST)

BIST is a thorough test of the digital portion of the selected AD9258 signal path. When enabled, the test is run from an internal pseudorandom noise (PN) source through the digital datapath starting from the ADC block output. The BIST sequence runs for 512 cycles and stops. The BIST signature value for Channel A or Channel B is placed in Register 0x24 and Register 0x25. If a channel is selected, its BIST signature will be written to both registers. If two channels are selected, the result of channel A will be placed in the BIST signature register.

During the test, the output is not disconnected, so the PN sequence can be observed at runtime. The PN sequence can continue from its last value or reset from the beginning according to the value programmed in Register 0x0E, Bit 2. BIST signature results vary by channel configuration.

output test mode

The output test options are shown in Table 17. When the output test mode is enabled, the analog portion of the ADC is disconnected from the digital backend block, and the test mode runs through the output formatting block. Some test patterns are bound by the output format, and some are not bound by the output format. The seed value for the PN sequence test can be forced if the PN reset bit is used to hold the generator in reset mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encoded clock. For more information, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

Serial Port Interface (SPI)

The AD9258 serial port interface (SPI) allows the user to configure the converter for a specific function or operation through the structured register space provided within the ADC. SPI provides users with additional flexibility and customization, depending on the application. The address is accessed through the serial port and can be written or read through the port. Memory is organized into bytes, which can be further divided into fields, which are recorded in the memory-mapped section. For detailed operational information, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

Configuration using SPI

Three pins define the SPI:SCLK/DFS pins of this ADC

SDIO/DCS pin and CSB pin. SCLK/DFS (serial clock) is used to synchronize the read and write data of the ADC. SDIO/DCS (Serial Data Input/Output) is a dual purpose pin that allows data to be sent to and read from the internal ADC memory mapped registers. CSB (chip select bar) is an active low control that enables or disables read and write cycles.

The falling edge of CSB and the rising edge of SCLK together determine the start of the frame. Examples of sequence timing and its definitions can be found in Figure 84 and Table 5.

Other modes involving CSB are also available. When CSB is held low indefinitely (this will permanently enable the device), this is called streaming. CSB can be suspended high between bytes to allow for additional external timing. When CSB is tied high, the SPI function is put into high impedance mode. This mode enables any SPI pin auxiliary functions. In the command phase, a 16-bit command is sent. The data follows the instruction phase and its length is determined by the W0 and W1 bits.

Data Input/Output (SDIO) pin used to change the input direction to the output direction at the appropriate point in the serial frame.

All data consists of 8-bit words. Data can be sent in MSBfirst mode or LSB first mode. MSB first is the default value at power-on and can be changed through the SPI port configuration registers. For more information on this and other features, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

In addition to word length, the instruction stage determines whether the serial frame is a read or write operation, allowing the serial port to be used to program the chip and read the contents of on-chip memory. The first bit of the first byte in a multibyte serial data transfer frame indicates whether to issue a read or write command.

hardware interface

The pins described in Table 14 comprise the physical interface between the user programming device and the serial port of the AD9258. When using SPI, the SCLK pin and the CSB pin are used as inputs. The SDIO pins are bidirectional and act as inputs during the write phase and as outputs during readback.

SPI is flexible enough to be controlled by FPGAs or microcontrollers. One method of SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Bootstrap Circuits.

The SPI port should not be active during periods when full dynamic performance of the converter is required. Since the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise on these signals can degrade converter performance. If the onboard SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9258 to prevent these signals from transitioning at the converter inputs during critical sampling.

When the SPI is not used, some pins have dual functions. When pins are tied to AVDD or ground during device power-up, they are associated with specific functions. The Digital Outputs section describes the bundleable functions supported by the AD9258.

Configuration without SPI

In applications that do not interface with the SPI control registers, the SDIO/DCS pins, SCLK/DFS pins, OEB pins, and PDWN pins are used as separate CMOS compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for duty cycle stabilizer, output data format, output enable, and power-down feature control. In this mode, the CSB chip select strip should be connected to AVDD, which will disable the serial port interface.

When the device is in SPI mode, the PDWN and OEB pins remain active. For SPI control of output enable and power down, the OEB and PDWN pins should be set to their default states.

SPI accessible functions

Table 16 briefly describes the general features accessible through the SPI. These features are described in detail in the AN-877 application note, which interfaces to high-speed ADCs via SPI. Part-specific features of the AD9258 are described in detail under Table 17 (External Memory Mapped Register Table).

memory map

Read Memory Mapped Register Table

Each row in the memory-mapped register table has eight bit positions. The memory map is roughly divided into four parts: chip configuration registers (address 0x00 to address 0x02); channel index and transfer registers (address 0x05 and address 0xFF); ADC function registers, including setup, control and test (address 0x08 to address 0x30) ;Digital Characteristic Control Register (Address 0x100).

The Memory Mapped Register Table (see Table 17) lists the default hex value for each hex address shown. Columns with header bit 7 (MSB) are the start of the given default hex value. For example, address 0x18 (the VREF select register) has a default hex value of 0xC0. This means that bit 7=1, bit 6=1, and the remaining bits are 0. This setting is the default reference selection setting. Default uses 2.0 V pp reference. For more information on this and other features, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI. This application note details the functions controlled by Register 0x00 to Register 0xFF. The remaining register 0x100 is recorded in the Memory Mapped Register Table section.

open location

All addresses and bit positions not included in Table 17 are not currently supported by this device. Unused bits in valid address locations should be written with 0. These locations only need to be written if part of the address location is open (for example, address 0x18). If the entire address location is open (for example, address 0x13), this address location should not be written.

Defaults

After the AD9258 is reset, the key registers are loaded with default values. The default values for the registers are given in Table 17 of the Memory Mapped Registers.

logic level

Logic level terms are explained as follows:

(1), "Bit is set" is synonymous with "Bit is set to Logic 1", or "A logic 1 is being programmed for a bit."

(2) "Clear a bit" is synonymous with "bit is set to Logic 0", or "A logic 0 is being written to the bit."

transfer register map

Address 0x08 to address 0x18 and address 0x30 are hidden. Writing to these addresses does not affect part of the operation until a transfer command is issued by writing 0x01 to address 0xFF and setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. Internal updates occur when the transfer bit is set and the bit is automatically cleared.

channel-specific registers

Certain channel setup functions, such as signal monitor thresholds, can be programmed differently for each channel. In these cases, the channel address location is repeated inside each channel. These registers and bits are designated as local in Table 17. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, subsequent writes affect the registers of both channels. During a read cycle, only channel A or channel B should be set to read one of the two registers. This section returns the value of channel A if both bits are set during the SPI read cycle. Registers and bits designated as global in Table 17 affect the entire section or channel characteristics, independent settings are not allowed between channels. The settings in Register 0x05 do not affect global registers and bits.

Memory Mapped Register Description

For more information on the functions of Register 0x00 controls to Register 0xFF, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

Synchronization Control (Register 0x100)

Bit 2 clock divider, next sync only

If the Master Sync Enable bit (Address 0x100, Bit 0) and the Clock Divider Sync Enable bit (Address 0x100, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and ignore the rest . The clock divider synchronization enable bit (Address 0x100, Bit 1) resets after synchronization.

Bit 1 Clock Splitter Sync Enable

Bit 1 gates the sync pulse to the clock divider. When bit 1 is high and bit 0 is high, the sync signal is enabled. This is continuous sync mode.

Bit 0 Master Sync Enable

Bit 0 must be high to enable any synchronization functions. If synchronization is not used, this bit should be kept low to save power.

application information

Design Guidelines

Before beginning to design and lay out the AD9258 as a system, designers are advised to familiarize themselves with these guidelines, which discuss the special circuit connections and layout requirements required for certain pins.

Power and Grounding Recommendations

When connecting power supplies to the AD9258, two separate 1.8 V supplies are recommended. Use one analog supply (AVDD); use a separate digital output supply (DRVDD). For AVDD and DRVDD, several different decoupling capacitors should be used to cover high and low frequencies. Place these capacitors close to the PCB layer entry points and part pins, and minimize trace lengths.

when using

9258 AD. Optimum performance is easily achieved with proper decoupling and intelligent partitioning of the analog, digital and clock sections of the PCB.

LVDS operation

The AD9258 defaults to CMOS output mode at power-up. If LVDS operation is required, this mode must be programmed using the SPI configuration registers after power-up. When the AD9258 is powered up in CMOS mode with LVDS termination resistors (100Ω) on the output, the DRVDD current may be higher than typical until the part is placed in LVDS mode. This additional DRVDD current will not cause damage to the AD9258, but it should be taken into account when considering the maximum DRVDD current for this part.

To avoid this additional DRVDD current, the AD9258 output can be disabled at power-up by setting the OEB pin high. After placing the part in LVDS mode via the SPI port, the OEB pin can be brought low to enable the output.

Exposed Blade Hot Slug Recommendations

For best electrical and thermal performance, the exposed paddle on the bottom of the ADC must be connected to analog ground (AGND). A continuous, exposed (no solder mask) copper plane on the PCB should match the exposed paddle (pin 0) of the AD9258.

The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation through the bottom of the PCB. These vias should be filled or plugged to prevent solder from passing through the vias and affecting the connection.

To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen overlay should be applied to divide the continuous plane on the PCB into several uniform sections. This provides several connection points between the ADC and the PCB during reflow. Using a continuous plane with no partitions ensures that there is only one connection point between the ADC and the PCB. For more information on packaging and PCB layout for chip scale packages, see AN-772 Application Note, Design and Manufacturing Guidelines for Lead Frame Chip Scale Packages (LFCSPs), available at .

VCM

A 0.1µF capacitor should be used to separate the VCM pin from ground, as shown in Figure 67.

RBIAS

The AD9258 requires a 10 kΩ resistor to be placed between the RBIAS pin and ground. This resistor sets the primary current reference for the ADC core and should have a tolerance of at least 1%.

Reference decoupling

The VREF pin should be externally decoupled to ground in parallel with a low ESR, 1.0µF capacitor and a low ESR, 0.1µF ceramic capacitor.

SPI port

The SPI port should not be active during periods when full dynamic performance of the converter is required. Since the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise on these signals can degrade converter performance. If the onboard SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9258 to prevent these signals from transitioning at the converter inputs during critical sampling.

Dimensions