illustrate

Avago's 2.5 Amp integrated gate drive optocoupler mismatch detection and fault status feedback make IGBT VCE fault protection compact, affordable and easy to implement while meeting global safety and regulatory requirements.

feature

2.5 Current Max Peak Output Drive IGBT to IC= 150A , VCE=1200V Optical Isolation, Fault Status Feedback SO-16 Package CMOS/TTL Compatible Max Switching Speed 500 ns

Features (continued)

"Soft" IGBT off

Integrated fail-safe IGBT protection

Demineralization (VCE) detection

Under Voltage Lockout Protection (UVLO)

hysteresis

User Configurable: Reverse, Non-Reverse, Auto Reset, Auto Shutdown

Wide operating voltage control range: 15 to 30 volts

-40°C to +100°C operating temperature range

15 kV/µs Minimum Common Mode Rejection (CMR)

VCM=1500V Regulatory Approvals: UL, CSA, IEC/EN/DIN EN 60747-5-5 (1414V peak working voltage)

Typical Fault Protection IGBT Gate Drive Circuit HCPL-316J is an easy-to-use smart gate driver which makes IGBT-VCE fault protection compact, inexpensive and easy to implement. User-configurable inputs, integrated VCE detection, under-voltage age lockout (UVLO), "soft" IGBT turn-off and isolated fault feedback provide maximum design flexibility and circuit protection.

Operating Instructions in Fault State

1.DESAT terminal through DDESAT.

2. When the voltage on the desalination terminal exceeds 7V, the IGBT gate voltage (VOUT) decreases slowly.

3. The fault output goes low, notifying the microcontroller of a fault condition.

4. The microcontroller takes appropriate action.

output control

The output of the HCPL-316J (VOUT and FAULT) is determined by VIN, UVLO and the detected IGBT desalination condition. The HCPL-316J can be configured as inverting or non-inverting using the VIN+ or VIN- inputs, respectively, as shown in the table below. When the configuration needs to be reversed, VIN+ must be held high and text- toggled. When the non-reversing configuration is required, the VIN- must be held low and the VIN+ switch toggled. Once UVLO is inactive (VCC2-VE>VUVLO), VOUT is allowed to rise and the HCPL-316J will be the main source of IGBT protection. UVLO is required to ensure the functionality of DESAT. Once VUVLO+>11.6 V, desalting will remain functional until VUVLO-<12.4 V. Therefore, desalting detection and UV low-e feature HCPL-316J work together to ensure constant IGBT protection.

product description

The HCPL-316J is a highly integrated power control unit that integrates a complete, isolated IGBT gate drive circuit with fault protection and feedback in one SO-16 package. TTL input logic levels allow direct interface with microcontrollers, an opto-isolated power output stage drives IGBTs rated up to 150 A and 1200 VA High-speed internal optical links minimize propagation delays between microcontroller and IGBTs at the same time Allows two systems to operate over a very wide range of common-mode voltage differences for industrial motor drives and other power switching applications. The output IC protects the IGBT from damage during overcurrent, and the second optical link provides a fully isolated feedback signal for the fault state microcontroller. A built-in "watchdog" circuit monitors the power stage supply voltage to prevent IGBTs caused by insufficient gate drive voltage. This integrated IGBT gate driver is designed to increase the cost, size and complexity of discrete designs for the performance and reliability of brushless DC motors. Two LEDs and two integrated circuits are packaged in the same SO-16 package, providing input control circuitry, output power stage and two optical channels. The input buffer chip is designed by bipolar process, and the output detection chip is designed by bipolar process and manufactured on high-voltage BiCMOS/power DMOS. The forward optical signal path, such as LED1, sends the gate control signal. As indicated by LED2, the return optical signal path transmits the fault status feedback signal. The two optical channels are completely controlled by the input and output chips, making the internal isolation boundary transparent to the microcontroller. During normal operation, the input gate control signal directly controls the IGBT gate detector IC through the isolated output. LED2 remains off and the fault latch in the input buffer IC is disabled. When an IGBT failure is detected, the output detector IC immediately begins a "soft" shutdown sequence, inducing overvoltage in a controlled manner that avoids potential damage to the IGBT. At the same time, this fault status is communicated back to the input buffer IC via LED2, where the fault latch disables the gate control input and the active low fault output alerts the microcontroller. During power-up, an under-voltage lockout (UVLO) function prevents insufficient gate voltage to the IGBT by forcing the output of the HCPL-316J low. Once the output is high, the HCPL-316J's demineralization (VCE) detection feature provides IGBT protection. Therefore, UVLO and DESAT work together to provide constant IGBT protection.

notes:

1. According to UL1577, each optocoupler is verified by applying insulation test voltage ≥6000 Vrms for 1 second. This test is carried out before the partial discharge 100% production test (method b) shown in the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics table, if applicable.

2. The input and output instantaneous withstand voltage is the dielectric voltage rating and should not be interpreted as the input and output continuous rated voltage. For continuous voltage ratings, refer to your equipment-level safety specifications or the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics table.

3. The device is considered a two-terminal device: pins 1-8 are shorted together and pins 9-16 are shorted together.

4. To achieve the specified absolute maximum power dissipation, pins 4, 9 and 10 require a ground connection and may be required. airflow. For details on how to estimate junction temperature and power dissipation, see the Thermal Models section in the application note at the end of this datasheet. In most cases, the absolute maximum output IC junction temperature is the limiting factor. The actual power achievable losses depend on the application environment (PCB layout, airflow, part placement, etc.). See the Layout section in the Recommended PCB Application Notes for layout considerations. When the temperature is higher than 90°C, the power dissipation of the output IC decreases linearly at 10 mW/°C. Input IC power consumption does not require derating.

5. Maximum pulse width = 10 s, maximum duty cycle = 0.2%. This value is intended to account for component tolerance peak min = 2.0 A for designs with IO. See the application section for more details on peak IOH. Derate linearly from 3.0 A at +25°C to 2.5 A at +100°C. This compensates for the increased IOPEAK due to volume temperature changes.

6. This supply is optional. Only required when implementing negative gate drive.

7. Maximum pulse width = 50 s, maximum duty cycle = 0.5%.

8. See the section "Slow IGBT gate discharge under fault conditions" in the application note at the end of this datasheet for details.

9.15 V is the recommended minimum operating positive supply voltage (Vcc2-VE) to ensure sufficient margin over the maximum VUVLO + threshold of 13.5 V. For high-level output voltage testing, VoH is measured with DC load current. When driving capacitive loads it will approach VCC as IOH approaches zero units.

10. Maximum pulse width = 1 ms, maximum duty cycle = 20%.

11. Once the VOUT of the HCPL-316J goes high (VCC2-VE>VUVLO), the desalination detection feature of the HCPL-316J will be the main source of IGBT protection. UVLO is required to ensure the functionality of DESAT. Once VUVLO+>11.6 V, desalting will remain functional until VUVLO-<12.4 V. Therefore, the desalination detection and UV LO characteristics of HCPL-316J work together to ensure constant IGBT protection.

12. See the Blanking Time Control section in the Application Notes at the end of this data sheet for details.

13. This is the "increase" (ie open or "forward" direction) of VCC2-VE.

14. This is the "falling" (i.e. off or "negative" direction) of VCC2-VE.

15. This load condition approximates the gate load of a 1200 V/75 A IGBT.

16. For any given unit, the pulse width distortion (PWD) is defined as |tPHL-tPLH|.

17. Measured from VIN+, VIN- to VOUT.

18. Difference between tPHL and tPLH between any two HCPL-316J parts under the same experimental conditions.

19. Supply voltage related.

20. This is the amount of time from when the desalination threshold is exceeded until the fault output goes low.

21. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low and the fault output goes low.

22. This is the amount of time from when reset is asserted low until the fault output goes high. The 3µs minimum specification is the guaranteed minimum fault signal pulse width when the HCPL-316J is configured for automatic reset. Please see the Auto reset section in the application note at the end of this data sheet for more details.

23. Common mode transient immunity at high state is maximum tolerable. dVCM/dt of the common mode pulse VCM to ensure that the output will remain high (ie VO > 15v or fault > 2v). 3KΩ pull-up resistors are required for 100 pF and fault detection modes.

24. Common mode transient immunity in low state is the maximum tolerable DVCM/dt of the common mode pulsed VCM to ensure that the output will remain in the low state (ie VO < 1.0V or fault < 0.8V).

25. Does not include LED2 current at fault or blanking capacitor discharge current.

26. To clamp the output voltage on VCC-3vbe, it is recommended to install a pull-down resistor between the output and VEE to sink a quiescent current of 650 microamps when the output is high. If the output pull-down resistor is

Typical Application/Operation Introduction to Fault Detection and Protection The power stage of a typical three-phase inverter is susceptible to several faults, most of which are potentially damaging to the power IGBTs. These failure modes can be grouped into four basic categories: stage and/or rail supply shorts or poor wiring due to incorrect user connections, control signal failures due to noise or calculation errors, and load and component failures in the gate drive circuit. In any kind of fault condition, the IGBTs will increase rapidly, resulting in excessive power dissipation and heating. IGBT damage occurs when the current load is close to the saturation current of the device, and the collector to emitter voltage is above the saturation voltage level. A radically increased power consumption can quickly overheat the powerplant and destroy it. To prevent damage, fault protection must be implemented to reduce or shut down overcurrent in fault conditions. Circuits that provide fast local fault detection and shutdown are ideal solutions, but the required components, board space consumption, cost, and complexity have so far limited their application to high performance. drive. This circuit must have high speed, low cost, low resolution, low power consumption, and small size. Application Information The HCPL-316J meets these standards by combining high speed, high output current drivers, high voltage opto-isolated outputs between the inputs, in-place IGBT desaturation detection and shutdown down, an opto-isolated fault status feedback signal into a 16-pin Surface mount package. The fault detection method used, HCPL-316J, monitors the saturation (collector) voltage of the IGBT and triggers a local fault shutdown sequence threshold when the collector voltage exceeds a predetermined value. A small gate bleeder prevents damage to high short-circuit IGBT current and voltage spikes. Before the dissipated energy reaches a destructive level, the IGBT is turned off. During the rest period in the state of the IGBT, the fault detection circuit is simply disabled to prevent false "fault" signals. Alternative protection schemes for measuring IGBTs. If shorted, the current to prevent desaturation is effective. The circuit capability of the power supply device is known, but this method will fail if the gate drive voltage is reduced by only partially turning on the IGBT. By directly measuring the collector voltage, the HCPL-316J limits the power loss gate drive voltage of the IGBT. Another more subtle advantage of desaturation detection methods is monitoring power dissipation in the IGBT, while current detection methods rely on preset current thresholds to predict safe limits of operation. Therefore, an over-conservative overcurrent threshold is not required to protect the IGBT

Recommended application circuit

The HCPL-316J has both inverting and non-inverting gate control inputs, an active low reset input, and an open collector fault output for wired or wired applications. The recommended application circuit diagram shown in shows a typical gate driver implementation using the HCPL-316J. Four supply bypass capacitors (0.1µF) provide the large transient current transitions required during switching. Due to the transient nature of the charging current, a low current (5mA) supply is sufficient. The desalting diode and 100 pF capacitor are necessary external components of the fault detection circuit. The gate resistor (10Ω) is used to limit the gate charging current and indirectly control when the IGBT collector voltage rises and falls. Open collector fault output passive 3.3 kΩ pull-up resistor and 330 pF filter capacitor. A 47 kΩ pull-down resistor on VOUT provides a more predictable high-level output voltage (VOH). In this application, when a fault is detected, a reset signal is applied in the microcontroller.

Operation/Timing Instructions

Figure 63 below shows the input and output waveforms under normal operating conditions, desalination fault conditions and normal reset behavior. Normal Operation During normal operation, the VOUT of the HCPL-316J is controlled by VIN+ or VIN-, and the IGBT collector output voltage is monitored by DDESAT. The fault output is high and the reset input should be kept high. See Figure 63. Figure 63. Timing diagram. Fault state When the voltage on the desalting pin exceeds 7V, the IGBT is turned on, and VOUT is lowered slowly to "gently" turn off the IGBT and prevent large di/dt induced voltages. The internal feedback channel is also activated to make the fault output low, in order to inform the microcontroller of the fault condition. See Figure 63. The reset fault output remains low until reset low. See Figure 63. When asserting the reset pin (low), the input pin (VIN+LOW or VIN-HIGH) must be asserted for the output low state. This can be achieved through software control (ie a microcontroller) or hardware control (see Figures 73 and 74).

Slow IGBT gate discharge on faults The device in the HCPL-316J output driver stage will turn on a "gentle" turn off the IGBT when a desaturation fault is detected. This device discharges slowly to prevent voltage spikes and wire inductances caused by lead that can cause voltage spikes at the gate of the IGBT with rapid changes in drain current. During slow-off the output pull-down device remains off until the output voltage falls below V+2 volts, at which point the pull-down device clamps the IGBT gate to turn it around. Demineralization fault detection blanking time The demineralization system fault detection circuit must remain disabled for a short time after the IGBT is energized to allow the collector voltage to drop below the demineralizer seth hold. This time period, called the desalting blanking time, is controlled by the internal desalting charging current, the desalting voltage threshold and the external desalting capacitor. The nominal blanking time is calculated as tBLANK=CBLANK x VDESAT/ICHG for the external capacitance (CBLANK), fault threshold voltage (VDESAT) and desalting charge current (ICHG). The recommended discharge time for a 100 pF capacitor is 100 pF*7V/250µA = 2.8µs. The capacitor value can be scaled slightly to adjust the blanking time, but values less than 100 pF are not recommended. This nominal feed time also represents the maximum time required for the HCPL-316J to respond to a desalination failure. If the collector and transmitter are shorted (switched to short) to the supply rails, the soft turn-off sequence will begin after approx. 3 microseconds. If the IGBT collector and emitter respond to the supply rails after the IGBT has been turned on due to parasitic paralleling, the time will be much faster to desalt the capacitance of the diode. The recommended 100pF capacitor should also provide sufficient blanking as fault response time for most applications. Under-Voltage Lockout The HCPL-316J Under-Voltage Lockout (UVLO) function is to prevent under-gating by forcing the HCPL-316J to output a low voltage to the IGBT during power-up. igbts typically require a gate voltage to reach their rated VCE (on) voltage. At gate voltages below 13 volts, its energization voltage typically rises dramatically, especially under higher ocean currents. With very low gate voltages (below 10 V), the IGBT can overheat quickly and in the linear region. The UVLO function enables the output to be clamped using operating power (VCC2) when insufficient. Once VCC2 exceeds VUVLO+ (the positive UVLO threshold), the UVLO releases the clamp to turn on the device output in response to the input signal. As VCC2 increases from 0 V (somewhat below VUVLO+), first the desalting protection circuit kicks in. As VCC2 increases further (above VUVLO+), release the Vvlo clamp. Desalination protection is already active when the UVLO clamp is released. Therefore, the UVLO and DESAT tomographic detection functions together provide seamless protection regardless of supply voltage (VCC2)

Behavioral Circuit Schematic

The functional behavior of HCPL-316J is represented by the logic diagram in Figure 64 which fully describes HCPL-316J. The input IC is in normal switching mode, no output fault is detected, and the low state of the fault latch allows the input signal to control the signal LED. The fault output is in the open collector state and the reset state pin does not affect the control of the IGBT gate. When a fault is detected, the fault output and signal input are both latched. The fault output becomes active low and the signal LED is forced off (output low). This locked state will last low until the reset pin is pulled out. Figure 64. Behavioral circuit schematic. Output IC Three internal signals control the state of the driver output: the state of the signal LED, and the UVLO and fault signals. If no fault on the IGBT collector is detected and the supply voltage is above the UVLO threshold, the LED signal will control the driver output state. This driver stage logic includes an interlock to ensure that the pull-up and pull-down devices in the output stage are never turned on at the same time. If the voltage is too low if detected, the output will be 50x DMOS device regardless of LED state. If the IGBT detects a desaturation fault when the signal LED is on, the fault signal will be latched high. The triple Darlington and 50x DMOS devices are disabled, and the smaller 1x DMO pull-down device is activated to slowly unload the IGBT gate. When the output drops below two volts, the 50xdmos device turns on again, firmly clamping the IGBT gate to turn it. The fault signal remains latched in a high state until the signal LED goes out.

Other recommended components

The application circuit in Figure 62 includes an output pull-down resistor, desalting pin protection resistor, a fault pin capacitor (330 pF), and a fault pin pull-up resistor. Output Pull-Down Resistor During the output high transition, the output voltage rises rapidly into the 3 diodes of VCC2. If the output then drops to zero current due to capacitive loading, the output voltage will slowly rise from approximately VCC2-3(VBE) to VCC2 in a few microseconds. To limit the output voltage of VCC2-3 (VBE), a pull-down resistor is recommended between the output and VEE for a quiescent current of 650µA when the output is high. The pull-down resistor value depends on the positive power supply, according to the formula, r pull-down = [VCC2-3*(VBE)]/650 microamps. The desalting pin protects the flyback diode of free-turning IGBTs with large transient forward voltages that greatly exceed the nominal forward transient diode voltage. This can cause a large negative voltage spike on the desalination pin, which will draw a lot of current from the IC if protection is not used. To limit the current level without damaging the IC, a 100 ohm resistor should be inserted in series with the desalting diode. The added resistance does not change the desalination threshold or desalination blanking time. The capacitor on the high CMR fault pin fast common mode transients can affect the pin voltage when the fault fault output is in the high state. A 330pF capacitor (Figure 66) should be connected at the fault pin and ground to achieve sufficient CMOS noise margin at a specified CMR value of 15kV/µs. The added capacitance does not increase the fault output delay when a desaturation condition is detected. Pull-Up Resistor on Fault Pin The fault pin is an open collector output, so a pull-up resistor is required to provide a high signal. Capacitive coupling of high CMR isolation with standard CMOS/TTL driving of high voltage and input related circuits is the main circuit CMR limit. Consideration must be given to achieving high CMR performance. Input pins VIN+ and VIN- must have active drive signals to prevent unwanted signal-pole common-mode output switching transient conditions. Input driver circuits that use pull-ups or pull-down resistors, such as open collector configurations, should be avoided. A standard CMOS or TTL driver circuit is recommended.

User-configured VIN+, VIN-, FAULT, and RESET input pins on the HCPL-316J input allow various gate control and fault configurations depending on the motor drive requirements. The HCPL-316J has both inverting and non-inverting gate control inputs for open collector fault outputs for wired or active low reset inputs. Non-inverting/inverting drive input pf HCPL-316J mode The gate drive voltage output of the HCPL-316J model can use the VIN- and VIN+ inputs. As shown in Figure 68, when a non-inverted configuration is required, VIN+ can be toggled by keeping the VIN low by connecting it to GND1. As shown in Figure 69, when the configuration needs to be reversed, by connecting VIN+ to VCC1, VIN+ is held high, and switched. Local Shutdown, Local Reset As shown in Figure 70, the fault outputs of each HCPL-316J gate driver are polled individually, and a single reset line is individually asserted low to reset the motor controller after a fault. Global Shutdown, Global Reset As shown in Figure 71, when configured for reverse operation, the HCPL-316J can be configured to shut down the fault automatically by tying the output to VIN+ in the event of a fault. For high reliability drives the open collector fault outputs of each HCPL-316J can be connected together on a common fault bus to form a single fault bus directly connected to the microcontroller. When a fault is detected in any of the six gate drivers, the fault output signal disables all six HCPL-316J gates while providing protection against further catastrophic failure.