HIP9011 is used to provide a method of detecting early detonations commonly referred to as "hit or hit" internal combustion engines. The integrated circuit is shown in a simplified block diagram. The chip can choose between two sensors for precise monitoring or a "V" motor if desired. Internal control over the SPI bus is fast enough on each transmit cycle. Programmable bandpass filters process signals from either sensor input. This selectable bandpass filter optimizes the extraction of background noise from the knock or knock signal from the engine. Further single processing is done by full-wave rectification of the filtered signal and its application of an integrator whose output voltage level corresponds to the amplitude of the knock signal. The chip is under the control of the microprocessor via the SPI interface bus.

Add "T" suffix for tape and reel.

Note: Intersil lead-free + annealed products feature a special lead-free material set; molding compound/mold join material and 100 % matte tinplate finish, RoHS compliant and compatible with SnPb and lead-free soldering operations. Intersil's lead-free products are classified as MSLs that meet or exceed the lead-free requirements for temperature IPC/JEDEC J Standard-020 during lead-free peak reflow soldering.

feature

Two sensor inputs

microprocessor programmable

Accurate and stable filter element

Digitally programmable gain

Digitally programmable time constant

Digitally Programmable Filter Characteristics

On-chip crystal oscillator

Programmable divider

External clock frequencies up to 24MHz - 4, 5, 6, 8, 10, 12, 16, 20 and 24MHz

Operating temperature range -40oC to 125oC

Lead-free plus annealed (RoHS compliant) available

application

Engine Knock Detector Processor

Analog Signal Processing of Controllable Filters

need feature

Note:

1. θJA is measured in free air with components mounted on the evaluation PC board

Electrical Specifications VDD=5V±5%, GND=0V, Clock Frequency 4MHz±0.1%, TA=-40oC to 125oC, unless otherwise specified

Electrical Specifications VDD=5V±5%, GND=0V, Clock Frequency 4MHz±0.1%, TA=-40oC to 125oC, unless otherwise specified (continued)

notes:

2.Q=fo/BW, where: fo=center frequency, BW=3dB bandwidth

3. Ideal equation: INTOUT (volts)=[VIN*GIN*GPR*GBPF*1/π*(N/tC(ms)*fQ(kHz))*GDSE]+VRESET where: VIN=input signal amplitude ( VP-P) GIN=external input gain; GIN=RF/RINGPR=programmed gain GBPF=bandpass filter gain (center ideally 2) tINT=integration time; tINT=N/fQ0.318=1/πN= The number of cycles of the input signal fQ = the frequency of the input signal RF = the feedback resistance value RIN = the signal input resistance value tC = the programming time constant GDSE = the gain of the DSE converter (ideally 2) VRESET = the integrator reset voltage = 0.125V , typ.

HIP9011 Operation Description This integrated circuit is designed as a general purpose digitally controlled analog circuit interface between an engine acoustic sensor or accelerometer and an internal combustion engine fuel management system. Two wideband input amplifiers are provided, allowing the use of two sensors. These sensors are piezoelectric and can be installed in the optimal location for keyed engine configurations. The outputs of these input amps are routed to a channel select mux switch and then into a third-order antialiasing filter. The output signal is then directed to two programmable gain stages, one of which inverts or shifts the knock signal 180 degrees. The gain stage signal is output to two programmable bandpass filter stages. The output BPF stages of both are full-wave rectified by programmable integrators before being digitized. The integrator output is applied to the line driver for the engine fuel management control system. The gain, bandpass filter and integrator stage settings can be sequenced by a microprocessor broadband piezoelectric ceramic transducer interfaced via the SPI bus, the device capacitance of the engine signal sensor is 1100pF, and the output voltage range is 5mV to 8V rms. During normal engine operation, a single input selects the channel and applies to the HIP9011. The amplitude of engine background noise is usually much lower than the noise before knocking. Therefore, the bandpass filter can optimize the stage to further differentiate the engine background noise, combustion noise and pre-shock noise. The basic approach of an engine pre-knock system is to observe the engine background only for the time interval where noise is expected, and if detected, delay the timing. This basic approach does not require selective solutions for sensitivity and continuous tunability. Improved fuel economy and performance A controlled fuel management system is obtained when the integrated circuit is coupled to a microprocessor.

Circuit block description

Input Amplifiers Choose from two amplifiers to connect sensors to the engine. These amplifiers have a typical open-loop gain of 100dB and a typical bandwidth of 2.6MHz. The common man mode input voltage range extends to the supply rails. The amplifier outputs have similar output ranges. Sufficient gain, bandwidth and output swing capability are provided to ensure that the amplifier can handle attenuation gain settings of 20 to 1 or -26dB. This would be required when a high peak output signal is obtained, at 8VRMS from the sensor. Gain is set when the sensor has an output level of 5mVRMS. In a typical application, the input signal frequency may vary from 1kHz to 20kHz. External capacitors are used to disconnect the IC from the sensors (C1 and C2) see diagram. The typical value of the capacitor is 3.3nF. The series input resistors R1 and R2 are used to connect the inverting inputs of the amplifier (pins 19 and 16) and feedback resistors R3 and R4, along with R3 and R4 are used to set the gain of the amplifier. The intermediate voltage levels are generated inside the integrated circuit. This level is set halfway between VDD and ground. Throughout the integrated circuit, this level is used as a quiet DC reference voltage for signal processing circuits within the integrated circuit. This is for several reasons, it can be used as a reference voltage and must be bypassed to ensure a quiet reference for internal circuits. Input amplifiers are functions designed to be powered down, and when activated, disable their bias circuits and their outputs go into a tri-state state. This is used during diagnostic mode, where the terminals of the output amplifier are externally driven with various test signals. The antialiasing filter IC has a 3rd order Butterworth filter with its 3dB point at 70kHz. Double polycapacitors and injection resistors are used to set the pole in the filter. This filter requires no attenuation of more than 1dB at 20kHz (highest frequency off interest) and a minimum attenuation of 10dB at 180kHz. This filter is located at the system frequency of 200kHz before the switched capacitor filter stage.

Programmable Gain Stage

The gain of two identical programmable gain stages can be adjusted so that knock energy is compensated if necessary. This adjustment is available with 64 different gain settings ranging from 2 to 0.111. The signal can swing from 20% to 80% of VDD. The programming protocol section is discussed in SPI Communication. Programmable Bandpass Filters Two identical programmable filters are used to detect frequencies of interest. A Band Pass Filter (BPF) is programmed to pass the frequency components of the engine to knock. The filter frequency is determined by the characteristics of the specific engine and sensor. By integrating these two filters on the rectified output stage of the integrator, if knocking occurs, it can be detected. The nominal differential gain of the filter is 4. Their frequency is set by a programmable word (in the SPI communication protocol section) The center frequency is programmable from 1.22kHz to 19.98kHz, in 64 steps. The filter Qs is typically 2.4. The output of the active full-wave rectifier band-pass filter is a unity-gain buffer prior to full-wave rectification using switched capacitor technology. Each side of the rectifier circuit provides negative and knock frequency bandpass frequency positive filtered outputs. The output can swing from 20% to 80% with respect to VDD. Take care to minimize the input to output of this stage. Programmable integrator stage The signal from the rectifier stage is split into two output terminals and then integrated into a signal path. Differential systems are used to minimize noise. One side integrates the positive energy value from the knock frequency rectifier. The second side is the integral value of negative energy. Positive and negative energy signals are opposite phase signals. Using this technique reduces system noise without affecting the actual signal. The integrator time constant is programmed by the software. The integration time constant is in the communication protocol section. The time constant can be programmed from 40 microseconds to 600 microseconds for a total of 32 steps. If, for example, we programmed the time constant to be 200 microseconds, then a voltage difference integrator between each channel would change in volts in 200 microseconds.

The integrated signal input/hold is enabled by the rising edge of the input control. The output of the integrator will drop approximately VRSET, 0.125V, within 20 microseconds of the integrated input reaching a logic high level. The integrator is an analog voltage. Differential Single-Ended Converter This circuit takes the differential output of the integrator (by testing the multiplexing circuit) and provides a signal which is the sum of the two signals. This technique is used to improve the noise immunity of the system. Output Buffer This output amplifier is combined with the input amplifier for interfacing with the sensor. This amplifier is in power-down mode in order to when the output of the anti-aliasing filter is evaluated. Test Multiplexer This circuit receives the output from the integrator, as well as from the different parts on the integrated circuit. The test Mux outputs the programming word of the communication protocol controlled by the fifth party. This multiplexed switched capacitor filter output, gain control output and anti-alias filter output. The SPI communication protocol communicates with the knock sensor (Moses) via the SPI bus. The chip select pin (CS) is used to enable the chip, which in conjunction with the SPI clock (SCK) shifts an eight-bit programming word. Five different programming words are used to set the following internal programmable registers: gain, bandpass frequency filter, integrator time constant, channel selection, so output mode and test mode. When the chip select (CS) goes low, the data is latched into the SPI register at the SPI clock (SCK). The data is shifted with the most significant bit first and the least significant bit last. Each word is divided into two parts: the first part address and value. Depending on when the function is controlled, the address is 2 or 3 bits and the value is 5 or 6 bits long. All five programming words can be entered into the IC in hold mode of operation. This integrated or hold mode of operation is controlled by the input/hold signal.

programming words

1. Bandpass Filter Frequency: Defines the frequency of the bandpass filter in the center system. The first 2 bits are used for the address and the last 6 bits are used for its value. 00FFFFFF example: 00001010 would be the value of 10 in Table 3 for a bandpass filter with a center frequency of 1.78kHz (bit).

2. Gain Control: Defines the value of the gain stage gain setting attenuation. The first 2 bits again use the address and the value of the last 6 bits. 10ggggg example: 10010100 would be the gain control (10 for the first two digits) with an attenuation of 0.739 (the median value in Table 3 is 20).

3. Integrator time constant: A constant that defines the integrator time system. The first 3 bits are used for the last 5 bits of the address and value. 110t example: 11000011 would be the integrator time constant (110 for the first 3 bits) and an integration time constant of 55 microseconds (bit value 3 in Table 3).

4. Test/channel selection control: input the first three bits again, 111 is the address of this function, and the last five bits define the programmable function. Example: 111B4B3B2B1B0; options are: A) If B0 is "0", select channel 0. If B0 is "1"; select channel 1 as input.

B) The remaining bits are used to select the diagnostic mode. test pin(14) = low. Not applicable in run mode.

5. Prescaler/SO terminal status: define the internal frequency prescaler and its status terminal, pin 11. P1 to P4 bit definitions can be used with an external clock. The state is tri-stated, so the pin is set by the last Z bit. 01P5P4P3P2P1Z; example: 0100000, note that bit P5 is not used in this example. (The 01 of the first 2 bits sets the prescaler/SO function) P1 to P4 set the prescaler frequency of the clock to 4MHz, and the last bit sets the S0 terminal to an active state.

The digital SPI block diagram in the figure shows the chip programming flow. Octet at the international airport. when the chip is enabled by the CS pin. The word is a decoding circuit that decodes by address, and the information is directed to 5 registers. These registers control the following chip functions:

1. Bandpass filter frequency.

2. Gain control or decay.

3. Correct the integral time constant of the BPF output.

4. Prescaler.

5. Test/Channel selection.

a) Test conditions for the part.

b) Channel selection to one of the two input amplifiers. A crystal oscillator circuit is provided. The chip needs to have at least one 4MHz crystal through OSCIN and a broken pin. An external 4MHz signal can also be supplied to pin 9 of the OSCIN terminal. In diagnostic mode, we can use the digital multiplexer to output one of the following results through the SO pin (11):

1. The value of one of the five registers in the chip

2. Buffered value of SI pin (12).

3. The value signal of the internal comparator used to correct the analog quantity The digital SPI filter is located in the SPI block, which provides a pseudo-noise immunity characteristic. Digital SPI filter operation requires that SCK be low before CS falls, followed by 8 SCK pulses (low-high-low transition). When SCK ends a pulse train with a logic low condition, a low-to-high transition of CS will cause the data word in the SPI buffer to be loaded into the correctly addressed programmable register. In integrated mode, the INT/HOLD pin is high, any if the conditions of the digital SPI filter are met. Digital SPI filter only allows to accept 8 bits per word