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2022-09-15 14:32:14
OPA2652 is dual, 700MHz, voltage feedback computing amplifier
Features
Broadband buffer: 700MHz, g u003d+1
Broadband line drive: 200MHz, G u003d+2
High-output current: 140mA
Low power current: 5.5mA/CH
Super Small packaging: SOT23-8
Low DG/Dφ: 0.05%/0.03 °
High conversion rate: 335V/microsecond
Power voltage: ± 3V to ± 6V
Application
A/D drive
Consumer video
]
pulse delay circuit
low cost upgrade to AD8056 or EL2210
Instructions
OPA2652 is a double path, low cost, low cost , Broadband voltage feedback amplifier, for price -sensitive applications. It is characterized by a high -gain bandwidth product of 200MHz under the 5.5mA/channel static current. It is suitable for running on the ± 5V power supply, and it also supports a single power supply from+6V to+12V, and the output current is 140mA. Its classic differential input and voltage feedback design can be widely used in active filters, integrations, cross -resistance largers and differential receivers.OPA2652 internal compensation has the stability of unit gain. It has a special bandwidth (700MHz) as a unit gain buffer and has almost no peak (0DB typical values). Under the input bias voltage of 1.5MV and the input bias current of 300NA, excellent DC accuracy is achieved.
Related Products
Packaging/Order Information
(1), related For the latest software packages and order information, see the software package options at the end of this document. 
TA u003d+25 ° C, G+2, RF u003d 402 , RL u003d 100 See Figure 28 and Figure 29.
Application information 
Broadband voltage FeedbackOperation 
OPA2652 is a dual low -power broadband voltage feedback amplifier. Each channel has internal compensation to provide unit gain stability. OPA265 full -symmetrical feedback structure input. This architecture will minimize the offset error, making OPA2652 very suitable for the design of filter and instrument. As a dual -computing amplifier, OPA2652 is an ideal choice. The design requires multiple channels to reduce the key of circuit board space, power consumption and cost. It optimizes the communication performance to provide a 200MHz gain bandwidth and the rapid rise of 2.0ns. This is an important consideration for high -speed data conversion. The low -current input offset of ± 1.5mv and the drift support high accuracy requirements of ± 5 μV/° C. In applications that require higher conversion rates and broader bandwidth, such as video and high -bit rate digital communication, consider dual current feedback OPA2694 or OPA2691.
FIG. 28 shows the characteristics of DC coupling +2 gain dual -power circuit configuration features as ± 5V specifications and typical values. This configuration is for a channel. Another channel connection is similar. For the purpose of testing, the input impedance is used to set the input impedance to 50 , and the output impedance is used to set the output impedance to 50
The voltage fluctuation reported in the specification is obtained directly at the input and output pin, and the output power (DBM) is loaded at the matched 50 In the circuit in FIG. 28, the total effective load will be 100 | | 804 . Figure 28 includes two optional components.
The additional resistor (174 ) is connected in series with non -swap input. Coupled with 25 DC source resistance, looking back at the signal generator, this additional resistance provides an input bias current offset the resistance, which is matched with the 201 DC accuracy and offset control part). In addition to the usual power supply container, the two power pins also include a 0.1 μF capacitor. In the actual printing circuit board (PCB) layout, this optional additional capacitor can usually increase the two harmonic distortion performance by 3 dB to 6 dB.
FIG. 29 shows the configuration of DC coupling bipolar supply circuit configuration of -1, which is the basis of the specifications and typical characteristics of G u003d -1. The input load of 50 the input load of the input impedance matching resistor (57.6 ). The resistor (205 ) will not be exchanged to the input ground. This configuration provides a DC resistance matching to eliminate the output error caused by the input bias current.
Differential ADC drive
HomepageThe circuit shows an OPA2652 Drive ADS807 modulus converter (ADC) with a gain of+2V/V. The output is coupled to the converter to adapt to the difference in power supply voltage. The 133 #8486 of the non -conversion input terminal is minimized to minimize DC offset error differential topology to minimize the even -order distortion products, such as second harmonic distortion.
Tongtong filter
FIG. 31 shows an OPA2652 that realizes the six -order passing filter. The filter -level two -tier SALLEN key segment and a double pole segment with zero -point transmission. It has a ripple of 0.3DB, 450kHz and 11MHz -3DB frequencies, 315kHz and 16MHz -23DB frequency. 20.0 The resistor isolates the first OPA2652 output to the capacitance load. This configuration improves stability and has the minimum effect on the filter response. Figure 30 shows the nominal response of the SPICE simulation.
Video cable driver
FIG. 32 shows OPA2652 for the video cable driver. Its excellent differential gain and phase allows it to be used for recording room equipment, and its low cost and SOT23-8 packaging options also support consumer applications. 
pulse delay circuit
FIG. 33 shows OPA2652 used for pulse delay circuits. This circuit will connect the two operational amplifiers in OPA2652, and each operational amplifier forms a single -acting -active full -pass filter. The total gain is +1, and the total delay of the filter is:
TGD u003d N (2RC), the total group delay
n u003d 2, the number of levels of the class
]
RF and RG need to be equal to maintain a constant gain. TR (in) of the input pulse rising and decreased time should be slow enough to prevent pre -filge pseudohadows in the response.
TR (IN) ≥5RC, minimum pre -shooting 
The simple passing filter is shown in Figure 34. OPA2652 is very suitable for this type of circuit because it is very stable at +1 noise gain.
Design Tools
Demonstration fixed device 
Demonstration device is requested on the Dharis instrument website through the OPA2652 product folder.
Macro model and application support 
Operation suggestion
Optimized resistance value
Since OPA2652 is a stable voltage feedback amplifier with a stable unit gain, feedback and gain setting resistors can use extensive resistance values. The main limitations of these values u200bu200bare set by dynamic range (noise and distortion) and parasitic capacitors. For irreversible unit gain follower applications, the feedback connection should use 25 resistors instead of direct short circuit. This configuration will isolate the inverter input capacitance from the output pins and improve the flat response flatness. Generally, the feedback resistance value should be between 200 and 1.5k . When it is less than 200 the feedback network will generate additional output loads, which will reduce the harmonic distortion performance of OPA2652. When more than 1.5k at the feedback resistance, typical parasitic capacitors (about 0.2pf) may cause the non -intentional bandwidth limit of the amplifier response.
A good rule of experience is to set the parallel combination of RF and RG (see Figure 28) to less than about 300 . The combination impedance RF | | RG interacts with inverter input capacitors, adding a pole to the feedback network, so that the positive response is zero. Assuming the parasitic 2PF on the reverse node, keep RF | | RG LT; 300 it can keep the pole above 250MHz. As far as it is concerned, this constraint means that the feedback resistance RF can increase to several K under high gain. As long as the parasitic capacitance formed by RF is not in the frequency range of interest, this increase is acceptable.
Bandwidth and gain: No reversal operation
As the signal gain increases, the closed bandwidth of the voltage feedback Territories gradually decreases. Theoretically, this relationship is described as a width bandwidth (GBP) displayed in the specification. Ideally, in addition to GBP, in addition to the gain without reversing signal (also known as noise gain, or NG), a closed -loop bandwidth can be predicted. In fact, this prediction is only established when the phase margin is close to 90 °, just like in a high -gain configuration. At low gain (increase feedback factor) In the lower, most amplifiers show a wider bandwidth and lower phase of phase. Compensation of OPA2652 has a flat response when the non -mutual gain is 1 (see Figure 28). The typical gain of this structure is a +1 bandwidth of 700MHz, which is far more than 200MHz GBP except the predictive value of Ng u003d 1. Increasing the gain is close to 90 °, and the bandwidth is closer to the predictive value (GBP/NG). When the gain is +5, the 45MHz bandwidth displayed in the electrical feature is similar to the bandwidth predicted with this simple formula.
Reverse amplifier operation
Because OPA2652 is a general broadband voltage feedback calculation amplifier, all familiar computing amplifiers application circuits are available for designers. Reversal operation is a more common requirement and provides several performance advantages. Figure 29 shows a typical reversal configuration.
In the reverse configuration, you must pay attention to three key design considerations. First, the gain resistance (RG) becomes part of the input impedance of the signal channel. If you need to input impedance matching (when the signal is coupled with cables, twisted wiring, long PCB trace lines, or other transmission wire conductors, this is beneficial), you can set RG to The required gain. This method is the simplest and can get the best bandwidth and noise performance. However, at low reverse gains, the feedback resistance value generated can provide an important load for the amplifier output. For -1 inverter gains, set RG to 50 for input matching, no RM, but a 50W feedback resistor is required. This structure has an interesting advantage, that is, for 50Ω source impedance, noise gain is equal to 2, which is the same as the non -conversion circuit considered above. However, the amplifier output is now seeing 50 the feedback resistance is connected in parallel with the external load. Generally, the feedback resistance should be limited to the range of 200 to 1.5k In this case, it is best to increase the RF and RG values u200bu200bat the same time, as shown in Figure 29 in the middle, and then use the third resistor (RM) to achieve the input matching impedance ground. The total input impedance becomes a parallel combination of RG and RM.
The second main consideration mentioned in the previous paragraph is that signal source impedance becomes part of the noise gain equation and affects the bandwidth. For the examples in FIG. 29, the RM value is combined with the external 50 the power impedance is combined with 50 | | 57.6 u003d 26.8 This impedance is connected in series with RG to calculate noise gain (NG). For FIG. 29, the NG obtained is 1.94 (the ideal source may cause ng u003d 2.00).
The third important consideration in the design of the inverter amplifier design is to set the bias current to eliminate the resistance on the non -rotated input terminal (RB). If the resistance is set to look out from the inverter nodeThe total DC resistance is reduced due to the input bias current (input offset current) RF. If the source impedance of 50 in Figure 29 is DC coupling, the total ground resistance on the reverse input will be 429 Paid it with the feedback resistor to get 208 , and the RB u003d 205 near Figure 29. To reduce additional high -frequency noise introduced by this resistor, it is sometimes bypass by a capacitor. As long as RB LT; 300 , there is no need for capacitors, because its total noise contribution is far less than the contribution of the input noise voltage of the computing amplifier.
Although the OPA2652 specification in the SPEC table is familiar in the industry, it considers voltage and current restrictions. In many applications, the voltage is more related to the circuit operation. See the output voltage and current limit diagram in the typical features. The X and Y axis of this figure show the zero voltage output current limit and zero current output voltage limit, respectively. These four quadrants give a more detailed view of the device output driving capacity. It notices that the figure is bounded by the safety operation area of u200bu200b1W's maximum internal power consumption (500MW per channel). When the output power does not exceed 2.5VΩ, the output power does not exceed 2.5V.
In order to maintain the maximum output level linearity, it does not provide short -circuit protection. This configuration is usually not a problem, because most applications include a series matching resistor on the output end. If the output side of the resistor is short -circuited, the internal power consumption is limited. However, in most cases, the output pins are directly connected to the adjacent positive power pins, which will damage the amplifier. Installing a small string of connected resistors (5 ) in the power cord can prevent this. Always put the 0.1 μF off -coupled container directly on the power pins.
Drive capacitance load
For the operator, one of the most common and most common load conditions is capacitance loading. Frequent capacitance load is an input terminal of analog-digital (A/D) converter, which includes additional external capacitors that can be used to improve A/D linearity. When the capacitance load is placed, a high -speed amplifier such as OPA2652 is easily due to decreased stability and the peak impact of closed -loop response directly on the output pin. When considering the opening resistance of the amplifier, this capacitance load will add a pole to the signal pathway to reduce the phase margin. Some people have proposed several external solutions to solve this problem. When the main consideration is frequency response flat, pulse response and/or distortion, the simplest and most effective solution is to insert a series isolation resistance between the output and capacitance load between the amplifier and the capacitance load. Sexual load is separated from feedback ring. This resistance does not eliminate the pole in the circuit response, but shifts it and adds a zero to a higher frequency. ZeroThe role is to eliminate the phase lag of the container characteristics, thereby increasing the phase of the pioneer and improving the stability.
The typical feature shows the recommended RS and the frequency response generated by the RS and capacitance loads and the frequency generated under the load. Parasitic capacitance load greater than 2PF will begin to reduce the performance of OPA2652. Long PCB trajectory, non -matching cables, and connections to multiple devices can easily exceed this value. Be sure to consider this impact carefully and bring the recommended series resistors as close to the OPA2652 output pins as much as possible (see the guidance guidelines of the circuit board layout).
distortion performance
OPA2652 provides good distortion performance under 100 #8486 at ± 5V power supply. Increased load impedance to directly improve distortion. Keep in mind that the total load includes the feedback network; in the non -reversing configuration (Figure 28), this is the sum of RF+RG, and in the reverse configuration, only RF. In addition, providing additional power supply -coupled capacitors (0.1 μF) (for bipolar operations) between power pins can slightly improve the second -order distortion (3DB to 6DB).
Increasing the output voltage swing will also increase the harmonic distortion.
Noise performance
OPA2652 Input reference voltage noise (8nv/√Hz) and two input reference current noise items (1.4Pa/√Hz), can be in various operating conditions Provide low output noise conditions. Figure 35 shows the noise analysis model containing all noise items. In this model, all noise items are considered noise voltage or current density items, and the unit is NV/√Hz or PA/√Hz.
The total output spots noise voltage can be calculated as a square root of all square output noise voltage contributors. Formula 1 shows the general form of the output noise voltage, as shown in Figure 35.
This expression divides this expression with noise gain (ng u003d 1+r to fine -tune the method, a key consideration is RF/RG) to obtain non -conversion inputs Equivalent input reference point noise voltage, as shown in equivalent 2.
The two equations of the OPA2652 circuit and component value in FIG. The noise voltage of the spots is 8.4nv/√Hz. The noise includes the bias current eliminating the resistance (205 ) the noise added to the input. The total input reference point noise voltage is only slightly higher than the 8NV/√Hz specification of the voltage noise of the operation amplifier. This is the case as long as the impedance restrictions that appear at each computing amplifier input at the previously recommended maximum value of 300 Keep (RF | | RG) and non -ease input source impedance less than300 , meet the consideration of noise and frequency response. Because the noise caused by the resistance is relatively negligible, the configuration of the inverter operation amplifier in Figure 29 does not need to eliminate the additional capacitor (RB) through the bias current.
DC accuracy and offset control 
ng u003d No reversing signal gain
Generally, you need to fine -tune the output offset or DC working point adjustment. There are many technologies to introduce DC offset control in the computing amplifier circuit. Most of these technologies increase DC current through feedback resistors. When selecting the method of mitigation and fine -tuning, a key consideration is the effect on the frequency response of the expectation signal path. If the signal path is non -reversible, it is best to use offset control as inversion and signal applications to avoid interaction with the signal source. If the signal path is reversed, you can consider the offset control of the input application of non -turbulent input. However, the DC offset voltage on the harmony will return the DC current to the power supply, which must be considered. For reverse computing amplifiers input application bias adjustment can change noise gain and frequency response flatness. For DC coupling inverters, FIG. 36 shows an example of the minimum offset adjustment technology that affects the signal frequency response. In this case, the DC offset current through the resistance values u200bu200bwith much greater signal channel resistance enter the inverter input node. This structure ensures the minimum impact of regulating circuits on the width rate, so it also has a minimum impact on the frequency response.
Heat analysis
Under extreme operating conditions, heat dissipation or forced airflow may be needed. The maximum expectation will set the maximum allowable internal power consumption as described below. In any case, the highest knot temperature must not exceed 175 ° C.
The working knot temperature (TJ) is given by TA+PD θJa. The total internal power consumption (PD) is the sum of the additional power consumed by static power (PDQ) and output (PDL). Static power is the specified air supply current multiplication by the total power supply voltage of the entire component. PDL depends on the required output signals and loads; for the ground resistance load, when the output is fixed at a voltage of 1/2 of the voltage of any power supply (for equal bipolar powerAt the time of), PDL is at the maximum value. Under this condition, PDL u003d vs2/(4 RL), where RL includes feedback network load.
Note that the power consumption of the internal power is the output level, not the load.
For example, the maximum TJ is calculated using OPA2652E (SOT23-8 packaging) in FIG. ;load.
This absolute and worst situation meets the highest knot temperature in line with the regulations. The actual PDL is almost smaller than the value here. Consider the maximum TJ in the application.
Circuit plate layout guide
To obtain the best performance and high -frequency amplifier, such as OPA2652 needs to pay close attention to the plate layout parasitic and external component types. Suggestions for optimization include:
A), minimize the parasitic capacitance of all signal I/O pins to any communication to the minimum. The parasitic capacitor on the output end and the inverter input pins will cause instability: in the non -rotating input, it will react with the source impedance, which will cause unintentional limits. In order to reduce unnecessary capacitors, the window around the signal I/O pin should be opened on all ground and power plane. Otherwise, ground and power aircraft should be uninterrupted elsewhere on the ship.
B), minimize the distance between the power pins to the high frequency 0.1 μF decoupled capacitor ( lt; 0.25 ""). At the equipment pin, the ground layout of the grounding and power supply should not be close to the signal I I /O pin. Avoid narrow power and ground traces, to minimize the inductance between the coupling capacitors. The power connection should always be decoupled with these capacitors. The decoupled capacitor (0.1 μF) will improve the second harmonic distortion performance. The decoupling capacitor with larger (2.2 μF to 6.8 μF) is effective at low frequency and is also used on the main power. These capacitors can be placed on the departure device. A little farther, and can be shared between multiple devices in the same area of u200bu200bPCB.
C), carefully selection and placing the external components will maintain the high frequency performance of OPA2652. The resistor should be extremely low -power resistance. Type. The surface installation of the resistor is the best and allows a closer overall layout. Metal film or carbon component axial hypertrophic resistor can also provide good high -frequency again. . In high -frequency applications, do not use a wire winding resistor. Since the output pins and inverter input pins are the most sensitive to parasitic capacitors, the feedback and series output resistors (if so) should be as close as possible to as close as possible to as close to as possible Output pins. Other network components, such as non -rotating input terminal connecting resistors, should also be placed near the package. If double -sided components are allowed to be installed, the feedback resistor will be placed directly on the other side of the board on the other side of the board.Below the package, between the output end and the reverse input pin. Even when the low -parasitic capacitor diversion the external resistor, the high resistance value will generate significant time constant, thereby reducing performance. A good axial metal film or surface installation of the resistor and the resistor to connect the parallel resistance of about 0.2pf. For the resistance value gt; 1.5k , the parasitic capacitor can add a pole and/or zero to the circuit operation below 500 MHz. Keep the resistance value as low as possible to meet load driving considerations. 402 #8486 used in typical performance specifications; feedback is a good starting point for design. Note that it is recommended to use 25 feedback resistor instead of direct short circuit, for uniform gain follower applications. This effectively isolates the reverse input capacitance from the output pins, otherwise it will cause the additional peak value of the +1 frequency response gain gain.
D), the connection to other broadband devices on the board can be performed through a short direct record or through the board transmission line. For short connections, the input of tracking and to the next device is considered as a concentrated capacitor load. A relatively wide trace line (50 to 100 mils) should be used, and it is best to open the ground and power aircraft around it. It is estimated that the total capacitance load is estimated, and RS is set according to the recommended RS and capacitance load (Figure 17). Low parasitic capacitance load ( lt; 5PF) may not require RS, because OPA2652 is named for compensation, and can work under 2PF parasitic load. When the signal gain increases (increasing the load phase margin), if a long trace line is required, and the 6DB signal loss inherent in the double -end transmission line is acceptable, it allows a higher parasitic capacitor load of RS without RS, and uses micro -bands to use micro -bands. The line or strip -like wire technology implements the matching impedance transmission line (see the ECL design manual of the microstructure and the line layout technology). 50 environment does not need to be on the ship. In fact, a higher impedance environment will improve distortion, such as distortion and load charts. In the case of defining the characteristic circuit board tracking impedance (based on circuit board materials and trace lines), the matching string resistor from OPA2652 output to tracking, and the use of the diversion resistor at the end of the target device input end. It is also necessary to remember that terminal impedance will be a parallel combination of parallel resistance and target equipment input impedance; total effective impedance should be set to match the tracking impedance. OPA2652's high output voltage and current capabilities allow multiple destinations to process multiple destinations as separate transmission cables, each with its own series and parallel ending. If the 6DB attenuation of the dual -end transmission line is unacceptable, the long record can only be connected in series at the source end. In this case, the trajectory is regarded as a capacitance load and a series resistance value is set, as shown in the relationship diagram of the proposed RS and the capacitance load (Figure 17). This configuration will not maintain signal integrity like a double -end line. If the input impedance of the destination device is low, due to the pressure of the sterilizer formed by the series output to enter the terminal impedance, there will be some signal attenuation.
E), noIt is recommended to put high -speed parts like OPA2652.The additional lead length and capacitance between the sockets will produce a very troublesome parasitic network, which is almost impossible to achieve smooth and stable frequency response.OPA2652 is directly welded to the circuit board to get the best results.
Input and ESD Protection
OPA2652 is made of very high -speed complementary bipolar crafts.For these very small geometric devices, the internal cutting voltage is relatively low.These segments are reflected in the absolute maximum rating table.As shown in Figure 37, all device pins are protected by the internal ESD to protect the power supply.
These diode provides moderate protection to input over -drive voltage higher than the power supply.Protecting diode can usually support 30mA continuous current.If there may be a higher current (for example, in a system that is driven by ± 15V power components to OPA2652), adding string linter resistors should be added to two input terminals.Keep these resistance as low as possible because high value will reduce noise performance and frequency response.