illustrate

Available in 8-pin dip or SO-8 package types respectively, the HCPL-7710 or HCPL-0710 optocouplers utilize the latest CMOS integrated circuit technology to achieve excellent performance with extremely low power consumption. The HCPL-x710 requires only two bypass capacitors to be fully CMOS compatible. The basic building blocks of the HCPL-x710 are the CMOS LED driver chip, high-speed LED and CMOS detector integrated circuits. A CMOS logic input signal controls the LED driver IC to supply current to the LEDs. The detector IC integrates an integrated photodiode transconductance amplifier and voltage comparator with an output driver.

Pin 3 is the anode of the internal LED and must be left unconnected for datasheet performance. Pin 7 is not connected internally. A 0.1µF bypass capacitor must be connected between pins 1 and 4, and between pins 5 and 8.

feature

+5 V CMOS compatibility

8 ns maximum pulse width distortion 20 ns maximum strut. Latency Deviation High Speed: 12 Mbd 40 ns max strut. Delay 10 kV/µs Minimum Common Mode Rejection -40°C to 100°C Temperature Range Safety and Regulatory Approvals UL Recognized per UL 1577, 3750 Vrms for 1 minute per UL 1577 (HCPL-7710), 5000 Vrms for 1 minute 1 minute option 020) CSA Component Acceptance Notice #5 IEC/EN/DIN Standard EN60747-5-5

– For HCPL-7710 option 060, VIORM=630 V peak

–VIORM=567 V peak for HCPL-0710 option 060

application

Digital Fieldbus Isolation: DeviceNet, SDS, Profibus

AC plasma display panel moves horizontally

multiplex data transmission

computer peripheral interface

Microprocessor System Interface

Reflow Soldering Thermal Profile

Recommended reflow conditions are in accordance with JEDEC Standard J-STD-020 (latest edition). Non-halide fluxes should be used.

Regulatory Information

HCPL-x710 has been approved by: UL Recognition According to UL 1577, Component Identification Program, File E55361. CSA approved under CSA Component Acceptance Notice 5, Document CA 88324. IEC/EN/DIN standard EN60747-5-5

All Avago datasheets report leakage and clearance inherent in the optocoupler assembly itself. These dimensions are the starting point that equipment designers need when determining circuit insulation requirements. However, once installed on a printed circuit board, minimum creepage and clearance requirements must be met for individual equipment standards. For creepage, the shortest distance path along the surface of the print must account for the board between the input and output lead solder fillets. Techniques such as grooves and ribs are suggested, which can be used on printed circuit boards to achieve the required creepage performance and clearance. Creepage distances and clearance distances also depend on the degree of pollution and insulation level.

Electrical Specifications

Unspecified test conditions can be anywhere within the recommended operating range. All typical specifications are TA=+25°C, VDD1=VDD2=+5 V.

notes:

1. When VI When VI is high.

2. tPHL propagation delay is the signal measured from the 50% level of the falling edge of VI to the 50% level of the falling edge of the VO signal. The tPLH propagation delay is the signal measured from the 50% level of the rising edge of VI to the 50% level of the rising edge of the VO signal.

3. MIMIMUM pulse width is the shortest pulse width, which can guarantee 10% maximum pulse width distortion. The maximum data rate is the inverse of the minimum pulse width. Operating the HCPL-x710 at data rates higher than 12.5 MBd is possible where PWD and data are correlated, in applications where jitter increases and relaxed noise margins can be tolerated. For example, if the maximum allowable variation in bit width is 30%, the maximum data rate becomes 37.5 mbar. Note: Avago does not guarantee the performance of the HCPL-x710 above 12.5MBd.

4.PWD is defined as |tPHL-tPLH|. %PWD (Percent Pulse Width Distortion) is equal to PWD divided by the pulse width.

5. tPSK is equal to the recommended operating conditions for the worst case difference in tPHL and/or tPLH between units over a given temperature range.

6.CMH is the maximum common mode voltage slew rate that can be maintained while maintaining VO>0.8 VDD2. CML is the greatest common denominator to maintain the mode voltage slew rate while maintaining VO < 0.8V. The common-mode voltage slew rate applies to rising and falling common-mode voltage edges.

7. The no-load dynamic power consumption is calculated as follows: CPD*VDD2*f+IDD*VDD, where f is the switching frequency in MHz.

8. A device that is considered a two-terminal device: pins 1, 2, 3, and 4 are shorted together, and pins 5, 6, 7, and 8 are shorted together.

9. According to UL1577, each HCPL-0710 is proof tested by applying insulation test voltage ≥4500 VRMS for 1 second (leakage detection current limit, II-O≤5μA). Each HCPL-7710 is proof tested by applying insulation test voltage ≥ 4500 VRMS for 1 second (leakage detection current limit, II-O ≤ 5 μA).

10. The input and output instantaneous withstand voltage is the dielectric voltage rating and should not be interpreted as the input and output continuous rated voltage. For continuous voltage ratings, see Equipment Level Safety Specifications or Avago Application Note 1074 "Optocoupler Input Output Continuous Voltage."

11. Competitive intelligence is the capacitance measured at pin 2 (VI)

application information

Bypass and PC board layout The HCPL-x710 optocoupler is very easy to use. No external interface circuitry is required because the HCPL-x710 uses high-speed CMOS integrated circuit technology, allowing CMOS logic to be directly connected to the inputs and outputs. As shown, the only external components required for proper operation are two bypass capacitors. The capacitor value should be between 0.01µF and 0.1µF. For each capacitor, the total lead length between the two capacitor ends and the power supply pins must not exceed 20 mm. Figure illustrates the recommended printed circuit board layout for the HPCL-x710.

Propagation Delay, Pulse Width Distortion, and Propagation Delay Deviation Propagation delay is an advantage that describes the speed at which logic signals travel through a system. This low-to-high propagation delay (tPLH) is the propagation of the input signal to the output, causing the output to go from low to high. Similarly, the high-to-low propagation delay (tPHL) is the amount of time it takes for the input signal to propagate to the output, making the output go from high to low. See Fig.

Pulse Width Distortion (PWD) is TPHL and TPLH and usually determines the rate capability of the maximum data transfer system. PWD can be divided by PWD (ns) by the minimum pulse width of the transmission (unit: ns). Typically, a PWD of 20-30% of the minimum pulse width is acceptable. The PWD specification for the HCPL-X710 is 8 ns (10%) maximum under recommended operating conditions. The 10% command maximum is based on the strictest of the three fieldbus standards, Fieldbus. Propagation delay skew is an important parameter to consider In parallel data applications, signal synchronization on parallel data lines is an issue. If parallel data is sent through a set of optocouplers, differences in propagation delay will result in different epochs of data arriving at the optocoupler output. If the difference in propagation delay is large enough, it will determine the maximum rate. Which parallel data can be sent through the optocoupler. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays of TPLH or TPHL for any given group. Optocoupler conditions that operate under the same conditions (ie, same drive current, supply voltage, output load, and operating temperature). As shown in the figure, if the inputs of a set of optocouplers are turned on or off at the same time, the difference between the shortest propagation delay in tPSK, whether it is tPLH or tPHL, and the longest propagation delay, tPLH or tPHL as mentioned earlier , TPSK can determine the maximum value. Parallel data transfer rate. Figure is a diagram of a typical parallel data application with clock and data lines sent through optocouplers. This figure shows the input and output of an optocoupler. In this case the data slave clock is assumed.

The propagation delay slope represents the uncertainty of where an edge might be after it is sent through the optocoupler. The diagram shows that both the data line and the clock line are indeterminate. These two fields of uncertainty cannot overlap; otherwise, the clock signal may have settled before the data output, or some of the data output may have started changing before the clock signal has arrived. From these considerations in parallel applications, the minimum pulse width that can be sent through an optocoupler is twice tPSK. A prudent design should use a slightly longer pulse width to ensure that the rest of the circuit does not cause a malfunction. The HCPL-x710 optocouplers have guaranteed specifications for propagation delay, pulse width distortion and propagation delay deviation over recommended temperature and power supply ranges.

Digital Fieldbus Communication Networks Until now, despite its many shortcomings, the 4-20 mA analog current loop has been widely accepted as the standard for process control system implementation. However, in today's manufacturing environment, automated systems are expected to help manage the process, not just monitor it. With the advent of digital fieldbus communication networks such as DeviceNet, Fieldbus, and Intelligent Distributed Systems (SDS), the days of limited information are gone. The controller can now receive multiple readouts (sensors, actuators, etc.) as well as diagnostic information from the field. The physical model communication network of these digital fieldbuses is very similar, as shown in Fig. Each includes one or more buses, an interface unit, optical isolation, transceivers, and sensing and/or actuation means.

Optical Isolation of Fieldbus Networks To fully realize the benefits of these networks, Avago recommends using optocouplers to provide galvanic isolation. Because network communication is bidirectional (including receiving and transmitting data two Avago optocouplers are required. By providing galvanic isolation, data integrity is muffled and spurious signals are suppressed. Additionally, network reception is maximized. Protection against power system faults and ground loops. The Within an isolated node, such as a device network node, as shown in the figure, some components of the node refer to the ground outside the V- of the network. Figure. Typical Fieldbus Communication Physical Model These components can include devices such as serial ports, parallel ports, etc. , RS-232 and RS-485 type ports. As shown, power from the network is for transceivers and optocouplers only. Isolation of nodes connected to any of the three types uses HCPL-x710 optocouplers. For each network the HCPL-x710 meets critical propagation delay and pulse width distortion requirements over a temperature range of 0°C to +85°C, as well as a supply voltage range of 4.5V to 5.5V.

When the HCPL-x710 is used to implement DeviceNet and SDS with transmission rates up to 1 Mbit/s, the two DeviceNet SDSs are based on the same broadcast-oriented communication protocol - Controller Area Network (CAN). Three types of orphan nodes are recommended on these networks: orphan nodes powered by the network (Figure 19), standalone nodes using network-powered transceivers (Figure 20), and standalone nodes powered by the network (Figure 21). Figure 18. A typical device network node. Figure 19. Network-Powered Standalone Nodes Network-Powered Standalone Nodes This type of node is very flexible, as shown in the figure. Figure 19 is considered "isolated" because the components have the same ground reference. However, all components are still powered by the network. This node contains two supervisors: one is independent for the controller, node-specific application and isolates (nodes) the two optocoupler edges, and the other is non-isolated. A non-isolated regulator provides the transceiver and two optocouplers.

Network-Powered Standalone Node with Transceiver Figure 20 shows that a node powered by two networks has another source of information. In this case, the transceiver and the isolated (network) side of the two optocouplers are powered by the network. The rest of the node is powered by the AC line, where the application requires a lot of power. This method is also ideal because it does not overload the network. What's more, the unique "double inversion" design ensures that the network does not "lock up" if the node's AC line power is lost or the node shuts down. Specifically, when the input power (VDD1) to the HCPL-x710 located in the transmission path is excluded, the recessive bus state is ensured as the HCPL-x710 output voltage (VO) is too high. *Bus V+ Sense recommends the Bus V+ Sense block shown in Figure 20 for implementation. A locally powered node attempts to transmit if an unpowered isolated PHY. The bus V+ sense signal will be used to change the BOI property of the DeviceNet object to the "auto reset" (01) value. See Volume 1, Section 5.5.3. This will cause the node to keep resetting until power is detected by the bus. Once a power supply is detected the BOI property will return to the "hold in bus off" (00) value. The BOI attribute should not be left at the "auto reset" (01) value, as this would break the jabber protection function of the CAN error limit. Any inexpensive low frequency opto-isolator can be used to achieve this.

Independent Nodes Powering the Network Figure 21 shows the supply network. The AC line powers the regulator, which provides local 5 V. The AC line also feeds the isolated 24V power supply, which powers the network, plus a 5V regulator, which in turn is the isolated (network) side of the transceiver and two optocouplers. This is powerful when there are a number of unwanted devices on a network, thus eliminating the power source. What's more, the unique "double inversion" design ensures that the network does not "lock up" if the node's AC line power is lost or the node shuts down. Specifically, when the input power (VDD1) to the HCPL-x710 located in the transmission path is excluded, the recessive bus state is ensured as the HCPL-x710 output voltage (VO) is too high.

Power and Bypass

The recommended DeviceNet application circuit is shown in Figure 22. Since the HCPL-x710 is fully compatible with CMOS logic level signals, the optocoupler is directly connected to the CAN transceiver. Double bypass capacitors (values between 0.01 and 0.1µF) are required and should be placed as close as possible to the input and output power pins of the HCPLx710. For each capacitor, there should be no more than 20 mm across the capacitor and power pins. The bypass capacitor is due to its high-speed digital nature of the signal inside the optocoupler.

Implementing PROFIBUS with HCPL-x710 PROFIBUS, short for Process Field Bus, is essentially a twisted pair serial link, very similar to RS-485, capable of implementing up to 12 mm wide. As shown in Figure 23, a PROFIBUS controller (PBC) establishes the connection of field automation units (control or central processing stations) or field devices to the transmission medium. PBOC includes line transceiver, optical isolation, frame characteristic transmitter/receiver (UART) and FDL/APP processor to interface with PROFIBUS users.

Power and Bypass

The recommended PROFIBUS application circuit is as shown in Figure 24. Since the HCPL-x710 is fully compatible with CMOS logic level signals, the optocoupler is directly connected to the transceiver. Double bypass capacitors (values between 0.01 and 0.1µF) are required and should be placed as close as possible to the input and output power pins of the HCPLx710. For each capacitor, there should be no more than 20 mm across the capacitor and power pins. The bypass capacitor is due to its high-speed digital nature of the signal inside the optocoupler. Much like a multi-drop RS485 system, the HCPL-061N optocoupler provides transmit disable enabling the bus during each master/slave transmit cycle. Specifically the HCPL-061N disables the transmitter of the line driver putting it in high state mode. In addition, the HCPL-061N switches the RX/TX driver IC to listening mode. The HCPL-061N offers HCMO compatibility and high CMR performance (1 kV/µs at VCM=1000 V) essential in industrial communication interfaces.