illustrate

HCPL-4504 and HCPL-0454 contain a GaAs LED while HCPL- J454 and HCNW4504 contain AlGaAs LEDs. The LED is optically coupled to an integrated high-gain photodetector. The HCPL-4504 series has short propagation delay and high centering. The HCPL-4504 series also has a difference in propagation delay (tPLH-tPHL). These features make the HCPL-4504 series an excellent solution for IPM switching problems such as inverter dead time. The CTR, propagation delay and CMR are all specified to provide TTL and IPM conditions for ease of application. These single-channel diode-transistor optocouplers are available in 8-pin DIP, SO-8, and wide-body package configurations. Insulation layer LEDs and integrated photodetectors provide isolation between input and output. Separate connections for photodiode bias and output transistor collectors increase speed to a conventional phototransistor coupler base collector capacitance.

feature

Short propagation delay for TTL and IPM applications Minimum common-mode transient immunity is 15 kV/µs at VCM= 1500 V for TTL/load drive High CTR at TA=25°C

>25% for HCPL-4504/0454

>23% for HCNW4504

>19% for HCPL-J454

Electrical Specifications for General Purpose IPM Applications

TTL compatible

Open collector output

Safety Approvals: UL Recognized – 3750 V rms/1min for HCPL-4504/0454/J454 – For HCPL-4504 Option 020 and HCNW4504 Type CSA Approved IEC/EN/DIN EN 60747-5-2

– For HCPL-0454 option 060, VIORM = 560 V peak

– For HCPL-4504 option 060, VIORM=630 V peak

– For HCPL-J454, VIORM = 891 V peak

– For HCNW4504, VIORM=1414 V peak

application

Inverter Circuits and Intelligent Power Modules (IPMs)

Interface: High Common Mode Transient Immunity

(>10kV/µs for IPM loads/drivers) and (tPLH-tPHL) regulations (see Power Inverter Deadband section)

Line Receivers: Short Propagation Delay and Low Input-Output Capacitance

High-speed logic ground isolation: TTL/TTL, TTL/CMOS, TTL/LSTTL

Replacing pulse transformers: saving board space and weight

Analog Signal Ground Isolation: Integrated Photodetector Improves Phototransistor Linearity

To sort, select a part number from the Part Number column and combine the columns with the desired option in that option to form an order entry.

Example 1: HCPL-4504-560E Order 300 mil Dip Groove Air Mount Packaging Tape and Reel The product is IEC/EN/DIN EN 60747-5-2 safety certified and RoHS compliant.

Example 2: HCPL-4504 ordered in a 300 mil tube dip package and non-RoHS compliant. An option data sheet is available. Please contact your Avago sales representative or authorized reseller for information. Note: The symbol "xxx" is used for existing products, while (new) products have been introduced since July 15, 2001. RoHS compliant will use '-XXXE.

NOTE: Time from 25°C to maximum temperature = 8 minutes. Tsmax=200°C, Tsmin=150°C Note: Non-halide should be used. *Recommended peak temperature for body 400 mils package is 245°C

All Avago datasheets report the leakage and gaps inherent in the optocoupler assembly itself. These dimensions are the starting point requirements that equipment designers need when determining circuit insulation. However, once installed on a printed circuit board, minimum creepage and clearance requirements must be specified in accordance with individual equipment standards. Input and output leads must be considered on the printed circuit board along the shortest distance to the surface for creepage purposes. There are recommended techniques such as grooves and ribs that can be used on printed circuit boards to achieve the required creepage and clearance. Creepage distances and clearance distances also vary according to factors such as pollution degree, insulation class, etc.

Note: These optocouplers are only suitable for "safe electrical isolation" within the safety limit data. The maintenance of safety data is ensured through the protection circuit.

Note: Insulation characteristics conform to IEC/EN/DIN EN 60747-5-2.

Note: Surface mount is classified as Class A according to CECC 00802.

Packaging Features

Above recommended temperature (TA=0°C to 25°C) unless otherwise specified.

All typical values at TA=25°C. I/O instantaneous withstand voltage is a dielectric voltage rating and should not be interpreted as an I/O continuous rated voltage. For continuous voltage ratings, refer to IEC/EN/DIN EN 60747-5-2 Insulation-Related Characteristics Table (if applicable) Equipment Level Safety Specifications or Avago Application Note 1074 entitled "Optocoupler Input Output Continuous Voltage"

notes:

1. Linearly reduce the free air temperature above 70°C at a rate of 0.8 mA/°C (8-pin immersion). Linearly reduce the free air temperature above 85°C at a rate of 0.5 mA/degree Celsius (SO-8).

2. Linearly reduce the free air temperature above 70°C at a rate of 1.6 mA/degree Celsius (8-pin immersion). Linearly reduce the free air temperature above 85°C at a rate of 1.0 mA/degree Celsius (SO-8).

3. Linearly reduce the free air temperature above 70°C at a rate of 0.9 mW/°C (8 needle immersion). The free air temperature above 85°C was linearly decreased at a rate of 1.1 mW/°C (SO-8).

4. Linearly reduce the free air temperature above 70°C at a rate of 2.0 mW/°C (8 needle immersion). The free air temperature above 85°C was linearly decreased at a rate of 2.3 mW/°C (SO-8).

5. The current transfer ratio expressed as a percentage is defined as the ratio of the output collector current IO to the forward LED input current IF multiplied by 100.

6. A device that is considered a double-ended device: pins 1, 2, 3, and 4 are shorted together, and pins 5, 6, 7, and 8 are shorted together.

7. Under TTL load and drive conditions: Common mode transient immunity in logic high is the maximum tolerable (positive) DVCM/dt. Common mode pulses the leading edge of VCM to ensure that the output will remain in a logic high state (ie VO > 2.0v). Common-mode logic-low transient immunity is the maximum tolerable (negative) DVCM/dt, VCM, of the trailing edge of the common-mode pulse signal to ensure that the output will remain in a logic low state (ie, VO < 0.8 V).

8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity to logic high is maximum. Tolerable dVCM/dt on the leading edge of the common mode pulse (VCM) to ensure that the output will remain in a logic high state (ie VO > 3.0V) Yes. Common-mode transient immunity for logic low is the maximum tolerable DVCM/dt for the trailing edge of the common-mode pulse. signal, VCM, to ensure that the output will remain in a logic low state (ie, VO < 1.0V).

A 9.1.9kΩ load represents a 1.6ma TTL unit load and a 5.6kΩ pull-up resistor.

10. RL=20 kΩ, CL=100 pF load means IPM (Intelligent Power Module) load.

11. See option 020 data sheet for more information.

12. A 0.1µF bypass capacitor connected between Pin 5 and Pin 8 is recommended.

13. According to UL 1577, each optocoupler is verified by applying insulation test voltage ≥ 4500 V rms for 1 second (leak detection current limit, Ii-o ≤ 5 μA).

14. According to UL 1577, each optocoupler is verified by applying insulation test voltage ≥ 4500 V rms for 1 second (leak detection) current limit, Ii-o ≤ 5 μA).

15. According to UL 1577, each optocoupler is verified by applying insulation test voltage ≥ 6000 V rms for 1 second (leak detection current limit, Ii-o ≤ 5μA).

16. This test is performed prior to the 100% production test shown in the VDE 0884 Insulation-Related Characteristics table (if applicable).

17. Difference between tPLH and tPHL between any two devices (same part number) under the same test conditions. (See the Power Inverter Dead Time and Propagation Delay Specifications section.)

Power Inverter Dead Time and Propagation Delay Specifications HCPL-4504/0454/J454 and HCNW4504 include specifications designed to help designers minimize "dead time" in their power inverter designs. The new "Propagation Delay Difference" specification (tPLH-tPHL) is useful for determining not only how much optocoupler switching delay is required to prevent "shoot-through" current, but also for determining the best achievable worst-case dead zone for a given design time. When the inverter power transistors switch (Q1 and Q2 in the diagram), it is important that they are never at the same time. If there is an overlap in their conduction during switching transitions, it can damage the transistor and even the surrounding circuitry. This "shoot-through" current is eliminated by delaying the turn-on of one transistor (Q2) long enough to ensure that the reverse transistor (Q1) has fully turned off. This delay introduces an amount of "dead time" at the inverter output during switching transitions with both transistors off. Minimizing this dead time is an important design goal of the inverter designer. The amount of turn-on delay required depends on the propagation delay characteristics of the optocoupler and the characteristics of the transistor base/gate drive circuit. Considering only the optocoupler (the pedestal/gate drive characteristics of the circuit can be analyzed in the same way), it is important to know the minimum and maximum on-time (TPHL) turn-off (tPLH) propagation delay specifications, preferably at the desired operation within the temperature range. The significance of these specifications is shown in the waveforms labeled "LED1", "LED2", "OUT1", and "OUT2" are the input and output voltages of the optocoupler circuits that drive Q1 and Q2, respectively. Most inverters are designed so that the power transistor turns on when the optocoupler LED is on; this ensures that both power transistors will turn off losses in the control circuit when powered on. The inverter can also be designed so that the power transistors are turned off when the optocoupler LEDs are turned on; however, this design requires additional fail-safe circuitry to shut down the power transistors if an overcurrent condition is detected. The timing shown in this figure assumes that when the optocoupler LED is on, the transistor is on.