feature

Accurate rms-to-DC conversion from 50 Hz to 6 GHz Single-ended input dynamic range >50 dB; no balun or external input tuning required; waveform modulation independent RF power detection; linear decibel output, scale: 52 m Volts/dB; Log Consistency Error: <±0.15dB; Temperature Stability: <±0.5dB; Supply Voltage Range: 4.5 V to 5.5 V; Operating Temperature Range: -40°C to + 125 °C; Power Down to 1.5 MW; small footprint, 4 mm x 4 mm, LFCSP.

application

Power Amplifier Linearization/Control Loop; Multi-Standard, Multi-Carrier Wireless Infrastructure (MCGSM, CDMA, WCDMA, TD-SCDMA, WiMAX, LTE); Transmitter Power Control; Transmitter Signal Strength Indication (TSSI); RF Instrumentation.

General Instructions

The AD8363 is a true rms responding power detector that can be driven directly from a single-ended 50Ω supply. This feature makes the AD8363 frequency versatile, eliminating the need for a balun or any other form of external input tuning to operate up to 6 GHz.

The AD8363 provides accurate waveform-independent power measurements for a variety of high-frequency communication and instrumentation systems. It only needs a 5V power supply and a few capacitors, which is easy to use and has high measurement accuracy. The AD8363 operates from any low frequency to 6GHz and accepts inputs from less than -50 dBm to at least 0 dBm rms, with large crest factors exceeding WiMAX, CDMA, W-CDMA, TD-SCDMA, multi-carrier GSM and LTE requirements for accurate signal measurement.

The AD8363 can determine the true power of high frequency signals with complex low frequency modulation envelopes and can also be used as a simple low frequency rms voltmeter. By adding a capacitor to the CHPF pin, the high pass angle created by its internal bias zero loop can be reduced.

VOUT is connected to VSET as a power measurement device. The output is then proportional to the log of the rms value of the input. This reading is expressed directly in decibels, conveniently scaled to 52 mV/dB, or about 1 V per decade; however, other ramps are easy to place. In controller mode, the voltage applied to VSET determines the power level required at the input so that the deviation from the set point is zero. The output buffer can supply high load currents.

When powered down by a logic high applied to the TCM2/PWDN pin, the AD8363 dissipates 1.5 mW. It energizes to its nominal operating current of 60mA in about 30µs at 25°C. The AD8363 is available in a 4 mm × 4 mm 16-lead LFCSP for operation over the -40°C to +125°C temperature range.

A fully populated RoHS compliant evaluation board is also available.

Typical performance characteristics

VPOS=5 V, ZO=50Ω, single-ended input driver, VOUT connected to VSET, VTGT=1.4 V, CLPF=3.9 nF, CHPF=2.7 nF, TA=+25°C (black), -40°C (blue) color), +85°C (red), if applicable. Errors calculated using a 3-point calibration at 0 dBm, -10 dBm, and -40 dBm unless otherwise noted. The input RF signal is a sine wave (CW) unless otherwise specified.

theory of operation

The computational core of the AD8363 is a high-performance AGC loop. As shown in Figure 33, the AGC loop includes a wideband variable gain amplifier (VGA), a square-law detector, an amplitude target circuit, and an output driver. See the AD8362 data sheet for a more detailed description of the function blocks.

The terms used in this data sheet to distinguish between pin names and pin signals are as follows:

(1), the pin names are capitalized (for example, VPOS, COMM and VOUT).

(2) The signal name or value associated with the pin is a pin mnemonic with partial subscripts (eg, C, CHPF, and VOUT).

Square-law detectors and magnitude targets

VGA gain in the form of:

Where: Walk is the basic fixed income. VGNS is the scaled voltage that defines the gain slope (in decibels per voltage change). Gain decreases as VSET increases.

VGA output is:

where RF is the AC voltage applied to the input terminals of the AD8363.

Apply the output of the VGA to a wideband square-law detector. The detector provides the true rms response of the RF input signal, independent of the waveform. The detector output I is a fluctuating current with a positive average value. The difference between I and the internally generated current I is integrated by C and an external capacitor attached to the CLPF pin at the summing node. C is the on-chip 25pf filter capacitor, and C is an external capacitor connected to the CLPF pin, which can be used to arbitrarily increase the averaging time while compromising response time. When the AGC loop is in equilibrium:

only if:

where VTGT is the voltage at the VTGT pin. This pin can be conveniently connected via voltage to the VREF pin when VTGT=1.4V.

Because the square-law detectors are electrically identical and well-matched, process and temperature-dependent changes are effectively canceled.

Since the electrical properties of the square-law detectors are identical and well-matched, process and temperature-dependent variations are effectively eliminated.

By changing the VGA set point to force the previous identification, it is clear that:

Substitute in the value of V from Equation 2:

When connected as a measurement device, VSET=VOUT. Solving for VOUT as a function of RFIN

Where: The vertical slope is 1 volt/decade (or 50 mV/dB). VZ is the intercepted voltage.

When RMS(RFIN) = VZ, since log10(1) = 0, this means VOUT = 0V, making the intercept the input that forces VOUT = 0V. Vz has been fixed to about 280 μV (approx.). -58 dBm, referenced to 50Ω) with a CW signal frequency of 100 MHz. In fact, the AD8363 pair is less than ~-56 dBm. This means that the intercept is extrapolated beyond the operating range of the device.

If desired, the effective value of V can be changed by using a resistive divider between VOUT and VSET. (See the Output Voltage Scaling section for more information.)

In most applications, the AGC loop is closed through the setpoint interface and the VSET pin. In measurement mode, VOUT is directly connected to VSET. (See the Measurement Mode Basic Connections section for more information.) In controller mode, the control voltage is applied to VSET, and the VOUT pin typically drives the control input of an amplifying or attenuating system. In this case, the voltage at the VSET pin forces the signal amplitude at the RF input of the AD8363 through feedback to balance the system. (See the Controller Mode Basic Connections section for more information.)

RF input interface

Figure 34 shows the connections for the RF inputs within the AD8363. The input impedance is primarily set by an internal 50Ω resistor connected between INHI and INLO. Set a DC level at approximately half the supply voltage on each pin. Either the INHI pin or the INLO pin can be used as a single-ended RF input pin. (See the RF Input Pin Selection section.) If the DC level on these pins is disturbed, performance will suffer; therefore, signal coupling capacitors must be connected from the input signal to INHI and INLO. The high-pass angle of the input signal formed by the coupling capacitor and the internal resistance is:

where C is Faraz and f is Hertz. The value of the input coupling capacitor must be large enough to pass the input signal frequency of interest. The other input pin should be RF AC coupled to common (ground).

Extensive ESD protection is employed on the RF input, which limits the maximum possible input amplitude to the AD8363.

Selection of RF Input Pins

The dynamic range of the AD8363 can be optimized by selecting the correct RF input pins for the expected operating frequency. With INHI (Pin 14), users can get the best dynamic range at frequencies up to 2.6ghz. Above 2.6ghz, INLO (pin 15) is recommended. At 2.6 GHz, roughly equal performance is obtained at both inputs. The AD8363 was designed with a single-ended RF driver in mind. Baluns can be used to drive INHI and INLO differentials, but this is unnecessary and will not result in improved dynamic range.

Small Signal Loop Response

The AD8363 uses a VGA in the loop to force the squared RF signal to equal the squared DC voltage. For loop responses of small signals, this nonlinear loop can be simplified and solved. The low-pass corner pole is given by:

where: I is in amperes. CLPF is in Faraz. Frequency is Hertz. ITGT is derived from VTGT; however, ITGT is VTGT times resistance, i.e.

GM is about 18.9µs, so VTGT is equivalent to a typical recommended 1.4 volts, and ITGT is about 37µA. This current varies with temperature; therefore, the small-signal magnetic pole varies with temperature. However, because the RF squaring circuit and the DC equalizing circuit rails vary with temperature, there is no temperature variation contribution to the absolute value of VOUT. For continuous wave signals,

However, signals with large crest factors contain low pseudo-random frequency components that require either filtering or sampling and averaging. See the section Choosing a value for CLPF for details.

temperature sensor interface

The AD8363 provides a temperature sensor output with an output voltage scaling factor of approximately 5 mV/°C. The output is capable of reaching a maximum of 4µA at temperatures above 4°C or 25°C, with a maximum of 25µm. If additional current sinking capability is required, an external resistor can be connected between the TEMP and COMM pins. The typical output voltage at 25°C is about 1.4 V.

VREF interface

The VREF pin provides an internally generated voltage reference. The V voltage is a temperature stable 2.3V reference capable of reaching a maximum of 50µA at temperatures above 4°C or 25°C. An external resistor can be connected between the VREF and COMM pins to provide additional current sinking capability. The voltage on this pin can be used to drive the TCM1, TCM2/PWDN and VTGT pins if desired.

Temperature Compensation Interface

Proprietary techniques are used to maximize the temperature stability of the AD8363. For optimum performance, output temperature drift must be compensated using the TCM1 and TCM2/PWDN pins. The absolute value of the compensation varies with frequency and voltage. Table 4 shows the recommended voltages for the TCM1 and TCM2/PWDN pins to operate over the specified temperature range (-40°C) when driving single-ended and using V=1.4V

The values in Table 4 were chosen to give the best drift performance at the high end of the available dynamic range over the -40°C to +85°C temperature range.

The use of TCM1 and TCM2/PWDN to compensate for temperature drift allows a great deal of flexibility, and the user may wish to modify these values at another amplitude point within the dynamic range, for different temperature ranges, or for frequencies other than those shown in Table 4. operating frequency is optimized.

To find a new compensation point, V and V can be swept while monitoring V over temperature at the frequency and amplitude of interest. At a given power and frequency, the optimal voltage for V and V to achieve minimum temperature drift is the value of V and V where V has the smallest shift. See the AD8364 and ADL5513 data sheets for more information.

As the device temperature approaches 25°C, changing V and V has very little effect on V; however, as the temperature deviates from 25°C, the effect of the compensation circuit increases and the need for optimal temperature drift performance increases .

Figure 37 shows the effect on temperature drift performance at 25°C and 85°C as V varies but V remains constant at 0.6 V.

TCM1 adjusts the intercept of the AD8363 primarily over temperature. In this way, TCM1 can be thought of as a rough adjustment to the compensation. Instead, TCM2 performs fine-tuning. For this reason, it is recommended to adjust V first when looking for compensation with V and V, and then adjust V for optimization when the best performance is found.

As evident from Figure 37, a temperature compensation circuit can be used to adjust for minimum drift at any chosen input amplitude. Although not shown in Figure 37, a similar analysis can be performed simultaneously at -40°C or any other temperature within the AD8363 operating range.

Different devices perform slightly differently; therefore, it is necessary to statistically derive optimal V and V values for a population of devices useful in mass production applications.

The TCM1 and TCM2 pins have high input impedances, approximately 5 KΩ and 500 KΩ, respectively, and can be conveniently driven from an external source or from a portion of VREF by using a resistive divider. VREF does vary slightly with temperature and RF input amplitude (see Figure 32 and Figure 29); however, the amount of variation is unlikely to have a significant impact on the final temperature stability of the RF measurement system.

Figure 38 shows a simplified schematic of TCM1. See the Power-Down Interface section for the TCM2 interface.

Power down interface

The quiescent and disabled currents for the AD8363 at 25°C are about 60mA and 300µA, respectively. The dual function pin TCM2/PWDN is connected to the temperature compensation circuit and the power-down circuit. Typically, when PWDN is greater than V−0.1v, the device is completely powered down. Figure 28 shows this characteristic as a function of V. Due to the design of this part of the AD8363, the TCM2/PWDN pin sinks approximately 750µA when V passes through a narrow range at 4.5 V (or V to 0.5 V). The source used to disable the AD8363 must have a high enough current capability for this. Figure 23 shows typical response times for different RF input levels. The output reaches 0.1dB of its steady-state value in approximately 35µs; however, the reference voltage can reach full accuracy in less time. This wake-up response varies with input coupling and capacitances C and C.

VSET interface

The VSET interface has a high input impedance of 72 kΩ. The voltage on VSET is converted to an internal current used to set the internal VGA gain. The VGA attenuation control is about 19 dB/V.

Output Interface

The output driver used in the AD8363 is different from the output stage on the AD8362. The AD8363 integrates a rail twist output driver with pull-up and pull-down capabilities. The closed-loop -dB bandwidth of the unloaded VOUT buffer is approximately 58 MHz with a unipolar roll-off of 20 dB/dx. The output noise is about 45 nV/z Hz at 100 kHz, which is independent of C due to the structure of the AD8363. VOUT can source and sink up to 10mA. The internal load between VOUT and COMM is 2.5 kΩ.

VTGT interface

The target voltage can be set using an external power supply or by connecting the VREF pin (2.3 V nominal) to the VTGT pin through a resistive divider. When there is a 1.4v voltage on the VTGT pin, the rms voltage that the VGA must provide is 1.4v×0.05=70mvrms to balance the AGC feedback loop. Most of the characterization information in this datasheet was collected at V=1.4V. Voltages above or below this voltage can be used; however, doing so will increase or decrease the gain at the internal square element, resulting in a corresponding increase or decrease in the intercept. This in turn affects the sensitivity and usable measurement range. Since the gain of a square element varies with temperature, it can cause oscillations or losses in the measurement range. For these reasons, do not lower V below 1.3 V.

Measurement Mode Basic Connections

The AD8363 requires a nominally 5 V single supply. Power is connected to two power pins, VPO. Use two capacitors of value equal to or similar to that shown in Figure 43 to disconnect the pins. These capacitors must provide low impedance over the entire frequency range of the input, and they should be as close as possible to the VPOS pin. Use two different capacitor values in parallel to provide broadband AC shorted to ground.

The input signal can be differential or single-ended, but in both cases the input impedance is 50Ω. Most of the performance information in this datasheet was obtained with single-ended drivers. The best measurement range is achieved using a single-ended driver on the INHI pin at frequencies below 2.6GHz (as shown in Figure 43), and similarly, the best performance is achieved on the INLO pin at frequencies above 2.6GHz (as shown in Figure 43). However, INLO is AC-coupled with the input, and INHI is AC-coupled with the ground).

The AD8363 is in measurement mode by connecting VOUT to VSET. This closes the AGC loop within the device with V representing the VGA control voltage required to present the correct rms voltage at the input of the internal square-law detector.

System calibration and error calculation

The measured transfer function of the AD8363 at 1.9GHz is shown in Figure 44, which includes plots of output voltage versus input amplitude (power) and calculated error versus input level. The output voltage varies from ~0 V to ~3.1 V when the input level changes from -55 dBm to +0 dBm.

Since the slope and intercept vary from device to device, board-level calibration must be performed for high accuracy. The equation for the ideal output voltage can be written as:

Where: Ramp change in output voltage divided by change in input power in decibels.

The intercept is the calculated input power level when the output voltage is equal to 0 V (note that the intercept is an extrapolated theoretical value, not a measured value).

Typically, calibration to establish slope and intercept is performed during device manufacturing by applying two or more known signal levels to the AD8363's input and measuring the corresponding output voltage. The calibration point is generally chosen to be within the linear in-dB operating range of the device.

With a two-point calibration, the slope and intercept are calculated as follows:

During device calibration, after the slope and intercept are calculated and stored in non-volatile memory, the unknown input power can be calculated using equations based on the detector's output voltage.

The log consistency error is the difference between this line and the actual performance of the detector.

Figure 44 includes an error plot when using a two-point calibration (calibration points at -20 dBm and -40 dBm). By definition, the error of the calibration point is equal to 0.

By increasing the number of calibration points, the residual nonlinearity of the transfer function evident in the two-point calibration error graph can be reduced. Figure 45 shows the post-calibration error plot for the three-point calibration. With multi-point calibration, the transfer function is segmented, each segment has its own slope and intercept. During calibration, multiple known power levels are applied and multiple voltages are measured. When the device is running, the voltage measured by the detector is first used to determine which stored slope and intercept calibration coefficients to use. The unknown power level is then calculated by inserting the appropriate slope and intercept in Equation 15.

Figure 45 shows the output voltage and error at 25°C and over temperature using a three-point calibration with calibration points of 0 dBm, -10 dBm, and -40 dBm. When selecting calibration points, it is not required that the points be equally spaced. There is also no limit to the number of calibration points used.

The -40°C and +85°C error plots in Figure 44 and Figure 45 were generated using the 25°C calibration factor. This is consistent with device calibration in a mass production environment where calibration at only one temperature is feasible.

Operating temperature 125°C

The AD8363 operates up to 125°C with a slight degradation in performance. Figure 46 shows typical operation at 125°C compared to other temperatures using the TCM1 and TCM2 values in Table 4 (error plotted using a two-point calibration). Temperature compensation can be optimized to operate above 85°C by modifying the voltages on the TCM1 and TCM2 pins shown in Table 4.

Output voltage scaling

The output voltage range of the AD8363 (nominally 0 volts to 3.5 volts) can be easily increased or decreased. In many cases it makes sense to adjust the output scale. For example, if the AD8363 is driving an analog-to-digital converter (ADC) with a 0 V to 5 V input range, it makes sense to increase the detector's nominal maximum output voltage of 3.5 V so that it is closer to 5 V. This allows better utilization of the ADC's input range and maximizes the system's resolution in bits/dB.

If only a portion of the AD8363's RF input power range is used (for example, -10 dBm to -40 dBm), the scaling can be increased so that this reduced input range fits within the AD8363's available output swing (0 V to 4.8 V) .

The output swing can be reduced by adding a voltage divider on the output pin, as shown in Figure 47 (VOUT is connected directly to VSET with a resistor divider on VOUT). Figure 47 also shows how to increase the output voltage swing using a technique similar to setting the op amp gain in non-converting mode. When the VSET pin acts as the inverting input of the op amp, connect a resistor divider between VOUT and VSET.

Equation 17 is the general function governing this.

where: VO is the nominal maximum output voltage (see Figure 4 through Figure 18). VO is the new maximum output voltage (eg, up to 4.8 volts). RIN is the VSET input resistance (72 kΩ).

When choosing R1 and R2, one must pay attention to the current drive capability of the VOUT pin and the input resistance of the VSET pin. Resistor selection should not result in excessive output current. However, making R1 and R2 too large is also problematic. If the value of R2 is compatible with the 72 kΩ input resistance of the VSET input, this input resistance (which varies slightly with the device) will result in the slope and output voltage. In general, the value of R2 should be at least 10 times smaller than the input resistance of VSET. Therefore, the values of R1 and R2 should be in the range of 1 kΩ to 5 kΩ.

It is also important to take into account the device-to-device and output swing frequency variation and the maximum output voltage of 4.8 V for the AD8363 output stage. The VOUT distribution is well characterized in the main frequency bands in the typical performance characterization section (Figure 3 to Figure 18).

Offset Compensation, Min C and Max C Capacitance Values Low Intercept Probability Hydro Power Plants

An offset compensation loop is used to remove small DC offsets within the internal VGA, as shown in Figure 48. The high-pass corner frequency of this loop is set to about 1 MHz using a 25 pF on-chip capacitor. This limits the operating frequency range of the device as input signals below 1MHz are interpreted as unwanted offset voltages. To operate the AD8363 at lower frequencies (below 1 MHz), the high pass corner frequency must be reduced by connecting a capacitor between CHPF and VPO.

The internal offset voltage depends on the gain at which the VGA is operating, and therefore on the amplitude of the input signal. When larger values of C are used, the offset correction process can delay more rapid changes in VGA gain, which can increase the time required for the loop to fully adapt to a given stable input amplitude. This can manifest in a jumpy, seemingly oscillatory response of the AD8363.

Therefore, care should be taken when choosing C and C as there is a possibility of oscillation. In general, make the capacitance on the CPLF pin as large as possible; there is no maximum capacitance on the capacitor. At high frequencies, the CHPF pin does not require an external capacitor; therefore, the pin can be left open. However, when trying to get a fast response time and/or operating at low frequencies, take extra care when choosing the appropriate capacitor values for C and C. By connecting the gain control pin (VSET) to VOUT, V can be rotated at a rate determined by the square cell and C on the chip. As V varies with time, the DC offset in the VGA also varies with time. The speed at which the VSET rotates produces a time-varying offset within the high-pass corner range set by the CHPF. Therefore, in measurement mode, pay attention to setting CLPF appropriately to reduce slewing. It is worth noting that most of the typical performance data is derived with CLPF=3.9nF and CHPF=2.7nF and CW waveforms.

The minimum appropriate CLPF based on the slew rate limit is as follows:

Where: CLPF in Faraz. Frequency is Hertz.

This takes into account the on-chip 25 pF capacitor, CF, in parallel with CLPF. However, because there are other internal device delays that affect loop stability, use a minimum CLPF of 390 lbs. The minimum suitable CHPF frequency for a given high pass pole is:

where FHP is Hertz.

The 25 pF subtraction is the result of the on-chip 25 pF capacitor in parallel with the external CHPF. Typically, the CHPF is chosen so that the pole (3db angle) is at least a decade below the desired signal frequency. Note that without an external CHPF, the high pass corner of the offset compensation system is about 1 MHz, so adding external capacitance reduces the corner frequency.

The following example illustrates the proper selection of input coupling capacitors, minimum CPLF, and maximum CHPF when using the AD8363 measurement mode with a 1 GHz input signal.

1. Select an input coupling capacitor with an angle of 3 dB at least ten years lower than the input signal frequency. From Equation 8, C>10/(2×π×RF×50)=32pf minimum. According to this calculation, 32 pF is sufficient; however, the value of the input coupling capacitor should be much larger, typically 0.1µF. The offset compensation circuit connected to the CHPF should be the real determinant of the high pass corner frequency of the system, not the input coupling capacitor. Using a 0.1µF coupling capacitor, signals as low as 32 kHz can be coupled to the input, which is well below the system high pass frequency.

2. Select C to reduce instability due to VSET slew rate.

See Equation 18, where FRQRFIN = 1 GHz, which results in a CLPF > 20 pF. However, as mentioned earlier, values below 390 pF are not recommended. For this purpose, a 470 pF capacitor was chosen. Also, if fast response times are not required, larger CLPF values than those given here should be chosen.

3. Select CHPF to set the 3db angle of the offset compensation system. See Equation 19, in this case FHPPOLE is 100 MHz, a decade below the desired signal. This produces a negative number, and obviously, negative values are not practical. Since the high pass corner frequency is already 1 MHz, this result simply states that the appropriate solution is to not use an external CHPF capacitor.

Note that according to Equation 9

The CPLF of 470 PF results in a small-signal low-pass corner frequency of about 144 kHz. This reflects the bandwidth of the measurement system, and how quickly the user expects the output to change. This does not imply any restrictions on the input RF carrier frequency.

choose a value for C

The Small Signal Loop Response section and the Offset Compensation, Minimum CPLF and Maximum CHPF Capacitor Values section discuss how to choose the minimum value for CPLF based on the minimum capacitance of 390 PF, slew rate limitations, and operating frequency. Using the minimum value of CLPF allows the fastest response time for pulsed waveforms such as WiMAX, but also allows for maximum residual ripple on the output from pseudorandomly modulated waveforms. For the CPLP-pin, there is no maximum capacitance, and in most cases a capacitor large enough can be added to cancel the residual ripple caused by the modulation, but allow a fast enough response to changes in input power.

Figure 49 shows how the residual ripple, rise time, and fall time vary with filter capacitance when the AD8363 is driven by a single-carrier CDMA2000 9CH SR1 signal at 2.14GHz. Rise and fall times are based on a signal pulsing between no signal and 10 dBm, but faster if the input power changes less.

Table 5 shows the CLPF recommendations for common modulation schemes. For non-pulse waveforms, increase CLPF until the residual output noise is below 50 mV (±0.5 dB). In each case, capacitors can be added to further reduce noise. Step responses from 10% to 90% of the input steps are also listed. If the increased response time is unacceptably high, lower C, which increases the noise on the output. Due to the random nature of the output ripple, averaging in the digital domain further reduces residual noise if sampled by the ADC.

Table 5 gives the CLPF values that minimize noise while maintaining a reasonable response time. For non-pulse waveforms, the output does not need to be averaged. For pulsed waveforms, the less noise, the less averaging is required for the output. The system specification determines the necessary rise and fall times. For example, the proposed C value for WiMAX assumes that no power measurement in the preamble is required.

Figure 50 shows how the rise time cuts off the leading. Note that the power in the preamble can be easily measured; however, the CLPF value must be lowered slightly and the noise in the main signal will increase.

As shown in Figure 49, the fall time of the AD8363 increases as the CLPF capacitance increases, the rise time increases. Some pulse-type modulation standards require a fast fall time as well as a fast rise time, and in all cases less output ripple is desirable. Placing an RC filter at the output reduces the frequency content of the ripple and filters. Using an RC output filter can also change the rise and fall times and the output ripple response compared to the CLPF capacitor.

Figure 51 shows the response to a 2.14GHz pulsed signal (C=3900pF). The residual ripple from the single carrier CDMA2000 9CH SR1 signal is 150 mV pp. (Ripple not shown in Figure 51). Ripple is measured separately. ) Figure 52 shows the response of a 2.14 GHz pulsed signal with a C of 390 pF and an output filter consisting of a series 75Ω resistor (closest to the output) and a 0.15µF capacitor to ground. The residual ripple for this configuration is also 150 mV pp. Note that when using a larger C to get 150 mV pp ripple, the rise time is faster and the fall time is slower.

RF Impulse Response and VTGT

The AD8363's response to a pulsed RF waveform is affected by V. Referring to Figures 21 and 22, there is a period of inactivity between the onset of the RF waveform and the time when V begins to show a response. This is the result of squared current balancing within the AD8363. This delay can be reduced by reducing V; however, as noted earlier in the VTGT interface section, this has implications for sensitivity, intercept, and dynamic range. Decreasing V increases V rise and fall times while reducing delay.

Controller Mode Basic Connections

In addition to being a measurement device, the AD8363 can be configured to control the rms signal level, as shown in Figure 53.

The device's RF inputs are configured by measurement mode, and any input can be used. A directional coupler can cut off some of the power produced by the VGA. If losses in the main signal path are not an issue, and reflected energy at the next stage in the signal chain is not an issue, a power splitter can be used instead of a directional coupler. Setting the maximum input signal on the AD8363 equal to the recommended maximum input level for best linearity and temperature stability at the operating frequency may require some additional attenuation.

The VSET and VOUT pins are no longer shorted together. VOUT now provides a bias or gain control voltage for the VGA. The gain control of the VGA must be negative and monotonic, that is, the higher the voltage, the smaller the gain. However, the gain control transfer function of the device does not need to be well controlled or particularly linearized. If the gain control of the VGA senses positive, an inverting op amp circuit with a dc offset shift can be used between the AD8363 and the VGA to keep the gain control voltage in the range of 0.03 V to 4.8 V.

VSET becomes the set point input for the system. As shown in Figure 53, this can be driven by a DAC if the output power is expected to vary, or by a stable reference voltage if a constant output power is required. The output swing of this DAC should be between 0.15 V and 3.5 V.

When V is set to a specific value, the AD8363 compares that value to the equivalent input power at the RF input. If these two values do not match, V will increase or decrease to balance the system.

The amplifier/integrator circuit that drives V is set by a capacitor on the CLPF pin; some experimentation may be required to choose the correct value for this capacitor.

In general, C should be chosen to provide stable loop operation over the entire output power control range. If the slope (dB/V) of the VGA's gain control transfer function is not constant, C must be chosen to guarantee a stable loop with the gain control slope at its maximum value. In addition, C must provide sufficient average value for the internal low-distance squared detector for efficient rms calculation. The larger the value of C, the worse the response of the loop.

The relationship between V and RF input follows the measurement mode behavior of the device. For example, Figure 4 shows the measurement mode transfer function at 900 MHz and an output voltage of approximately 2.5 V with an input power of 10 dBm. Therefore, in controller mode, if V is 2.5 V, the AD8363 output will go to whatever voltage is necessary to set the AD8363 input power to 10 dBm.

Constant output power operation

In controller mode, the AD8363 can be used to keep the output power of the VGA stable over a wide temperature/input power range. This is useful in a topology where a transport card drives an HPA, or when connecting any two power-sensitive modules together.

Figure 54 shows a schematic diagram of the circuit setup to maintain the output power to approximately 26 dBm at 2.14 GHz when the input power varies over a 40 dB dynamic range. Figure 55 shows the results. A portion of the output power is coupled using a 10db directional coupler and fed into the AD8363. V is fixed at 0.95 volts, which forces the AD8363 output voltage to control the ADL5330, making the input to the AD8363 approximately 36 dBm.

If the AD8363 is in measurement mode and an input power of -36 dBm is applied, the output voltage will be 0.95 V. A rail-to-rail op amp (AD8062) is typically used to invert the slope of the AD8363 so that the gain of the ADL5330 decreases as the AD8363 control voltage increases. Due to the action of the coupler, the output power is controlled at a power level 10 dB higher than that of the AD8363. High-end power is limited by the linearity of a VGA with high attenuation (ADL5330) and can be increased by using a higher linear VGA.

Low-end power is limited by the maximum gain of the VGA (ADL5330) and can be increased by using a VGA with more gain. Using TCM1 = 0.52 V and TCM2 = 0.6 V, the temperature performance is directly related to the temperature performance of the AD8363 at 2.14 GHz and -26 dBm. The AD8363 eliminates all other temperature variations.

RF Characterization

A general hardware configuration for most AD8363 features is shown in Figure 56. The AD8363 is driven in a single-ended configuration for all characterizations.

The AD8363 features a multi-site test strategy. Several AD8363 devices mounted on a circuit board made of Rogers 3006 material were simultaneously inserted into a remotely controlled thermal chamber. The Keithley S46 RF switching network connects the Agilent E8251A signal source to the appropriate device under test. The Agilent 34980A switch matrix provides DC power and metering switches for the test site. A PC running Agilent VEE Pro controls signal sources, switches and chamber temperature.

Voltmeters measure subsequent responses to stimulation, and the results are stored in a database for later analysis. In this way, multiple AD8363 devices are characterized over amplitude, frequency, and temperature in the shortest time possible.

The RF stimulation amplitude was calibrated to the connector of the board carrying the AD8363. However, calibration does not account for minor losses due to connectors and traces from connectors to the device under test. Therefore, small absolute amplitude errors (<0.5db) are not considered in the characterization data.

This means that there is a slight error in the reported intercept; however, this is usually not significant because the slope and relative accuracy of the AD8363 are not affected.

Typical performance data is derived from C=3.9nF and C=2.7nF, and the waveform is CW.

Evaluate and characterize board layouts

Figure 57 through Figure 61 show evaluation boards for the AD8363.

Assembly drawing

Dimensions