feature

Low-Power, Four-nm Digital-to-Analog Converter; AD5664 : 16-bit; AD5624: 12-bit; Relative Accuracy: ±12 LSB Max; Monotonic by Design; 10-lead MSOP and 3 mm × 3 mm LFCSP-WD; 5.5 V power supply; power-on reset to zero; power down per channel; serial interface, up to 50 MHz.

application

Process Control; Data Acquisition Systems; Portable Battery-Powered Instruments; Digital Gain and Offset Adjustment; Programmable Voltage and Current Sources; Programmable Attenuators.

General Instructions

The AD5624/AD5664, a family of nanoDACs, are low-power, quad-, 12-, and 16-bit buffered voltage output DACs that operate from a single 2.7 V to 5.5 V supply and are guaranteed to be monotonic by design.

The AD5624/AD5664 require an external reference voltage to set the output range of the DAC. This part includes a power-on-reset circuit that ensures the DAC output powers up to 0v and remains there until a valid write occurs. These parts include a power-down feature that reduces the device's current consumption to 480Na at 5V and provides a software-selectable output load in power-down mode.

The low power consumption of these parts during normal operation makes them ideal for portable battery-operated devices. Power consumption is 2.25mW at 5v and drops to 2.4µW in power down mode.

The AD5624/AD5664 on-chip precision output amplifiers allow rail-to-rail output swing.

The AD5624/AD5664 use a versatile 3-wire serial interface that operates at clock frequencies up to 50 MHz and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards.

Product Highlights

1. Relative accuracy: maximum ±12 LSBs.

2. Provide 10-lead MSOP and 10-lead, 3 mm×3 mm, LFCSP U WD.

3. Low power, typically consumes 1.32mW at 3V and 2.25mW at 5V.

4. The maximum settling time is 4.5μs (AD5624) and 7μs (AD5664).

the term

Relative Accuracy or Integral Nonlinearity (INL) For DACs, relative accuracy or integral nonlinearity is the maximum deviation measured from a straight line in the LSBs through the endpoints of the DAC transfer function.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured variation and the ideal 1lsb variation of any two adjacent codes. The specified differential nonlinearity ±1 LSB maximum guarantees monotonicity. The monotonicity of the DAC is guaranteed by design.

Zero scale error

Zero-scale error is a measure of the output error when the zero code (0x0000) is loaded into the DAC register. Ideally, the output should be 0 V. Since the output of the DAC cannot go below 0 V, zero code errors are always positive in the AD5624/AD5664. This is due to a combination of offset errors in the DAC and output amplifier. Zero-code errors are expressed in millivolts.

full scale error

Full-scale error is a measure of the output error when the full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be V-1 LSB. Full-scale error is expressed in % of FSR.

gain error

This is a measure of the span error of the DAC. It is the deviation of the slope of the DAC transfer characteristic from the ideal, expressed as a percentage of FSR.

Zero code error drift

This is a way to measure the zero code error as a function of temperature. Expressed in μV/°C.

Gain temperature coefficient

This is a measure of gain error as a function of temperature. Expressed in parts per million FSR/°C.

offset error

Offset error is the difference between V(actual) and V(ideal) in mV in the linear region of the measurement transfer function. The offset error is measured on the AD5624/AD5664 and the DAC register is loaded with code 512 . It can be negative or positive.

DC Power Supply Rejection Ratio (PSRR)

This shows how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V to the change in V for the full-scale output of the DAC. The unit is decibel. V remains at 2V and V varies by ±10%.

Output voltage settling time

This is the time required for the output of the DAC to settle to the specified level for a 1/4 to 3/4 full-scale input change, measured from the 24 falling edge of SCLK.

Digital-to-analog fault pulse

A digital-to-analog fault pulse is a pulse injected into the analog output when the input code in the DAC register changes state. It is usually designated as a fault region in nV-s, measured when the digital input code is changed by 1lsb at the major carry transition (0x7FFF to 0x8000).

digital feedthrough

Digital feedthrough is a measurement of the pulses injected into the DAC's analog output from the DAC's digital input, but when the DAC output is not being updated. It is specified in nV-s and is measured by a full-scale code change on the data bus, i.e. from 0 to 1 and vice versa.

Total Harmonic Distortion (THD)

This is the difference between an ideal sine wave and a decaying sine wave using a DAC. The sine wave is used as a reference for the DAC, and THD is a measure of the harmonics of the DAC's output. The unit is decibel.

noise spectral density

This is a measure of internally generated random noise. Random noise is characterized by its spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring the noise at the output. The unit of measurement is nV/√Hz.

DC crosstalk

DC crosstalk is the DC change in the output level of one DAC as the output of another DAC changes. It is measured by the full-scale output change of one DAC (or soft power off and on) while monitoring the other DAC held at mid-scale. Expressed in μV.

DC crosstalk caused by load current changes is a way to measure the effect of a change in load current on one DAC on another DAC held at midscale. Expressed in μV/mA.

digital crosstalk

This is a glitch pulse that is midscale transferred to the output of one DAC in response to a full-scale code change in the input register of the other DAC (all 0s to all 1s and vice versa). It is measured in standalone mode and expressed in nV-s.

Analog crosstalk

This is a glitch pulse transferred to the output of one DAC due to a change in the output of the other DAC. It is measured by loading an input register for a full range of code changes (from 0 to 1 and vice versa). Then execute a software LDAC and monitor the output of the DAC whose digital code has not changed. The fault area is denoted by nV-s.

DAC-to-DAC crosstalk

This is a glitch pulse transferred to the output of one DAC due to a change in the digital code of the other DAC and a subsequent change in the analog output. It is a comprehensive code change (from 0 to 1 and vice versa) by using the commands write-to and update to load the attack channel, while monitoring the output of the attacked channel at the mid-scale. The fault energy is expressed in nV-s.

Double the bandwidth

Amplifiers within a DAC have limited bandwidth. Multiplying bandwidth is one measure. A sine wave on the reference appears in the output (loading the full-scale code to the DAC). The octave bandwidth is where the output amplitude drops 3db below the input.

theory of operation

Section D/A

The AD5624/AD5664 digital-to-analog converters are fabricated in a CMOS process. The structure consists of a string DAC and an output buffer amplifier. Figure 29 shows a block diagram of the DAC architecture.

Since the input encoding of the DAC is straight binary, the ideal output voltage is given by:

Where: D is the 0 to 4095 (12 bits) loaded into the DAC register: AD5624. 0 to 65535 (16 bits) for AD5664. N is the DAC resolution.

resistor string

The resistor string is shown in Figure 30. It's just a string of resistors, each with a value of R. The code loaded into the DAC register determines at which node on the string the voltage is tapped into the output amplifier. The voltage is cut off by closing a switch to connect the string to the amplifier. Because it is a string of resistors, monotonicity is guaranteed.

output amplifier

The output buffer amplifier can generate rail-to-rail voltage at its output, the output range is 0v to V, can drive a 2kΩ load, and is connected in parallel with 1000pf to GND. The source and sink capabilities of the output amplifier are shown in Figure 17. The slew rate is 1.8v/μs, and the whole settling time is 7μs.

serial interface

The AD5624/AD5664 feature a 3-wire serial interface (synchronous, SCLK and DIN) with SPI, QSPI and MICROWIRE interface standards and most DSPs.

Pull the sync line low at the beginning of the write sequence. Data from the data line is recorded into a 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50MHz, making the AD5624/AD5664 compatible with high-speed DSPs. On the 24 falling clock edge, the last data bit is clocked and the programming function is performed, ie, a change of DAC register contents and/or a change of mode operation. During this phase, the sync line can be held low or high. In both cases, it must be brought up at least 15 ns before the next write sequence, so that the falling edge of synchronization can initiate the next write sequence. Since the sync buffer draws more current at V=2.0V than at V=0.8V, a low-idle sync should be used between write sequences for lower power operation. However, it must be turned up again before the next write sequence.

input shift register

The input shift register is 24 bits wide, the first two bits are insignificant bits. The next three bits are the command bits, C2 to C0 (see Table 7), followed by the 3-bit DAC address, A2 to A0 (see Table 8), then the 16-bit and 12-bit data words. The data word consists of a 16-bit, 12-bit input code followed by 0 or 4 bits, independent of the AD5664 and AD5624, respectively (see Figure 31 and Figure 32). These data bits are transferred to the DAC register on the falling edge of SCLK 24.

Sync outage

In a normal write sequence, the sync line is held low for at least 24 falling edges of SCLK, and the DAC is updated on 24 falling edges. However, if sync is brought high before the falling edge of 24, then this will act as an interruption to the write sequence. The input shift register is reset and the write sequence is considered invalid. Neither an update of the DAC register contents nor a change in operating mode occurs (see Figure 33).

power-on reset

The AD5624/AD5664 family includes a power-on reset circuit that controls the output voltage during power-up. The AD5624/AD5664 DACs output supplies up to 0V and remain unchanged until a valid write sequence to the DACs. This is useful in applications where it is important to know the state of the DAC's output during power-up.

software reset

The AD5624/AD5664 include a software reset function. Command 110 is reserved for the software reset function (see Table 7). The software reset command contains two reset modes, which are software programmable by setting bit DB0 in the control register. Table 9 shows how the state of the bits corresponds to the software reset mode of operation of the device.

Power down mode

The AD5624/AD5664 contain four independent modes of operation. Command 100 is reserved for the power down function (see Table 7). These modes are software programmable by setting two bits in the control register (DB5 and DB4). Table 10 shows how the state of the bits corresponds to the operating mode of the device. All DACs (DAC D to DAC A) can be turned off to the selected mode by setting the corresponding four bits (DB3, DB2, DB1 and DB0) to 1. Any combination of DACs is enabled by executing the same command 100 with bits DB5 and DB4 set to normal operating mode. To select the combination of DAC channels to power up, set the corresponding four bits (DB3, DB2, DB1, and DB0) to 1. The contents of the input shift register during power-down/power-up operation are shown in Table 11.

When both bits are set to 0, the part operates normally and its normal power consumption is 450µA at 5 V. However, for the three power-down modes, the supply current drops to 480 nA at 5 V (200 nA at 3 V). Not only does the supply current drop, but the output stage also switches from inside the amplifier's output to a network of resistors of known value. This allows the output impedance of the component to be known when the component is in power down mode. The output can be internally connected to GND through a 1kΩ or 100kΩ resistor, or left open (tri-stated) (see Figure 34).

When the power-down mode is activated, the bias generator, output amplifier, resistor string and other associated linear circuits are turned off. However, when powered down, the contents of the DAC registers are not affected. The power-off time is typically 4 μs, V = 5 V, and V = 3 V (see Figure 21).

LDAC function

The AD5624/AD5664 DACs have a double-buffered interface consisting of two sets of registers: the input register and the DAC register. The input registers are connected directly to the input shift registers, and the digital code is transferred to the associated input register upon completion of a valid write sequence. The DAC register contains the digital code used by the resistor string.

The double-buffered interface is useful if the user needs to update all DAC outputs simultaneously. The user can write to each of the three input registers, then write to the remaining input registers and update all DAC registers, simultaneously updating the outputs. Command 010 is reserved for this software LDAC.

Access to the DAC registers is controlled by the LDAC function. The LDAC register contains two modes of operation for each DAC channel. The DAC channel is selected by setting bits in the 4-bit LDAC register (DB3, DB2, DB1, and DB0). Command 110 is reserved for setting the LDAC register. When the LDAC bit register is set low, the corresponding DAC register is latched and the input register can change state without affecting the contents of the DAC register. However, when the LDAC bit register is set high, the DAC registers become transparent and the contents of the input registers are transferred to them on the falling edge of the 24 SCLK pulses. This is equivalent to the LDAC hardware pin permanently tied low for the selected DAC channel (ie synchronous update mode). See Table 12 for the LDAC register operating modes. During the LDAC register set command, the contents of the input shift register are shown in Table 13.

This flexibility is useful in applications where the user wishes to update a selected channel at the same time as the rest of the channel is updated synchronously.

Microprocessor interface

AD5624/AD5664 to black fin® ADSP-BF53x interface

Figure 35 shows the serial interface between the AD5624/AD5664 and the Blackfin ADSP-BF53x microprocessors. The ADSP-BF53x processor family includes two dual-channel synchronous serial ports SPORT1 and SPORT0 for serial and multiprocessor communications. Use SPORT0 to connect to the AD5624/AD5664 with the following interface settings. DTOPRI drives the DIN pins of the AD5624/AD5664, and TSCLK0 drives the part's SCLK. Synchronization is driven by TFS0.

AD5624/AD5664 to 68HC11/68L11 interface

Figure 36 shows the serial interface between the AD5624/AD5664 and 68HC11/68L11 microcontrollers. The SCK of the 68HC11/68L11 drives the SCLK of the AD5624/AD5664, while the MOSI output drives the serial data line of the DAC.

The sync signal comes from the port line (PC7). The setup conditions for correct operation of this interface are as follows. The CPOL bit of the 68HC11/68L11 is configured as 0 and the CPHA bit is configured as 1. When data is transferred to the DAC, the sync line is low (PC7). When the 68HC11/68L11 is configured as described above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data for the 68HC11/68L11 is transferred in 10-bit bytes with only 8 falling clock edges during the transfer cycle. The data MSB is transferred first. To load data into the AD5624/AD5664, after the first 8 bits have been transferred, PC7 is held low and a second serial write is performed to the DAC; at the end of this process, PC7 is taken high.

AD5624/AD5664 to 80C51/80L51 interface

Figure 37 shows the serial interface between the AD5624/AD5664 and the 80C51/80L51 microcontroller. The interface settings are as follows. The TxD of the 80C51/80L51 drives the SCLK of the AD5624/AD5664, while the RxD drives the serial data line portion of the AD5624/AD5664. Synchronization signals come from bit-programmable pins on the port. In this case, use port line P3.3. P3.3 is taken low when data is being transferred to the AD5624/AD5664. The 80C51/80L51 only transmits data in 10-bit bytes; therefore only 8 falling clock edges occur during the transmit cycle. To load data into the DAC, P3.3 is held low after the first 8 bits have been sent and a second write cycle is initiated to send the second byte of data. P3.3 rises after this cycle is completed. The 80C51/80L51 outputs serial data in a format with LSB first. The AD5624/AD5664 must receive data with the MSB first. The 80C51/80L51 transfer routines should take this into account.

AD5624/AD5664 to Microwire Interface

Figure 38 shows the interface between the AD5624/AD5664 and any Microwire compatible device. Serial data is shifted out on the falling edge of the serial clock and into the AD5624/AD5664 on the rising edge of SK.

application

Select Reference for AD5624/AD5664

To achieve the best performance of the AD5624/AD5664, consideration should be given to selecting an accurate voltage reference. The AD5624/AD5664 have only one reference input, V. The voltage on the reference input is used to provide the positive input to the DAC. Therefore, any errors in the reference will be reflected in the DAC.

When choosing a voltage reference for a high-precision application, error sources are initial accuracy, ppm drift, long-term drift, and output voltage noise. The initial accuracy of the DAC's output voltage will result in the full-scale error of the DAC. To minimize these errors, benchmarks with high initial accuracy are preferred. Selecting a reference with an output trim adjustment (such as the ADR423) allows the system designer to trim system errors by setting the reference voltage to a voltage other than the nominal voltage. The trim adjustment can also be used to trim any errors at temperature.

Long-term drift is a measure of how much a reference drift changes over time. A reference with strict long-term drift specifications ensures that the entire solution remains relatively stable over its entire lifetime.

The temperature coefficient of the reference output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce the temperature dependence of the DAC output voltage under ambient conditions.

In high-precision applications with relatively low noise budgets, the reference output voltage noise needs to be considered. Choosing a reference voltage with as low an output noise voltage as possible is important for system noise resolution requirements. Precision voltage references such as the ADR425 produce low output noise in the 0.1Hz to 10Hz range. Table 14 shows an example of a recommended accuracy reference to use as a power supply for the AD5624/AD5664.

Use the reference as a power source

AD5624/AD5664

Since the supply current required by the AD5624/AD5664 is extremely low, another option is to use a voltage reference to supply the required voltage to the part (see Figure 39). This is especially useful if the power supply is noisy, or if the system supply voltage is not 5V or 3V, such as 15V. The voltage reference outputs the regulated supply voltage for the AD5624/AD5664 (see Table 14 for a suitable reference). If a low dropout REF195 is used, it must supply 450µA to the AD5624/AD5664 with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply current to the load. The total current required (with a 5 kΩ load on the DAC output) is:

The load regulation of the REF195 is typically 2ppm/mA, which results in an error of 2.9ppm (14.5µV) for the 1.45ma current drawn from it. This corresponds to a 0.191 LSB error.

Bipolar Operation Using the AD5624/AD5664

The AD5624/AD5664 are designed for single-supply operation, but a bipolar output range can also be achieved using the circuit in Figure 40. The output voltage range of this circuit is ±5 V. Using the AD820 or OP295 as the output amplifier enables rail-to-rail operation at the output of the amplifier.

The output voltage of any input code can be calculated as follows:

where D represents the input code in decimal (0 to 65536). When VDD=5V, R1=R2=10KΩ,

This is an output voltage range of ±5 V, 0x0000 corresponds to -5 V output and 0xFFFF corresponds to +5 V output.

Using AD5624/AD5664 with Galvanically Isolated Interface

In process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the control circuit from any dangerous common-mode voltages that may be present in the area where the DAC operates. Isocouplers provide isolation in excess of 3 kV. The AD5624/AD5664 use a 3-wire serial logic interface, so the ADuM130x 3-channel digital isolators provide the required isolation (see Figure 41). The power supply to this part also needs to be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V required by the AD5624/AD5664.

Power Bypass and Ground

When accuracy is important in a circuit, it is helpful to carefully consider the power and ground return layout on the board. A printed circuit board containing the AD5624/AD5664 should have separate analog and digital sections, each with its own board area. If the AD5624/AD5664 are in a system where other devices require an AGND-to-DGND connection, they should only be connected at one point. This ground point should be as close as possible to the AD5624/AD5664.

The power supplies to the AD5624/AD5664 should be bypassed with 10µF and 0.1µF capacitors. The capacitor should be as close to the device as possible, ideally the 0.1µF capacitor is facing the device. The 10µF capacitors are of the tantalum bead type. It is important that 0.1µF capacitors have low effective series resistance (ESR) and effective series inductance (ESI), for example, common ceramic capacitors. This 0.1µF capacitor provides a low impedance ground path for high frequencies caused by transient currents generated by the internal logic switches.

The power cord itself should have as large a trace as possible to provide a low impedance path and reduce the impact of faults on the power cord. Clocks and other fast switching digital signals should be shielded from the rest of the board by digital ground. Avoid crossover of digital and analog signals as much as possible. When the traces cross on opposite sides of the board, make sure they run at right angles to each other to reduce the effect of feedthrough through the board. The best board layout technique is microstrip, where the component side of the board is used only for the ground plane, and the signal traces are placed on the solder side. However, this is not always possible with 2-layer boards.

Dimensions