The HIP6012 is a DC-DC converter microprocessor application optimized for high performance. It is designed to drive an N-channel mosfet topology in two synchronously rectified bucks. The HIP6012 integrates all control, output, adjustment, monitoring and protection functions into one. The output voltage of the converter can be precisely regulated down to 1.27 volts with maximum tolerance. Temperature and line voltage variation ±1.5%. The HIP6012 provides simple, single feedback loop, fast transient response voltage mode control. It includes a 200kHz free-running triangle wave oscillator adjustable from below 50kHz to over 1MHz. The error amplifier features a 15MHz gain bandwidth product and 6V/µs slew rate, enabling high converter bandwidth fast transient performance. The resulting PWM duty cycle ranges from 0% to 100%. The HIP6012 operates by suppressing pulse width modulation. The HIP6012 monitors current by using the rDS(ON) of the upper MOSFET to eliminate the need for a current sense resistor.

feature

Driving two N-channel mosfets

Operates from +5V or +12V input

Simple single-loop control design

Voltage type PWM control

fast transient response

High Bandwidth Error Amplifier

Full 0% to 100% duty cycle

Excellent output voltage regulation

1.27V internal reference voltage

1.5% over line voltage and temperature

Overcurrent Fault Monitor

No additional current sensing element required

Use MOSFETs rDS (on)

Small converter size

Constant frequency operation

200kHz free-running oscillator programmable from

50 kHz to over 1 MHz

14-pin, SOIC and TSSOP packages

Lead-free available (RoHS compliant)

application

Pentium, Pentium Pro, PowerPC 8482 ; and

Alpha™ Microprocessor

High Power 5V to 3.xV DC-DC Regulator

Low Voltage Distributed Power

Note: Intersil lead-free products feature a special lead-free material jacket; molding compound/die attach material and 100% matte tin plate termination finish, RoHS compliant and compatible with both SnPb and lead-free soldering operations. Intersil lead-free products are classified as MSL meeting or exceeding the lead-free requirements of IPC/JEDEC J STD-020 at lead-free peak reflow temperatures.

CAUTION: Stresses exceeding those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation of the device under the above or any other conditions stated in the operating section of this specification is not implied.

Note: 1. θJA is measured with components mounted on a high-efficiency thermal conductivity test board in free air.

RT (Pin 1) This pin provides oscillator switching frequency adjustment. By connecting a resistor (RT) to ground from this pin, the nominal 200kHz switching frequency is based on the following equation:

Instead, connect the pull-up resistor (RT) of this pin to VCC according to the following equation:

The catenary (pin 2) connects the resistor (ROCSET) from this pin to the upper MOSFET. ROCSET, the internal 200µA current source (IOCS) and the upper MOSFET on-resistance (rDS(on)) are set according to the following equation:

Overcurrent trip cycle soft-start function. SS (pin 3) connects the capacitor to ground from this pin. This capacitor, along with the internal 10µA current source, sets the converter's soft-start interval. COMP (pin 4) and FB (pin 5) COMP and FB are wrong external pins available for the amplifier. The FB pin is the error inverting input to the amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the feedback loop of the voltage-controlled converter. EN (Pin 6) This pin is the open collector enable pin. Pull this pin below 1V to shut down the converter. When shutting down, the soft start pins are exhausted and the molar and amalgam pins remain low. Ground (Pin 7) The IC's signal ground. All voltage levels are used on this pin. Phase (Pin 8) connects the Phase pin to the upper MOSFET source. This pin is used to monitor the voltage drop across the MOSFET for overcurrent protection. This pin also provides a path back to the upper gate drive. Wear (pin 9) connects UGATE to the upper MOSFET gate. This pin provides gate drive for the upper MOSFET. Sheath (Pin 10) This pin provides the bias voltage for the upper MOSFET driver. A bootstrap circuit can be used to generate a bootstrap voltage suitable for driving standard N-channel MOSFETs.

PGND (Pin 11) This is the power ground connection. Tie the source of this pin of the MOSFET. LGATE (pin 12) connects LGATE to the lower MOSFET gate. This pin provides gate drive for the lower MOSFET. PVCC (Pin 13) provides the bias supply for the lower gate drive of this pin. VCC (pin 14) provides a 12V bias supply for the chip.

Function description: Initialization HIP6012 is automatically initialized after receiving power. No special sequencing of input power is required. A power-on reset (POR) function continuously monitors the input supply voltage and enable (EN) pin. Ball monitors the voltage on the VCC pin and the bias voltage at the input (VIN) on the OCSET pin. The level on OCSET is equal to the vehicle identification number minus the fixed voltage drop (see overcurrent protection). When the EN pin is held on VCC, the POR functions initiate soft-start operations after two input supply voltages exceed their POR thresholds. A single operation +12V supply, VIN and VCC are equivalent, and the +12V supply must exceed the VCC rising threshold before the POR begins to operate. Power-on-reset (POR) function inhibits operation when the chip is disabled (EN pin low). Both input supplies are above their POR thresholds, transitioning EN-pin high to start the soft-start interval. The soft-start POR function initiates a soft-start sequence. An internal 10µA current source to charge the external capacitor (CSS) is set to 4V on the SS pin. Soft start stuck error amplifier output (COMP pin) and reference input (+ terminal error amp) to SS pin voltage. Figure 3 shows the interval starting with CSS = 0.1 μF. The output voltage of the converter is initially clamped at the error amplifier (COMP pin). At t1 in Figure 3, the SS voltage reaches the triangle wave of the valley oscillator. The oscillator's triangular waveform is compared to a ramped error amplifier voltage. This produces wider and wider phase pulses to charge the output capacitors. This time increases the pulse width until t2. With sufficient output voltage, refer to the clamped output voltage on the input control. This is the interval between t2 and t3 Figure 3. At t3, the SS voltage exceeds the reference voltage and the output voltage is in regulation. This method provides fast and controllable output voltage rise.

overcurrent protection

The overcurrent function protects the converter from short circuiting the output using the resistors on the mosfet, rDS(on) to monitor the current. This approach enhances the efficiency of the inverter and reduces the cost of current sense resistors. Over-current function Cyclic soft-start function provides fault-protected hiccup mode. A resistor (ROCSET) programs the overcurrent trip level. An internal 200µA (typ) current sink produces a voltage on the ROCSET referring to the VIN. When the voltage through the upper MOSFET (also referred to as VIN) exceeds the voltage through ROCSET, the overcurrent function initiates a soft-start sequence. The soft-start function uses a 10µA current sink and inhibits PWM operation. The soft-start function recharges the CSS and then clamps to the SS voltage using an error amplifier. Should the overload occur while charging the CSS, the soft-start function completes its cycle by fully charging the CSS to 4V. Figure 4 shows this with an overload condition. Note that the inductor current increases beyond 15A during the CSS charge interval and causes an overcurrent trip. The converter consumes very little power with this method. The measured input power condition of Figure 4 is 2.5W.

The overcurrent function will trip on inductor current peaks (IPEAK) by: where IOCSET is the internal OCSET current source (200µA - typical). The change in the OC trigger point is mainly due to the rDS(ON) variant of the MOSFETs. To avoid overcurrent tripping within the normal operating load range, find the ROCSET resistor from the equation above:

1. Maximum RDS(ON) at maximum junction temperature.

2. Minimum IOCSET in spec sheet.

3. Decide, where ∏I is the output inductor ripple current. See the component guide titled "Output Inductor Selection" for the equation for ripple current. Small ceramic capacitors should be used with the ROCSET to smooth the voltage across the ROCSET with switching noise present on the input voltage.

Application Guide

Layout Considerations

In any high frequency switching converter, layout is very important. Switching current from one power supply device to another can trace the impedance of interconnecting bond wires and circuits. These interconnect impedances should be minimized by using wide and short printed circuit traces. This critical component should be as close as possible using a ground plane structure or single point ground. Figure 5 shows the converter. In order to minimize voltage overshoot, the interconnect lines represented by bold lines should be part of the ground plane or power plane in the printed circuit board. The parts shown in Figure 6 should be as close together as possible. Note that the capacitors CINCO each represent many physical capacitors. Positioning the HIP6012 within 3 inches of MOSFETs, Q1 Q2. The circuit traces the gate of the mosfet and the source connection from the HIP6012 must be sized to handle up to 1A peak current. Figure 6 shows that additional layout considerations are required. The structure of the circuit shown using a single point and a ground plane. Minimize leakage on the current path on the SS pin, and locate the capacitor, the CSS is only 10µA due to the internal current source. the VCC and ground pins. Place capacitors as close as possible to the start and phase pins.

feedback compensation

Figure 7 highlights a synchronous rectified buck converter. The output voltage (VOUT) is regulated to the reference voltage level. Error amplifier (error amplifier) output (VE/A) with oscillator (OSC) providing pulse width triangular wave modulation (PWM) wave, at the phase node. The output filter smoothes the PWM wave (LO and CO). The modulator transfer function is a function of the small signal transfer VOUT/VE/A. The function is controlled by DC gain and output filters (LO and CO) with a cut-off frequency at the bipolar FLC and zero at the FESR. The DC gain modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage

The compensation network consists of an error amplifier (inside the HIP6012) and impedance networks ZN and ZFB. The goal of the compensation network is a closed-loop transfer function frequency (f0dB) with a maximum 0dB crossover and sufficient phase margin. The phase margin is f0dB and 180o. The following equations relate to the compensation for the poles, zeros, and component gains of the network (R1, R2, R3, C1, C2, and C3 in Figure 8). Use these guidelines to locate the poles and zeros of the compensation network:

1. Pickup gain for desired converter bandwidth (R2/R1)

2. Place the first zero below the double pole of the filter (about 75% FLC)

3. Place a second zero at the filter's bipolar

4. Place the first pole at the ESR zero

5. Place 2 poles at half the switching frequency

6. Check the gain against the open loop gain of the error amplifier

7. Estimate Phase Margin - Repeat if necessary

Figure 8 shows an asymptotic plot of gain versus frequency for a DC-DC converter. The actual modulator gain has a high-gain output filter with a high Q-factor peak do, not shown in Figure 8. Using the above guidelines should give a compensation gain similar to the plotted curve. The open loop error amplifier gain limits the compensation gain. Check out the error-capable FP2 compensated gain amplifier. The closed loop gain is established logarithmically by adding the modulator gain (in dB) to the compensation gain (in dB). This is equivalent to the modulator transfer function to the compensation transfer function and plotting the gain.

The compensation gain provides a stable, high bandwidth (BW) overall loop using external impedance networks ZFB and ZN. Stable control loop with -20dB/decade slope, phase margin greater than 45o. in determining the phase margin. Component Selection Guidelines Output Capacitor Selection An output capacitor is required to filter output and supply load transient currents. Filtering requirements are a function of switching frequency and ripple current. The load transient requirement is a function of the rate of slew (di/dt) and the magnitude of the transient load current. These requirements are usually determined by capacitors and careful placement. Modern microprocessors generate more than 1A/sec. High-frequency capacitors initially provide a transient reduction in the current-carrying rate of bulk capacitors. Bulk filter capacitor values are usually dictated by effective series resistance and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close as possible to the power pins of the load. Be careful not to add inductance to the board layout that might cancel out the effects of these low inductance components. Consult the load's manufacturer for specific decoupling requirements. For example, Intel recommends that the Pentium Pro consist of at least forty (40) 1.0µF ceramic capacitors in a 1206 surface mount package. Use only dedicated low ESR capacitor switching regulators in bulk capacitor applications. The ESR of this bulk capacitor will determine the output ripple voltage and the initial voltage drop after high slew rate transients. The ESR value of an aluminum electrolytic capacitor is the same as in a larger case size, available in a lower ESR case size. However, their equivalent series inductance (ESL) capacitors increase with case size and can reduce the capacitor's contribution to high slew rate transient loads. Sadly, ESL is not a specified parameter. Check with your capacitor supplier and measure the impedance of the capacitor to select the appropriate component frequency. In most cases, a small multi-cell electrolytic capacitor performs better than a larger capacitor.

Output Inductor Selection The output inductor is selected to meet output voltage ripple requirements and minimize the converter's response load transient time. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations:

Increasing the inductance value reduces ripple current and voltage. However, larger inductor values can reduce the converter's response time to load transients. One of the parameters limiting the converter's response to load transients is the time it takes to change the inductor current. Given a fast enough control loop design the HIP6012 will provide 0% or 100% duty cycle in response to load transients. The response time is to convert the inductor current from the initial current value to the transient current level. During this time between the inductor current and the transient current must be powered by the output capacitor. Minimizing the response time minimizes the required output capacitance. Transient response time versus applied and removed loads. The following equations give approximate response time intervals. Apply and remove transient loads:

Where: ITRAN is the instantaneous load current step, tRISE is the response time to the loading application, and tFALL is the unloading response time. With a +5V input source, the worst-case response time can be in the application or depending on the output voltage setting, with the load removed. Be sure to check both equations for minimum and worst-case response times for maximum output levels. Input capacitor selection uses a hybrid input bypass capacitor to control voltage overshoot to the mosfet. Use small ceramic high frequency decoupling capacitors and bulk capacitors to provide the current required each time Q1 turns on. Place a small ceramic capacitor physically close to the mosfet between the drain of Q1 and the source of Q2. Important parameters for bulk input capacitors are the voltage rating and the rms current rating. For reliable operation, choose bulk capacitors with voltage and current ratings higher than the maximum input voltage and current required by the maximum rms circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum value. Input voltage and 1.5 times the rated voltage are conservative guidelines. The rms current rating requires approximately 1/2 the DC load current for the input capacitance of the buck regulator. For through-hole designs, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX may be required. For surface mount designs, solid tantalum capacitors can be used, but care must be taken regarding capacitor surge current ratings. These capacitors Must be able to power on. Both the TPS series offered by AVX and the series from 593DSprague are inrush current tested. MOSFET selection/notes Selection requirements and thermal management requirements. In high current applications, MOSFET power dissipation, packaging choice and heat sink are the main design factors. Power dissipation consists of two loss components; conduction loss and switching loss. This conduction loss is the largest component of power Losses in part of the upper and lower MOSFETs. These losses are distributed between the two MOSFETs according to the duty cycle (see equation below). Only the upper MOSFET has switching losses because the Schottky rectifier clamps the switch node before the rectifier turns on Where: D is the duty cycle = VO/VIN, tSW is the switching interval, and Fs is the switching frequency

These equations assume a linear voltage-current transition and cannot adequately model power losses due to reverse recovery of the body diodes of lower MOSFETs. This gate charge loss is dissipated by the HIP6012 instead of heating the mosfet. However, a large gate charge increases switching spacing and tSW increases MOSFET switching losses. Make sure both mosfets are within the maximum junction temperature range in high ambient according to the package thermal resistance specification. Individual heat sinks may be required depending on MOSFET power, package type, ambient temperature and air flow. Standard gate MOSFETs are generally recommended for use with the HIP6012. However, logic-level gate MOSFETs can be used in special cases. The input voltage, the upper gate drive level and the absolute gate-source voltage rating of the MOSFETs determine which logic level MOSFETs are suitable for. Figure 9 shows the bootstrap circuit from VCC. The boot capacitor produces a floating supply voltage pin relative to the phase. This supply is refreshed every cycle at VCC. When the MOSFET is low, the boot diode drop (VD) of Q2 turns on less. Logic stage MOSFETs should only be used with Q1MOSFETs whose absolute gate-source voltage rating exceeds the maximum voltage applied to VCC. For Q2, a logic level MOSFET can be used if its absolute gate voltage rating exceeds the maximum voltage. to PVCC

Figure 10 shows a direct connection to VCC. This option can only be used in converter systems with a main input voltage of +5 VDC or less. The highest gate-to-source voltage is approximately VCC less input supply. For +5V main power supply and +12V DC bias voltage, gate-to-source voltage A logic stage MOSFET is a good choice A logic stage MOSFET can be used for Q2 gate-to-source voltage ratings exceeding the maximum voltage for PVCC

Schottky-selective rectifier D2 is a dead-time swing between a clip with a negative inductance that turns off the lower MOSFET and turns on the upper MOSFET. The diodes must be Schottky-type anti-lossy parasitic MOSFET body diodes that do not conduct. Omitting the diode is acceptable to let the body diode of the lower MOSFET clamp the negative inductance swing, but the efficiency will drop a percent or two as a result. The diode's reverse breakdown voltage rating must be greater than the maximum input voltage.

HIP6012 DC-DC Converter Application Circuit The figure below shows the microprocessor application originally designed for the HIP6006 controller. Given the HIP6006 and HIP6012 controllers, the circuit can be modified using the HIP6012 controller. However, considering the extended reference voltage tolerance range, HIP6012-based converters may require additional output capacitance.