feature

Low power, minimum pin compatible, dual nanoDAC; AD5663R : 16-bit; AD5643R: 14-bit; AD5623R: 12-bit; user selectable external or internal reference; external reference default; on-chip 1.25 V/2.5 V, 5 ppm/ °C reference; 10-lead MSOP and 3 mm × 3 mm LFCSP; 2.7 V to 5.5 V supply; power-on reset by design to zero-scale guaranteed monotonicity; power down per channel; serial interface up to 50 MHz; hardware LDAC and CLR function.

application

Process Control; Data Acquisition Systems; Portable Battery-Powered Instruments; Digital Gain and Offset Adjustment; Programmable Voltage and Current Sources; Programmable Attenuators.

General Instructions

The AD5623R/AD5643R/AD5663R, nanoDAC 174 ; family of low-power, dual 12-, 14-, and 16-bit buffered voltage output digital-to-analog converters (DACs) operate from a single 2.7 V to 5.5 V supply and are guaranteed by design monotonous.

The AD5623R/AD5643R/AD5663R have an on-chip reference.

AD5623R-3/AD5643R-3/AD5663R-3 voltage is 1.25V, 5ppm/°C reference voltage, full-scale output 2.5V; AD5623R-5/AD5643R-5/AD5663R-5 reference voltage is 2.5V, 5ppm/°C , full-scale output 5V. The chip reference is turned off at power-up, allowing the use of an external reference; all devices operate from a single 2.7V to 5.5V supply. Open internal references by writing to the DAC.

These parts include a power-on-reset circuit that ensures the DAC output powers up to 0v and remains there until a valid write occurs. This part includes a power-down function that reduces the current consumption of the device to 480Na at 5V and provides a software-selectable output load in power-down mode.

The low power consumption of this part during normal operation makes it ideal for portable battery-operated devices.

The AD5623R/AD5643R/AD5663R use a general-purpose 3-wire serial interface that operates at clock frequencies up to 50 MHz, and they are compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards. On-chip precision output amplifiers achieve rail-to-rail output swing.

Product Highlights

1. Dual 12-bit, 14-bit and 16-bit DACs.

2. On-chip 1.25 V/2.5 V, 5 ppm/℃ benchmark.

3. 10-lead MSOP and 10-lead, 3 mm×3 mm LFCSP are available.

4. Low power; typically consumes 0.6mW at 3V and 1.25mW at 5V.

5. The maximum settling time of 4.5 μs is for the AD5623 R.

the term

Relative Accuracy or Integral Nonlinearity (INL) For DACs, relative accuracy or integral nonlinearity is the maximum deviation measured from a straight line in the LSBs through the endpoints of the DAC transfer function. Typical INL and code diagram.

Differential Nonlinearity (DNL)

Differential Nonlinearity (DNL) is the difference between the measured variation of any two adjacent codes and the ideal 1lsb variation. The specified differential nonlinearity ±1 LSB maximum guarantees monotonicity. The monotonicity of the DAC is guaranteed by design. Typical DNL and code diagram.

Zero scale error

Zero-scale error is a measure of the output error when the zero code (0x0000) is loaded into the DAC register. Ideally, the output should be 0 V. Since the output of the DAC cannot go below 0 V, the zero-scale error is always positive in the AD5623R/AD5643R/AD5663R. This is due to a combination of offset errors in the DAC and output amplifier. Zero-scale error is expressed in millivolts. Plot of zero-scale error versus temperature.

full scale error

Full-scale error is a measure of the output error when the full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be V-1 LSB. Full-scale error is expressed as a percentage of full-scale range. Plot of full-scale error versus temperature.

gain error

Gain error is a measure of DAC span error. It is the slope deviation of the DAC transfer characteristic from ideal, expressed as a percentage of the full-scale range.

Zero-scale error drift

Zero-scale error drift is a measure of the change in zero-scale error with temperature. It is expressed in microvolts per degree Celsius (µV/degree Celsius).

Gain temperature coefficient

Gain temperature coefficient is a measure of gain error as a function of temperature. Expressed in (ppm of full scale)/°C.

offset error

Offset error is the difference between V(actual) and V(ideal) in mV in the linear region of the measurement transfer function. The offset error is measured on the AD5623R/AD5643R/AD5663R and the DAC register is loaded with code 512. It can be negative or positive.

DC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to the change in VDD for the full-scale output of the DAC. The unit is decibel. VREF remains at 2v and VDD varies by ±10%.

Output voltage settling time

Output voltage settling time is the time required for the DAC output to settle to a specified level for a 1/4 to 3/4 full-scale input change, measured from the 24th falling edge of SCLK.

Digital-to-analog fault pulse

A pulse injected into the analog output when the input code in the DAC register changes state. It is usually specified as a fault area in nV sec and is measured when the digital input code is changed by 1lsb at the major carry transition (0x7FFF to 0x8000).

digital feedthrough

When the DAC output is not updating, measure the pulse injected from the DAC's digital input, digital feedthrough, into the DAC's analog output. It is measured in nV-sec by a full-scale code change on the data bus, i.e. from 0 to 1 and vice versa.

reference feedthrough

Reference feedthrough is when the ratio of the signal amplitude at the DAC output to the reference input is not updated (ie, LDAC is high) when the DAC outputs. It is expressed in decibels (decibels).

noise spectral density

Noise spectral density is a measure of internally generated random noise. Random noise is characterized by its spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring the noise at the output. Noise spectral density plot.

DC crosstalk

DC crosstalk is the DC change in the output level of one DAC as the output of another DAC changes. It is measured by the full-scale output change of one DAC (or soft power off and on) while monitoring the other DAC held at mid-scale. Expressed in microvolts (μV).

DC crosstalk caused by load current changes is a way to measure the effect of a change in load current on one DAC on another DAC held at midscale. It is expressed in microvolts per milliampere (µV/mA).

digital crosstalk

Digital crosstalk is a glitch pulse transmitted to the mid-scale output of one DAC in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of the other DAC. It is measured in standalone mode and is expressed in nanovolt seconds (nV seconds).

Analog crosstalk

Analog crosstalk is a glitch pulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading an input register and making a full-scale code change (from 0 to 1 and vice versa) while holding LDAC high. Then pulse the LDAC low and monitor the output of the DAC whose digital code has not changed. The fault area is expressed in nanovolt seconds (nV seconds).

DAC-to-DAC crosstalk

DAC-to-DAC crosstalk is a glitch pulse transferred to the output of one DAC due to a change in the digital code of one DAC and a subsequent change in the output of the other DAC. This includes digital and analog crosstalk. It is measured by loading a DAC with a full range code change (from 0 to 1 and vice versa) with LDAC low and monitoring the output of the other DAC. The energy of the fault is expressed in nanovolt seconds (nV seconds).

Double the bandwidth

Amplifiers within a DAC have limited bandwidth. Multiplying bandwidth is one measure. A sine wave on the reference appears in the output (loading the full-scale code to the DAC). The octave bandwidth is the frequency at which the output amplitude drops 3db below the input.

Total Harmonic Distortion (THD)

Total Harmonic Distortion is the difference between an ideal sine wave and an attenuated sine wave using a DAC. The sine wave is used as a reference for the DAC, and THD is a measure of the harmonics of the DAC's output. It is measured in decibels (decibels).

theory of operation

Digital-to-analog conversion part

The AD5623R/AD5643R/AD5663R DACs are fabricated using a CMOS process. The structure consists of a string DAC and an output buffer amplifier. Figure 49 shows a block diagram of the DAC architecture.

Because the input encoding of the DAC is straight binary, the ideal output voltage when using an external reference is given by:

The ideal output voltage when using the internal reference is given by:

Where: D is the load to the DAC register: 0 to 4095 (12-bit) for AD5623R 0 to 16383 (14-bit) for AD5643R 0 to 65535 (16-bit) for AD5663R N is the DAC resolution.

resistor string

The resistor string section is shown in Figure 50. It's just a string of resistors, each with a value of R. The code loaded into the DAC register determines at which node on the string the voltage is tapped into the output amplifier. The voltage is cut off by closing a switch to connect the string to the amplifier. Because it is a string of resistors, monotonicity is guaranteed.

output amplifier

The output buffer amplifier can generate rail-to-rail voltage at its output, the output range is 0v to V, can drive a 2kΩ load, and is connected in parallel with 1000pf to GND. The source and sink capabilities of the output amplifier are shown in Figure 31. The slew rate is 1.8v/µs, and the 1/4 to 3/4 full-scale settling time is 10µs.

internal reference

The AD5623R/AD5643R/AD5663R on-chip reference is turned off at power-up and enabled by writing to the control register. See the Internal Reference Settings section for details.

The AD5623R-3/AD5643R-3/AD5663R-3 have a 1.25V, 5ppm/°C reference and provide a 2.5V full-scale output The AD5623R-5/AD5643R-5/AD5663R-5 have a 2.5V, 5ppm/°C Voltage reference that provides a full-scale output of 5V. The internal reference voltage associated with each part is available from the V pin. A buffer is required if the reference output is used to drive an external load. When using the internal reference, it is recommended to place a 100 nF capacitor between the reference output and GND to maintain reference stability.

xref

The V pins on the AD5623R-3/AD5643R-3/AD5663R-3 and AD5623R-5/AD5643R-5/AD5663R-5 allow external references to be used if required by the application. The on-chip reference is turned off at power-up, which is the default condition. The AD5623R-3/AD5643R-3/AD5663R-3 and AD5623R-5/AD5643R-5/AD5663R-5 can operate from a single 2.7 V to 5.5 V supply.

serial interface

The AD5623R/AD5643R/AD5663R feature a 3-wire serial interface (SYNC, SCLK, and DIN) with SPI, QSPI, and MICROWIRE interface standards, as well as most DSPs. A timing diagram of a typical write sequence is shown in Figure 2.

Pull the sync line low at the beginning of the write sequence. Data enters the 24-bit shift register from the data line on the falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the AD5623R/AD5643R/AD5663R compatible with high-speed digital signal processors. On the 24th falling clock edge, the last data bit is clocked and a programming function is performed, such as a change in the contents of a DAC register and/or a change in operating mode.

During this phase, the sync line can be held low or high. In either case, it must be turned up at least 15 ns before the next write sequence so that the falling edge of sync can initiate the next write sequence. Because the sync buffer draws more current when VIN=2v and VIN=0.8V, the sync should be in the sequence for lower power operation. Before that, however, it must be raised again for the next write sequence.

input shift register

The width of the input shift register is 24 bits (see Figure 52). The first time both didn't care. The next three are command bit C2 to command bit C0 (see Table 8), then the 3-bit DAC address A2 to DAC address A0 (see Table 9), and finally the 16-, 14-, and 12-bit data words. The data word consists of a 16-, 14-, and 12-bit input code followed by 0, 2, or 4 bits, which do not matter for the AD5663R, which are the AD5643R and AD5623R, respectively (see Figure 51, Figure 52, and Figure 53). Data bits are transferred to the DAC register on the 24th falling edge of SCLK.

Sync outage

In a normal write sequence, the sync line has at least 24 falling edges on SCLK and the DAC on the 24th falling edge. However, if on the 24th falling edge, the write sequence is interrupted. The shift register is reset and the write sequence is considered invalid. Neither the DAC register contents are updated nor the operating mode change (see Figure 54).

power-on reset

The AD5623R/AD5643R/AD5663R contain a power-on reset circuit that controls the output voltage during power-up. The AD5623R/AD5643R/AD5663R DACs have output power up to 0V and the output remains there until a valid write sequence to the DAC. This is useful in applications where it is important to know the state of the output of the DAC during power up. Any event on LDAC or CLR during power-on reset is ignored.

software reset

The AD5623R/AD5643R/AD5663R include a software reset function. Command 101 is reserved for the software reset function (see Table 8). The software reset command contains two reset modes, which are software programmable by setting bit DB0 in the control register. Table 10 shows how the state of the bits corresponds to the operating mode of the device. Table 12 shows the contents of the input shift register during the software reset mode of operation.

After a full software reset (Db0=1), there must be a short delay, about 5 seconds, to allow the reset to complete. During reset, a low pulse can be observed on the CLR line. If the next SPI transaction starts before the CLR line returns high, the SPI transaction is ignored.

Power down mode

The AD5623R/AD5643R/AD5663R contain four independent modes of operation. Command 100 is reserved for the power down function (see Table 8). These modes are software programmable by setting Bit DB5 and Bit DB4 in the control register. Table 11 shows how the state of the bits corresponds to the operating mode of the device. Any or all DACs (DAC B and DAC A) can be powered down to the selected mode by setting the corresponding two bits (Bit DB1 and Bit DB0) to 1.

By executing the same command 100, any combination of dacs can be started by setting bits DB5 and DB4 to normal operating mode.

Likewise, to select the combination of DAC channels to power up, set the corresponding bits (Bit DB1 and Bit DB0) to 1. The contents of the input shift register during power-down/power-up operations are shown in Table 13. When LDAC is low, the DAC output power reaches the value in the input register. If LDAC is high, the DAC output will power up to the value held in the DAC register prior to power down.

When both bit DB1 and bit DB2 are set to 0, the part operates normally and its normal power consumption is 250 microamps (5 volts). However, for the three power-down modes, the supply current drops to 480mA at 5V (200mA at 3V). Not only does the supply current drop, but the output stage also switches from inside the amplifier's output to a network of resistors of known value. The advantage of this is that the output impedance of the component is known when the component is in power down mode. The output can be internally connected to ground through a 1 kΩ or 100 kΩ resistor, or left open (three states) (see Figure 55).

When the power-down mode is activated, the bias generator, output amplifier, resistor string and other associated linear circuits are turned off. However, when powered down, the contents of the DAC registers are not affected. The power-off time is typically 4 Vs for VDD=5 V and VDD=3 V.

LDAC function

The AD5623R/AD5643R/AD5663R DACs have a double-buffered interface consisting of two sets of registers: the input register and the DAC register. The input registers are connected directly to the input shift registers, and the digital code is transferred to the associated input register upon completion of a valid write sequence. The DAC register contains the digital code used by the resistor string. Access to the DAC registers is controlled by the LDAC pin.

When the LDAC pin is high, the DAC registers are locked and the input registers can change state without affecting the contents of the DAC register. However, when LDAC is lowered, the DAC registers become transparent and the contents of the input registers are transferred to them. The double-buffered interface is useful if the user needs to update all DAC outputs simultaneously. The user can write to one input register individually, then, when writing to the other DAC input register, by lowering LDAC, all outputs will be updated simultaneously.

These sections all contain the additional feature that the DAC registers are not updated unless the input registers have been updated since the last time LDAC was low. Normally, when LDAC is low, the DAC register is filled with the contents of the input register. In the case of the AD5623R/AD5643R/AD5663R, the DAC register is updated only if the input register has changed since the last time the DAC register was updated, thereby eliminating unwanted digital crosstalk.

The outputs of all DACs can be updated simultaneously, using the hardware LDAC pins.

The synchronous LDAC is on the falling edge of the 24th SCLK pulse. As shown in Figure 2, LDAC can be permanently low or pulsed.

Asynchronous LDAC

The output is not updated while writing to the input register. When LDAC goes low, the DAC register is updated with the contents of the input register.

The LDAC register provides the user with complete flexibility and control over the hardware LDAC pins. This register allows the user to select a combination of channels that are updated simultaneously when the hardware LDAC pin is executed. Setting the LDAC bit register for a DAC channel to 0 means that the update of that channel is controlled by the LDAC pin. If this bit is set to 1, the channel is updated synchronously; that is, the DAC register is updated after new data is read, regardless of the state of the LDAC pin. It effectively pulls the LDAC pin low.

See Table 15 for the LDAC register operating modes. This flexibility is useful in applications where the user wishes to simultaneously update the selected channel while the remaining channels are updated synchronously.

Write to the DAC using Command 110 to load the 2-bit LDAC registers[DB1:DB0]. The default value for each channel is 0; that is, the LDAC pin is functioning properly. Setting the bit to 1 means that the DAC register is updated regardless of the state of the LDAC pin. During the LDAC register set command, the input shift register.

Internal reference settings

By default, the on-chip reference is turned off at power-up. This reference can be turned on or off by setting software programmable bit DB0 in the control register. Table 16 shows how the state of the bits corresponds to the operating mode.

Microprocessor interface

AD5623R/AD5643R/AD5663R T-Type o Blackfin® Microprocessor Interface

Figure 56 shows the serial interface between the AD5623R/AD5643R/AD5663R and a blackfin microprocessor such as the ADSP-BF531. The ADSP-BF531 contains two dual-channel synchronous serial ports SPORT1 and SPORT0 for serial and multiprocessor communications. Use SPORT0 to connect to the AD5623R/AD5643R/AD5663R with the following interface setup: DT0PRI drives the DIN pins of the AD5623R/AD5643R/AD5663R, while TSCLK0 drives the part's SCLK. Synchronization is driven by TFS0.

AD5623R/AD5643R/AD5663R to 68HC11/68L11 Interface

Figure 57 shows the serial interface between the AD5623R/AD5643R/AD5663R and the 68HC11/68L11 microcontroller.

The SCK of the 68HC11/68L11 drives the SCLK of the AD5623R/AD5643R/AD5663R, and the MOSI output drives the serial data line of the DAC.

The sync signal comes from the port line (PC7). The setup conditions for this interface to operate correctly are as follows: The 68HC11/68L11 is configured with the CPOL bit at 0 and the CPHA bit at 1. When data is transferred to the DAC, the sync line is taken low (PC7). When the 68HC11/68L11 is configured as described above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data for the 68HC11/68L11 is transferred in 8-bit bytes with only 8 falling clock edges during the transfer cycle.

The data MSB is transferred first. To load data into the AD5623R/AD5643R/AD5663R, after the first 8 bits have been transferred, PC7 is held low and a second serial write is performed to the DAC. At the end of this routine, PC7 is set to a high value.

AD5623R/AD5643R/AD5663R T-Type o 80C51/80L51 Interface

Figure 58 shows the serial interface between the AD5623R/AD5643R/AD5663R and the 80C51/80L51 microcontroller. The interface setup is as follows: The TxD of the 80C51/80L51 drives the SCLK of the AD5623R/AD5643R/AD5663R and RxD, which drives the serial data line of the part. The sync signal again comes from the bit programmable pins on the port. In this case, use port line P3.3. When data is to be transferred to the AD5623R/AD5643R/AD5663R, P3.3 is taken low. The 80C51/80L51 only transmits data in 8-bit bytes; therefore, only 8 falling clock edges occur during the transmit cycle. To load data into the DAC, P3.3 is held low after the first 8 bits have been sent and a second write cycle is initiated to send the second byte of data. P3.3 rises after this cycle is completed.

The 80C51/80L51 outputs serial data in a format with LSB first. The AD5623R/AD5643R/AD5663R must receive data with the MSB first. The 80C51/80L51 transfer routines should take this into account.

AD5623R/AD5643R/AD5663R T-Type o Microwire Interface

Figure 59 shows the interface between the AD5623R/AD5643R/AD5663R and any Microwire compatible device. Serial data is shifted out on the falling edge of the serial clock and into the AD5623R/AD5643R/AD5663R on the rising edge of SK.

application information

Use the reference as a power source

Since the supply current required by the AD5623R/AD5643R/AD5663R is extremely low, another option is to use a voltage reference to supply the required voltage to the part (see Figure 60). This is especially useful if the power supply is noisy, or if the system supply voltage is not 5 V or 3 V, such as 15 V. The voltage reference outputs the regulated supply voltage for the AD5623R/AD5643R/AD5663R. If the low-loss REF195 is used, the AD5623R/AD5643R/AD5663R must be supplied with 500µA of current to load the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply current to the load. The total current required (with a 5 kΩ load on the DAC output) is:

The load regulation of the REF195 is typically 2ppm/mA, which results in a 3ppm (15µV) error in the 1.5ma current drawn from it. This corresponds to a 0.196 LSB error for the 16-bit AD5663R.

Bipolar Operation Using the AD5663R

The AD5663R is designed for single-supply operation, but a bipolar output range can also be achieved using the circuit in Figure 61. The output voltage range of this circuit is ±5 V. Using the AD820 or OP295 as the output amplifier enables rail-to-rail operation at the output of the amplifier.

The output voltage of any input code can be calculated as follows:

where D represents the input code in decimal (0 to 65535). When V=5 V, R1=R2=10 kΩ,

This is an output voltage range of ±5 V, 0x0000 corresponds to -5 V output and 0xFFFF corresponds to +5 V output.

Using AD5663R with Galvanically Isolated Interface

In process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the control circuit from any dangerous common-mode voltages that may be present within the DAC's operating area. iCoupler® provides isolation in excess of 2.5 kV. The AD5663R uses a 3-wire serial logic interface, so the ADuM1300 3-channel digital isolator provides the required isolation (see Figure 62). The power supply to this part also needs to be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V required by the AD5663R.

Power Bypass and Ground

When accuracy is important in a circuit, it is helpful to carefully consider the power and ground return layout on the board. A printed circuit board containing the AD5663R should have separate analog and digital sections, each with its own board area.

If the AD5663R is in a system where other devices require an AGND to DGND connection, it should only be connected at one point. This ground point should be as close as possible to the AD5663R.

The supply to the AD5663R should be bypassed with 10µF and 0.1µF capacitors. Capacitors should be placed as close to the device as possible, ideally a 0.1µF capacitor should be placed close to the device. The 10µF capacitors are of the tantalum bead type. Importantly, 0.1µF capacitors must have low effective series resistance (ESR) and effective series inductance (ESI), such as can be found in common ceramic type capacitors.

This 0.1µF capacitor provides a low impedance path to ground for high frequencies due to transient currents caused by internal logic switches.

The power cord itself should have as large a trace as possible to provide a low impedance path and reduce the impact of faults on the power cord. Clocks and other fast switching digital signals should be shielded from the rest of the board by digital ground. Avoid crossover of digital and analog signals as much as possible. When the traces cross on opposite sides of the board, make sure they run at right angles to each other to reduce the effect of feedthrough through the board. The best board layout technique is microstrip, where the component side of the board is used only for the ground plane, and the signal traces are placed on the solder side. However, this is not always possible with 2-layer boards.

Dimensions